KR980005609A - Method of forming a contact of a semiconductor device - Google Patents

Method of forming a contact of a semiconductor device Download PDF

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Publication number
KR980005609A
KR980005609A KR1019960025725A KR19960025725A KR980005609A KR 980005609 A KR980005609 A KR 980005609A KR 1019960025725 A KR1019960025725 A KR 1019960025725A KR 19960025725 A KR19960025725 A KR 19960025725A KR 980005609 A KR980005609 A KR 980005609A
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KR
South Korea
Prior art keywords
conductive wiring
forming
contact
contact hole
lower conductive
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KR1019960025725A
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Korean (ko)
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KR100200307B1 (en
Inventor
김현수
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019960025725A priority Critical patent/KR100200307B1/en
Publication of KR980005609A publication Critical patent/KR980005609A/en
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Publication of KR100200307B1 publication Critical patent/KR100200307B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 콘택 형성방법에 관한 것으로, 반도체 기판의 주변회로부는 게이트전극을 하부 도전배선으로 콘택홀을 형성하고 상기 콘택홀을 매립하는 상부 도전배선 형성공정으로 콘택을 형성하는 방법에 있어서, 상기 반도체 기판 상부에 텅스텐 폴리사이드로 하부 도전배선을 형성하고 상기 하부 도전배선 상부에 하부절연층을 형성한 다음, 상기 하부절연층을 식각하되, 콘택 마스크를 이용하여 상기 하부 도전배선을 노출시키는 콘택홀을 형성하고 상기 콘택홀을 상부 도전배선으로 매립하되, 상기 상부 도전배선을 매립하는 증착 챔버를 고온의 수소가스분위기로 열처리하여 상기 콘택홀 저부의 하부 도전배선에 형성된 자연산화막을 완전히 제거한 다음에 실시함으로써 콘택을 용이하게 형성하게 반도체 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체 소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a contact of a semiconductor device, in which a peripheral circuit portion of a semiconductor substrate is formed by forming a contact hole with a lower conductive wiring in a gate electrode, Forming a lower conductive wiring with tungsten polycide on the semiconductor substrate, forming a lower insulating layer on the lower conductive wiring, etching the lower insulating layer, exposing the lower conductive wiring using a contact mask, A contact hole is formed and the contact hole is filled with an upper conductive wiring. The deposition chamber in which the upper conductive wiring is buried is heat treated in a high temperature hydrogen gas atmosphere to completely remove the natural oxide film formed in the lower conductive wiring of the contact hole bottom The characteristics and the reliability of the semiconductor device are improved so that the contact can be easily formed. Phase was a technique that enables high integration of the semiconductor device thereof.

Description

반도체 소자의 콘택 형성방법Method of forming a contact of a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성방법을 도시한 단면도.FIG. 2 is a cross-sectional view illustrating a method of forming a contact of a semiconductor device according to an embodiment of the present invention. FIG.

Claims (7)

반도체 기판의 주변회로부는 게이트전극을 하부 도전배선으로 콘택홀을 형성하고 상기 콘택홀을 매립하는 상부 도전배선 형성공정으로 콘택을 형성하는 방법에 있어서, 상기 반도체 기판 상부에 텅스텐 폴리사이드로 하부 도전배선을 형성하는 공정과, 상기 하부 도전배선 상부에 하부절연층을 형성하는 공정과, 상기 하부절연층을 식각하되, 콘택마스크를 이용하여 상기 하부도전배선을 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 상부 도전배선으로 매립하되, 상기 상부 도전배선을 매립하는 증착챔버를 고온의 수소가스 분위기로 열처리하여 상기 콘택홀 저부의 하부 도전배선에 형성된 자연산화막을 완전히 제거한 다음 매립공정을 실시함으로써 콘택홀 형성하는 공정을 포함하는 반도체소자의 콘택 형성방법.A method of forming a contact in a peripheral circuit portion of a semiconductor substrate by forming a contact hole with a lower conductive wiring and filling the contact hole with a gate electrode, the method comprising the steps of: forming a tungsten polycide on the semiconductor substrate, Forming a lower insulating layer on the lower conductive wiring; etching the lower insulating layer to form a contact hole exposing the lower conductive wiring using a contact mask; The contact hole is filled with the upper conductive wiring and the deposition chamber in which the upper conductive wiring is buried is heat treated in a high temperature hydrogen gas atmosphere to completely remove the natural oxide film formed in the lower conductive wiring of the bottom portion of the contact hole, And forming a hole in the contact hole. 제1항에 있어서, 상기 하부 도전배선과 상부 도전배선은 텅스텐 폴리사이드로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method according to claim 1, wherein the lower conductive wiring and the upper conductive wiring are formed of tungsten polycide. 제1항 또는 제2항에 있어서, 상기 하부 도전배선은 셀부와 주변회로부를 갖는 반도체기판으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method for forming a contact of a semiconductor device according to claim 1 or 2, wherein the lower conductive wiring is formed of a semiconductor substrate having a cell portion and a peripheral circuit portion. 제1항에 또는 제2항에 있어서, 상기 상부 도전배선은 폴리사이드와 유사한 특성을 갖는 물질로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1 or 2, wherein the upper conductive interconnection is formed of a material having properties similar to polycides. 제4항에 있어서, 상기 상부 도전배선은 Ti/TiN/W.Ti/TiN/Al.Ti/WN/W 또는 WN/W의 적층 구조로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법5. The method for forming a contact of a semiconductor device according to claim 4, wherein the upper conductive wiring is formed of a laminated structure of Ti / TiN / W.Ti / TiN / Al.Ti / WN / W or WN / W 제1항에 있어서, 상기 열처리 공정은 습식방법으로 상기 자연산화막을 제거하고 실시하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method according to claim 1, wherein the annealing process is performed by removing the natural oxide film by a wet process. 제1항에 있어서, 상기 열처리 공정은 400~700℃ 정도의 온도에서 실시하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method according to claim 1, wherein the heat treatment is performed at a temperature of about 400 to 700 ° C. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025725A 1996-06-29 1996-06-29 Method for forming a contact of a semiconductor device KR100200307B1 (en)

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Application Number Priority Date Filing Date Title
KR1019960025725A KR100200307B1 (en) 1996-06-29 1996-06-29 Method for forming a contact of a semiconductor device

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Application Number Priority Date Filing Date Title
KR1019960025725A KR100200307B1 (en) 1996-06-29 1996-06-29 Method for forming a contact of a semiconductor device

Publications (2)

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KR980005609A true KR980005609A (en) 1998-03-30
KR100200307B1 KR100200307B1 (en) 1999-06-15

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