KR100260521B1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
KR100260521B1
KR100260521B1 KR1019970079264A KR19970079264A KR100260521B1 KR 100260521 B1 KR100260521 B1 KR 100260521B1 KR 1019970079264 A KR1019970079264 A KR 1019970079264A KR 19970079264 A KR19970079264 A KR 19970079264A KR 100260521 B1 KR100260521 B1 KR 100260521B1
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South Korea
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layer
lower layer
contact hole
semiconductor device
forming
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KR1019970079264A
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Korean (ko)
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KR19990059067A (en
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김학묵
김진태
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve the characteristics of the device, by lowering a contact resistance with varying the characteristics of a foreign substance layer formed on a surface of a bottom layer into a conductor. CONSTITUTION: A bottom layer(12) of W-polycide structure is formed on a substrate(11). An interlayer insulation film(13) is formed on the whole structure including the bottom layer. A contact hole where the bottom layer is revealed is formed by etching a selected part of the interlayer insulation film with an etching process using a photoresist film as a mask layer. The photoresist film is removed with an oxygen plasma etching process, and during the oxygen plasma etching process, a foreign substance layer is formed on the surface of the bottom layer. The foreign substance layer is varied to a conductive conductor(15A) by performing a high temperature thermal annealing process. After performing a cleaning process using an HF solution or a BOE solution, a top layer(16) contacted with the bottom layer through the contact hole is formed.

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 제조 공정중 하부층이 텅스텐 폴리사이드(W-polycide) 구조로 형성되고, 이러한 하부층이 콘택홀을 형성 과정에서 플라즈마 식각 분위기에 노출되면서 표면에 형성되는 이물질층(예를 들어, 텅스텐 화합물; WOx)을 고온 열처리로 금속성 도체로 그 특성을 변화시켜 콘택 저항을 낮추므로써, 제품의 특성을 향상시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a lower layer is formed of a tungsten polycide (W-polycide) structure during a manufacturing process of a semiconductor device, and the lower layer is exposed to a plasma etching atmosphere during the formation of a contact hole. The present invention relates to a method for manufacturing a semiconductor device capable of improving the characteristics of a product by lowering contact resistance by changing a property of a foreign material layer (for example, tungsten compound; WOx) to a metallic conductor by high temperature heat treatment.

일반적으로, 반도체 소자의 제조 공정중 전극 형성 공정에 있어, 전극의 도전성을 증대시키기 위해 폴리실리콘층과 텅스텐 실리사이드층이 적층된 텅스텐 폴리사이드 구조가 널리 적용되고 있다.In general, a tungsten polyside structure in which a polysilicon layer and a tungsten silicide layer are laminated is widely used in an electrode forming step of a semiconductor device manufacturing process to increase the conductivity of an electrode.

도 1(a) 및 도 1(b)는 텅스텐 폴리사이드 구조가 적용되는 종래 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device to which a tungsten polyside structure is applied.

도 1(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(1)상에 폴리실리콘과 텅스텐 실리사이드가 적층된 텅스텐 폴리사이드 구조의 하부층(2)이 형성된다. 하부층(2)을 포함한 전체 구조상에 층간 절연막(3)이 형성된다. 층간 절연막(3)의 선택된 부분을 식각 하여 하부층(2)이 노출되는 콘택홀(4)이 형성된다. 콘택홀(4)은 감광막을 마스크층으로 한 식각 공정으로 형성되고, 이후에 감광막을 제거하여야 하는데, 이때 산소 플라즈마 식각 공정으로 감광막을 제거하게 된다. 산소 플라즈마 식각 공정시에 콘택홀(4)을 저면을 이루는 텅스텐 폴리사이드 구조의 하부층(2)의 표면에 이물질층(5)이 형성된다. 이물질층(5)은 하부층(2)의 텅스텐 이온과 플라즈마 식각 분위기 가스인 산소 이온이 반응하여 텅스텐 화합물(WOx)이 생성되어 형성된다.Referring to FIG. 1A, a lower layer 2 of a tungsten polyside structure in which polysilicon and tungsten silicide are stacked is formed on a substrate 1 having a structure in which various elements for forming a semiconductor device are formed. An interlayer insulating film 3 is formed on the entire structure including the lower layer 2. Selected portions of the interlayer insulating layer 3 are etched to form contact holes 4 through which the lower layer 2 is exposed. The contact hole 4 is formed by an etching process using the photoresist film as a mask layer, and then the photoresist film should be removed. In this case, the photoresist film is removed by an oxygen plasma etching process. During the oxygen plasma etching process, the foreign material layer 5 is formed on the surface of the lower layer 2 of the tungsten polyside structure forming the bottom of the contact hole 4. The foreign material layer 5 is formed by reacting tungsten ions of the lower layer 2 with oxygen ions, which are plasma etching atmosphere gases, to generate a tungsten compound (WOx).

도 1(b)를 참조하면, 콘택 저항을 낮추기 위해 HF 용액이나 BOE 용액을 사용하여 세정 공정을 실시한 후에 콘택홀(4)을 통해 하부층(2)과 접촉되는 상부층(6)을 형성한다. 상부층(6)은 폴리실리콘 또는 폴리실리콘/텅스텐 실리사이드로 형성된다.Referring to FIG. 1B, after the cleaning process is performed using an HF solution or a BOE solution in order to lower contact resistance, an upper layer 6 contacting the lower layer 2 is formed through the contact hole 4. The top layer 6 is formed of polysilicon or polysilicon / tungsten silicide.

상기한 공정에서, 콘택홀(4)의 저면을 이루는 하부층(2)의 표면에 플라즈마 식각 분위기에 의한 텅스텐 화합물로 된 이물질층(5)이 형성되는데, 이 이물질층(5)은 HF 용액 또는 BOE 용액으로 완벽하게 제거되지 않아, 도 1(B)에 도시된 바와 같이, 하부층(2)과 상부층(6)의 콘택 부분에 남아있게 된다. 이로 인하여 하부층(2)과 상부층(6)의 콘택 저항이 증가되어, 예를 들어, 수십 ΚΩ 의 저항을 갖게되어 제품을 정상적으로 작동시킬 수 없게 된다. 도 2는 하부층(2)과 상부층(6)의 콘택 부분에 이물질층(5)이 존재하는 것을 보여주는 사진이다.In the above process, a foreign matter layer 5 made of a tungsten compound by a plasma etching atmosphere is formed on the surface of the lower layer 2 forming the bottom of the contact hole 4, and the foreign matter layer 5 is formed of HF solution or BOE. Not completely removed in solution, as shown in FIG. This increases the contact resistance of the lower layer 2 and the upper layer 6, for example, several tens. ΚΩ The resistance of the product will prevent the product from operating normally. 2 is a photograph showing that the foreign material layer 5 is present in the contact portion of the lower layer 2 and the upper layer 6.

따라서, 본 발명은 반도체 소자의 제조 공정중 하부층이 텅스텐 폴리사이드(W-polycide) 구조로 형성되고, 이러한 하부층이 콘택홀을 형성 과정에서 플라즈마 식각 분위기에 노출되면서 표면에 형성되는 이물질층을 금속성 도체로 그 특성을 변화시켜 콘택 저항을 낮추므로써, 제품의 특성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a metallic conductor having a lower layer formed of a tungsten polycide (W-polycide) structure during the manufacturing process of a semiconductor device, and the lower layer being exposed to a plasma etching atmosphere in the process of forming a contact hole. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the characteristics of a product by changing the characteristics of the contact to lower the contact resistance.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상에 폴리실리콘과 텅스텐 실리사이드가 적층된 텅스텐 폴리사이드 구조의 하부층을 형성하는 단계; 상기 하부층을 포함한 전체 구조상에 층간 절연막을 형성하고, 상기 층간 절연막의 선택된 부분을 식각 하여 하부층이 노출되는 콘택홀을 형성하는 단계; 상기 콘택홀 저면을 이루는 상기 하부층의 표면에 형성된 텅스텐 화합물로 된 이물질층을 고온 열처리 공정으로 금속성 도체로 변화시키는 단계; 및 상기 콘택홀을 세정한 후, 상기 콘택홀을 통해 상기 하부층과 접촉되는 상부층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming a lower layer of a tungsten polyside structure in which polysilicon and tungsten silicide are stacked on a substrate having a structure in which various elements are formed; Forming an interlayer insulating film on the entire structure including the lower layer, and etching a selected portion of the interlayer insulating film to form a contact hole through which the lower layer is exposed; Converting a foreign material layer of a tungsten compound formed on a surface of the lower layer forming the bottom of the contact hole into a metallic conductor by a high temperature heat treatment process; And after cleaning the contact hole, forming an upper layer in contact with the lower layer through the contact hole.

도 1(a) 및 도 1(b)는 종래 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.

도 2는 도 1(b)에 도시된 콘택 부분의 사진.Figure 2 is a photograph of the contact portion shown in Figure 1 (b).

도 3(a) 내지 도 3(c)는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.3A to 3C are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 4는 도 3(b)의 열처리 온도의 변화에 따른 콘택 저항의 특성 변화를 나타낸 그래프.4 is a graph showing a change in characteristics of the contact resistance according to the change in the heat treatment temperature of FIG.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 및 11: 기판 2 및 12: 하부층1 and 11: Substrate 2 and 12: lower layer

3 및 13: 층간 절연막 4 및 14: 콘택홀3 and 13: interlayer insulating film 4 and 14: contact hole

5 및 15: 이물질층 15A: 금속성 도체5 and 15: foreign material layer 15A: metallic conductor

6 및 16: 상부층6 and 16: top layer

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3(a) 내지 도 3(c)는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.3A to 3C are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11)상에 폴리실리콘과 텅스텐 실리사이드가 적층된 텅스텐 폴리사이드 구조의 하부층(12)이 형성된다. 하부층(12)을 포함한 전체 구조상에 층간 절연막(13)이 형성된다. 층간 절연막(13)의 선택된 부분을 식각 하여 하부층(12)이 노출되는 콘택홀(14)이 형성된다. 콘택홀(14)은 감광막을 마스크층으로 한 식각 공정으로 형성되고, 이후에 감광막을 제거하여야 하는데, 이때 산소 플라즈마 식각 공정으로 감광막을 제거하게 된다. 산소 플라즈마 식각 공정시에 콘택홀(14)을 저면을 이루는 텅스텐 폴리사이드 구조의 하부층(12)의 표면에 이물질층(15)이 형성된다. 이물질층(15)은 하부층(12)의 텅스텐 이온과 플라즈마 식각 분위기 가스인 산소 이온이 반응하여 텅스텐 화합물(WOx)이 생성되어 형성된다.Referring to FIG. 3A, a lower layer 12 of a tungsten polyside structure in which polysilicon and tungsten silicide are stacked is formed on a substrate 11 having various elements for forming a semiconductor device. An interlayer insulating film 13 is formed on the entire structure including the lower layer 12. A selected portion of the interlayer insulating layer 13 is etched to form a contact hole 14 through which the lower layer 12 is exposed. The contact hole 14 may be formed by an etching process using the photoresist as a mask layer, and then the photoresist may be removed. The photoresist may be removed by an oxygen plasma etching process. During the oxygen plasma etching process, the foreign material layer 15 is formed on the surface of the lower layer 12 of the tungsten polyside structure forming the bottom of the contact hole 14. The foreign material layer 15 is formed by reacting tungsten ions of the lower layer 12 with oxygen ions, which are plasma etching atmosphere gases, to generate a tungsten compound (WOx).

도 3(b)를 참조하면, 고온 열처리 공정을 실시하여 텅스텐 화합물로 된 이물질층(15)을 금속성 도체(15A)로 변화시킨다.Referring to FIG. 3B, a high temperature heat treatment process is performed to change the foreign material layer 15 made of a tungsten compound into a metallic conductor 15A.

상기에서, 고온 열처리 공정은 400 내지 1100℃의 온도에서 수 내지 수십 초간 실시한다. 최고 온도는 이미 형성된 소자에 영향을 미치지 않는 범위 내에서 설정할 수 있다.In the above, the high temperature heat treatment process is carried out for several to several tens of seconds at a temperature of 400 to 1100 ℃. The maximum temperature can be set within a range that does not affect the devices already formed.

도 3(c)를 참조하면, 자연 산화막 등 콘택 저항을 증가시킬 수 있는 요인들을 제거하기 위해 HF 용액이나 BOE 용액을 사용하여 세정 공정을 실시하고, 이후 콘택홀(14)을 통해 하부층(12)과 접촉되는 상부층(16)을 형성한다. 상부층(16)은 폴리실리콘, 폴리실리콘/텅스텐 실리사이드 또는 도전성 금속 물질로 형성된다.Referring to FIG. 3 (c), a cleaning process is performed using HF solution or BOE solution to remove factors that may increase contact resistance such as a natural oxide film, and then the lower layer 12 through the contact hole 14. Forming an upper layer 16 in contact with it. Top layer 16 is formed of polysilicon, polysilicon / tungsten silicide, or a conductive metal material.

상기한 공정에서, 콘택홀(14)의 저면을 이루는 하부층(12)의 표면에 플라즈마 식각 분위기에 의한 형성된 텅스텐 화합물로 된 이물질층(15)은 열처리에 의해 금속성 도체(15A)로 변하게 되어 이후에 형성되는 상부층(16)과의 콘택 저항이 감소하게 된다.In the above process, the foreign material layer 15 made of a tungsten compound formed by the plasma etching atmosphere on the surface of the lower layer 12 forming the bottom of the contact hole 14 is changed into the metallic conductor 15A by heat treatment. The contact resistance with the upper layer 16 to be formed is reduced.

도 4는 도 3(b)의 열처리 온도의 변화에 따른 하부층(12)과 상부층(16)사이의 콘택 저항의 특성 변화를 나타낸 그래프로서, 열처리 온도가 높은 수록 수백 Ω 정도로 저항이 낮아지는 것을 알 수 있다.FIG. 4 is a graph illustrating a change in characteristics of the contact resistance between the lower layer 12 and the upper layer 16 according to the change of the heat treatment temperature of FIG. 3 (b). Ω It can be seen that the resistance is lowered to the extent.

상술한 바와 같이, 본 발명은 반도체 소자의 제조 공정중 하부층이 텅스텐 폴리사이드 구조로 형성되고, 이러한 하부층이 콘택홀을 형성하는 과정에서 플라즈마 식각 분위기에 노출되면서 표면에 형성되는 텅스텐 화합물과 같은 이물질층을 고온 열처리로 금속성 도체로 그 특성을 변화시켜 콘택 저항을 낮추므로써, 제품의 특성을 향상시킬 수 있다.As described above, in the present invention, a lower layer is formed of a tungsten polyside structure during the manufacturing process of a semiconductor device, and the lower layer is a foreign material layer such as a tungsten compound formed on the surface while being exposed to a plasma etching atmosphere in the process of forming a contact hole. The characteristics of the product can be improved by changing the characteristics of the metallic conductor by high temperature heat treatment to lower the contact resistance.

Claims (4)

반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상에 폴리실리콘과 텅스텐 실리사이드가 적층된 텅스텐 폴리사이드 구조의 하부층을 형성하는 단계;Forming a lower layer of a tungsten polyside structure in which polysilicon and tungsten silicide are laminated on a substrate having a structure in which various elements for forming a semiconductor device are formed; 상기 하부층을 포함한 전체 구조상에 층간 절연막을 형성하고, 상기 층간 절연막의 선택된 부분을 식각 하여 하부층이 노출되는 콘택홀을 형성하는 단계;Forming an interlayer insulating film on the entire structure including the lower layer, and etching a selected portion of the interlayer insulating film to form a contact hole through which the lower layer is exposed; 상기 콘택홀 저면을 이루는 상기 하부층의 표면에 형성된 텅스텐 화합물로 된 이물질층을 고온 열처리 공정으로 금속성 도체로 변화시키는 단계; 및Converting a foreign material layer of a tungsten compound formed on a surface of the lower layer forming the bottom of the contact hole into a metallic conductor by a high temperature heat treatment process; And 상기 콘택홀을 세정한 후, 상기 콘택홀을 통해 상기 하부층과 접촉되는 상부층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.And cleaning the contact hole, and then forming an upper layer in contact with the lower layer through the contact hole. 제 1 항에 있어서,The method of claim 1, 상기 열처리 공정은 400 내지 1100℃의 온도에서 수 내지 수십 초간 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법.The heat treatment process is a method of manufacturing a semiconductor device, characterized in that performed for several to several tens of seconds at a temperature of 400 to 1100 ℃. 제 1 항에 있어서,The method of claim 1, 상기 상부층은 폴리실리콘, 폴리실리콘/텅스텐 실리사이드 및 도전성 금속 물질 중 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.And the upper layer is formed of any one of polysilicon, polysilicon / tungsten silicide, and a conductive metal material. 제 1 항에 있어서,The method of claim 1, 상기 이물질층은 WOx 인 것을 특징으로 하는 반도체 소자의 제조 방법.The foreign material layer is a method of manufacturing a semiconductor device, characterized in that the WOx.
KR1019970079264A 1997-12-30 1997-12-30 Method of manufacturing a semiconductor device KR100260521B1 (en)

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