KR100274337B1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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KR100274337B1
KR100274337B1 KR1019970081153A KR19970081153A KR100274337B1 KR 100274337 B1 KR100274337 B1 KR 100274337B1 KR 1019970081153 A KR1019970081153 A KR 1019970081153A KR 19970081153 A KR19970081153 A KR 19970081153A KR 100274337 B1 KR100274337 B1 KR 100274337B1
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conductive pattern
forming
semiconductor device
manufacturing
contact hole
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KR1019970081153A
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Korean (ko)
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KR19990060907A (en
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양종열
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent damage to a semiconductor substrate in an etch process for forming a contact hole, by previously forming a conductive pattern in a portion of the substrate for the contact hole and by forming the contact hole after predetermined processes. CONSTITUTION: After the first interlayer dielectric(13) is formed on the semiconductor substrate(11) having a junction part(12), the junction part is opened. The conductive pattern(14) is formed on the open junction part. After various elements for forming the semiconductor device are formed, the second interlayer dielectric(15) is formed on the resultant structure including the conductive pattern. The second and first interlayer dielectrics are sequentially etched to form the contact hole(16) to which the conductive pattern on the junction part is exposed. After the exposed conductive pattern is removed, a metal interconnection(17) connected to the junction part is formed.

Description

반도체 소자의 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 제조 공정 중 콘택홀 형성을 위한 식각 공정시 반도체 기판의 식각 손상을 방지하여, 소자의 전기적 특성 및 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to prevent etching damage of a semiconductor substrate during an etching process for forming a contact hole during a manufacturing process of a semiconductor device, thereby improving the electrical characteristics and the reliability of the device. A method for manufacturing a device.

일반적으로, 메모리 소자를 포함한 반도체 소자의 제조 공정 중에서 주변 회로의 전원 공급 라인 및 접지 라인으로 사용되는 금속과 반도체 기판의 접합부(n+영역 또는 p+영역)와의 콘택 형성이 진행되는데, 제품 집적도가 점차 증가됨에 따라 접합부의 깊이도 얕아지게 되고, 이로 인하여 콘택홀에서 발생되는 누설 전류가 증가되어 제품 불량의 원인이 된다. 따라서, 접합부에서의 누설 전류의 증가를 방지하는 것이 필요하다.In general, in the process of manufacturing a semiconductor device including a memory device, a contact is formed between a metal used as a power supply line and a ground line of a peripheral circuit and a junction portion (n + region or p + region) of a semiconductor substrate. As it gradually increases, the depth of the junction becomes shallower, which increases the leakage current generated in the contact hole, which causes product defects. Therefore, it is necessary to prevent an increase in the leakage current at the junction.

도 1(a) 및 도 1(b)는 종래 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.

도 1(a)를 참조하면, 접합부(2)가 형성된 반도체 기판(1)상에 제 1 층간 절연막(3)이 형성된다. 제 1 층간 절연막(3)은, DRAM 소자의 경우, 반도체 기판(1)상에 형성된 트랜지스터를 전기적으로 절연하면서 보호하기 위해 형성된다. 제 1 층간 절연막(3)을 형성한 후 비트 라인 및 캐패시터 등의 반도체 소자의 구성 요소를 형성하고, 제 2 층간 절연막(5)을 형성한다. 이후, 주변 회로 지역의 제 2 및 1 층간 절연막(5 및 3)을 습식 식각 및 건식 식각 공정으로 순차적으로 식각 하여 반도체 기판(1)의 접합부(2)가 노출되는 콘택홀(6)이 형성된다.Referring to FIG. 1A, a first interlayer insulating film 3 is formed on a semiconductor substrate 1 on which a junction portion 2 is formed. In the case of a DRAM device, the first interlayer insulating film 3 is formed to electrically protect and protect the transistor formed on the semiconductor substrate 1. After forming the first interlayer insulating film 3, components of semiconductor elements such as bit lines and capacitors are formed, and the second interlayer insulating film 5 is formed. Thereafter, the second and first interlayer insulating films 5 and 3 in the peripheral circuit region are sequentially etched by wet etching and dry etching to form contact holes 6 through which the junction portions 2 of the semiconductor substrate 1 are exposed. .

상기에서, 콘택홀(6) 형성을 위한 식각 공정시 과도 식각 등으로 인하여 접합부(2)의 표면에 식각 손상(8)이 발생된다.In the above, the etching damage 8 is generated on the surface of the junction part 2 due to excessive etching during the etching process for forming the contact hole 6.

도 1(b)를 참조하면, 콘택홀(6)을 포함한 전체 구조상에 금속층 증착 및 패터닝 공정으로 주변 회로 지역의 전원 공급 라인 및 접지 라인으로 사용되는 금속배선(7)이 형성된다.Referring to FIG. 1 (b), a metal layer 7 used as a power supply line and a ground line in a peripheral circuit region is formed by a metal layer deposition and patterning process on an entire structure including a contact hole 6.

상기한 종래 방법으로 금속 배선(7)을 형성할 경우, 콘택홀(6) 형성시에 접합부(2)의 표면이 식각 손상되어 누설 전류를 증가시키게 되고, 따라서, 제품의 전기적 특성 및 신뢰성이 저하되는 문제가 발생할 뿐만 아니라, 소자의 고집적화 실현을 어렵게 한다.When the metal wiring 7 is formed by the above-described conventional method, the surface of the junction portion 2 is etched at the time of forming the contact hole 6, thereby increasing the leakage current, thereby deteriorating the electrical characteristics and reliability of the product. Not only does this cause a problem, but also makes it difficult to realize high integration of the device.

따라서, 본 발명은 반도체 소자의 제조 공정 중 콘택홀 형성을 위한 식각 공정시 반도체 기판의 식각 손상을 방지하여, 소자의 전기적 특성 및 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method of manufacturing a semiconductor device that can prevent the etching damage of the semiconductor substrate during the etching process for forming the contact hole during the manufacturing process of the semiconductor device, thereby improving the electrical characteristics and the reliability of the device. There is a purpose.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 접합부가 형성된 반도체 기판 상에 제 1 층간 절연막을 형성한 후, 상기 접합부를 개방시키고, 개방된 부분에 도전성 패턴을 형성하는 단계; 반도체 소자를 형성하기 위한 여러 요소를 형성한 후, 상기 도전성 패턴을 포함한 전체 구조상에 제 2 층간 절연막을 형성하는 단계; 상기 제 2 및 1 층간 절연막을 순차적으로 식각 하여 상기 접합부상의 도전성 패턴이 노출되는 콘택홀을 형성하는 단계; 및 상기 노출된 도전성 패턴을 제거한 후, 상기 접합부와 연결되는 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming a first interlayer insulating film on a semiconductor substrate on which a junction is formed, opening the junction, and forming a conductive pattern on the open portion; After forming various elements for forming a semiconductor device, forming a second interlayer insulating film on the entire structure including the conductive pattern; Sequentially etching the second and first interlayer insulating layers to form a contact hole exposing the conductive pattern on the junction portion; And after removing the exposed conductive pattern, forming a metal wire connected to the junction part.

도 1(a) 및 도 1(b)는 종래 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.

도 2(a) 내지 도 2(c)는 본 발명의 실시예에 의한 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of devices for explaining the method for manufacturing a semiconductor device according to the embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

1 및 11: 반도체 기판 2 및 12: 접합부1 and 11: semiconductor substrates 2 and 12 junctions

3 및 13: 제 1 층간 절연막 14: 도전성 패턴3 and 13: first interlayer insulating film 14: conductive pattern

5 및 15: 제 2 층간 절연막 6 및 16: 콘택홀5 and 15: second interlayer insulating film 6 and 16: contact hole

7 및 17: 금속 배선 8: 식각 손상7 and 17: metal wiring 8: etch damage

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2(a) 내지 도 2(c)는 본 발명의 실시예에 의한 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 2(a)를 참조하면, 접합부(12)가 형성된 반도체 기판(11)상에 제 1 층간 절연막(13)이 형성된다. 제 1 층간 절연막(13)은, DRAM 소자의 경우, 반도체 기판(11)상에 형성된 트랜지스터를 전기적으로 절연하면서 보호하기 위해 형성된다. 접합부(12) 부분의 제 1 층간 절연막(13)을 개방시킨 후에 접합부(12)와 연결되는 도전성 패턴(14)이 형성된다.Referring to FIG. 2A, the first interlayer insulating layer 13 is formed on the semiconductor substrate 11 on which the junction part 12 is formed. In the case of a DRAM element, the first interlayer insulating film 13 is formed to electrically insulate and protect the transistor formed on the semiconductor substrate 11. After opening the first interlayer insulating film 13 of the junction portion 12, the conductive pattern 14 connected to the junction portion 12 is formed.

상기에서, 도전성 패턴(14)은 별도의 공정으로 형성할 수도 있으며, 반도체 소자의 제조 공정 중에 도전성 물질 증착 공정시에 형성할 수도 있다. 예를 들어, 셀 지역의 비트 라인 형성을 위한 폴리실리콘 증착 및 패터닝 공정시 접합부(12)상에 도전성 패턴(14)을 남길 수 있다.In the above, the conductive pattern 14 may be formed by a separate process, or may be formed during the conductive material deposition process during the manufacturing process of the semiconductor device. For example, the conductive pattern 14 may be left on the junction 12 during the polysilicon deposition and patterning process for forming bit lines in the cell region.

도 2(b)를 참조하면, 제 1 층간 절연막(13)을 형성한 후 비트 라인 및 캐패시터 등의 반도체 소자의 구성 요소를 형성하고, 제 2 층간 절연막(15)을 형성한다. 이후, 주변 회로 지역의 제 2 및 1 층간 절연막(15 및 13)을 습식 식각 및 건식 식각 공정으로 순차적으로 식각 하여 접합부(12)상의 도전성 패턴(14)이 노출되는 콘택홀(16)이 형성된다.Referring to FIG. 2B, after forming the first interlayer insulating layer 13, components of semiconductor elements such as bit lines and capacitors are formed, and the second interlayer insulating layer 15 is formed. Thereafter, the second and first interlayer insulating layers 15 and 13 of the peripheral circuit region are sequentially etched by wet etching and dry etching to form a contact hole 16 through which the conductive pattern 14 on the junction 12 is exposed. .

상기에서, 콘택홀(16) 형성을 위한 식각 공정시 과도 식각을 실시하더라도 도전성 패턴(14)에 의해 접합부(12)의 표면에 식각 손상이 발생되지 않게 된다.In the above, even when excessive etching is performed in the etching process for forming the contact hole 16, the etching pattern is not generated on the surface of the junction part 12 by the conductive pattern 14.

도 2(c)를 참조하면, 콘택홀(16)의 저면을 이루는 도전성 패턴(14)을 식각 공정으로 제거한 후에 전체 구조상에 금속층 증착 및 패터닝 공정으로 주변 회로 지역의 전원 공급 라인 및 접지 라인으로 사용되는 금속배선(17)이 형성된다.Referring to FIG. 2 (c), the conductive pattern 14 constituting the bottom surface of the contact hole 16 is removed by an etching process and then used as a power supply line and a ground line in a peripheral circuit region by a metal layer deposition and patterning process on the entire structure. The metal wiring 17 is formed.

상기에서, 도전성 패턴(14) 식각 공정은 접합부(12)의 식각 손상을 방지하기 위해 습식 식각 공정으로 제거한다. 한편, 도전성 패턴(14)을 제거하지 않고 금속 배선(17)을 형성할 수도 있다.In the above, the etching process of the conductive pattern 14 is removed by a wet etching process to prevent etching damage of the junction 12. In addition, the metal wiring 17 can also be formed without removing the conductive pattern 14.

상술한 바와 같이, 본 발명은 반도체 소자의 제조 공정 중 금속 배선 콘택을 위한 콘택홀 형성시 콘택홀이 형성될 부분의 반도체 기판 상에 미리 도전성 패턴을 형성하고, 공정 순서에 따라 예정된 공정을 거친 후 콘택홀을 형성하므로, 콘택홀 형성을 위한 식각 공정시 반도체 기판의 식각 손상을 방지할 수 있어, 소자의 전기적 특성 및 소자의 신뢰성을 향상시킬 수 있다.As described above, in the process of manufacturing a semiconductor device, a conductive pattern is formed on a semiconductor substrate in a portion where a contact hole is to be formed when forming a contact hole for a metal wiring contact, and after a predetermined process according to the process sequence, Since the contact hole is formed, the etching damage of the semiconductor substrate may be prevented during the etching process for forming the contact hole, thereby improving the electrical characteristics and the reliability of the device.

Claims (5)

접합부가 형성된 반도체 기판 상에 제 1 층간 절연막을 형성한 후, 상기 접합부를 개방시키는 단계;Forming a first interlayer insulating film on a semiconductor substrate on which a junction is formed, and then opening the junction; 상기 개방된 접합부 상에 도전성 패턴을 형성하는 단계;Forming a conductive pattern on the open junction; 반도체 소자를 형성하기 위한 여러 요소를 형성한 후, 상기 도전성 패턴을 포함한 전체 구조상에 제 2 층간 절연막을 형성하는 단계;After forming various elements for forming a semiconductor device, forming a second interlayer insulating film on the entire structure including the conductive pattern; 상기 제 2 및 1 층간 절연막을 순차적으로 식각 하여 상기 접합부상의 도전성 패턴이 노출되는 콘택홀을 형성하는 단계; 및Sequentially etching the second and first interlayer insulating layers to form a contact hole exposing the conductive pattern on the junction portion; And 상기 노출된 도전성 패턴을 제거한 후, 상기 접합부와 연결되는 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.And removing the exposed conductive pattern, and forming a metal wire connected to the junction portion. 제 1 항에 있어서,The method of claim 1, 상기 도전성 패턴은 반도체 소자의 제조 공정중 도전성 물질 증착 및 패터닝 공정시에 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The conductive pattern is a method of manufacturing a semiconductor device, characterized in that formed during the conductive material deposition and patterning process of the semiconductor device manufacturing process. 제 1 항에 있어서,The method of claim 1, 상기 콘택홀은 습식 식각 및 건식 식각 공정에 의해 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The contact hole is a method of manufacturing a semiconductor device, characterized in that formed by wet etching and dry etching processes. 제 1 항에 있어서,The method of claim 1, 상기 도전성 패턴은 습식 식각 공정으로 제거되는 것을 특징으로 하는 반도체 소자의 제조 방법.The conductive pattern is a method of manufacturing a semiconductor device, characterized in that removed by a wet etching process. 제 1 항에 있어서,The method of claim 1, 상기 도전성 패턴 제거 공정 없이 상기 금속 배선 형성 공정을 진행하는 것을 포함하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device comprising the step of performing the metal wiring forming step without the conductive pattern removing step.
KR1019970081153A 1997-12-31 1997-12-31 Method of manufacturing a semiconductor device KR100274337B1 (en)

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Publication number Priority date Publication date Assignee Title
JPH09148268A (en) * 1995-11-22 1997-06-06 Nec Corp Method for manufacturing semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09148268A (en) * 1995-11-22 1997-06-06 Nec Corp Method for manufacturing semiconductor device

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