KR19980053654A - Via hole formation method of semiconductor device - Google Patents

Abstract

The present invention provides a method for forming a via hole in a semiconductor device, which can improve step coverage of a metal wiring layer by forming a via hole using only dry etching using a photoresist film having a different etching selectivity from an interlayer insulating film. Forming an interlayer insulating film on the formed semiconductor substrate; Performing first dry etching of the interlayer insulating layer on the first conductive layer pattern to expose a predetermined portion of the first conductive layer pattern; Forming an organic material layer having an etch selectivity different from that of the interlayer insulating layer on the first conductive layer pattern and the interlayer insulating layer so as to be buried in the exposed portion; Removing the organic layer by a first etching process so that only a predetermined portion of the height of the interlayer insulating film on both sides of the exposed portion remains; Second dry etching the interlayer insulating film; And removing the remaining organic material layer completely by a secondary etching process to form a via hole.

Description

Via hole formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a via hole in a semiconductor device capable of improving step coverage in a multilayer metal wiring.

The multi-layered metal wiring according to the high integration of the semiconductor device enables cross wiring of the devices, and the shortening of the length of the wiring gap along the multi-layered metal wiring reduces the resistance and the capacitor, thereby reducing the device delay time.

An electrical contact is formed to connect the multilayer interconnections. A contact in the multilayer interconnection is referred to as a via contact, and a via hole is formed to form such a via contact.

Next, the method of forming the via hole will be described with reference to FIG. 1.

As shown in FIG. 1, an interlayer insulating film 3 for insulating between metal layers is formed on a semiconductor substrate 1 on which a first metal wiring layer 2 is formed, and an interlayer insulating film on the first metal wiring layer 2 ( 3) is etched to expose a first portion of the first metal wiring layer 2 to form a via hole 4. At this time, the etching of the interlayer insulating film 3 is first etched by a wet etching process, and then second etching is performed by a dry etching process.

However, in the conventional via hole forming method using the etching method, a patch (a) is generated at the site where the wet and dry etching profiles meet due to the wet etching followed by the dry etching. As a result, not only the step coverage of the metal wiring layer is lowered, but also a problem is caused that the metal wiring layer is opened at a site having the worst topologies, thereby degrading the reliability of the device.

Accordingly, the present invention has been made in view of the above-described problems, and forms a via hole using only a dry etching using a photoresist film having an etch selectivity different from an interlayer insulating layer to form stepped via holes in a semiconductor device. The purpose is to provide a method.

1 is a cross-sectional view illustrating a method of forming a via hole in a conventional semiconductor device.

2A through 2E are cross-sectional views sequentially illustrating a method of forming a via hole in a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 semiconductor substrate 12 first metal wiring layer

13 interlayer insulating film 14 photoresist film

15: Via Hole

A method of forming a via hole in a semiconductor device according to the present invention for achieving the above object includes forming an interlayer insulating film on a semiconductor substrate on which a first conductive layer pattern is formed; Performing first dry etching of the interlayer insulating layer on the first conductive layer pattern to expose a predetermined portion of the first conductive layer pattern; Forming an organic material layer having an etch selectivity different from that of the interlayer insulating layer on the first conductive layer pattern and the interlayer insulating layer so as to be buried in the exposed portion; Removing the organic layer by a first etching process so that only a predetermined portion of the height of the interlayer insulating film on both sides of the exposed portion remains; Second dry etching the interlayer insulating film; And removing the remaining organic material layer completely by a secondary etching process to form a via hole.

According to the present invention having the above constitution, the step coverage of the metal wiring layer can be improved by forming the via hole using only dry etching using the organic material layer having different interlayer insulating film and etching selectivity.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2A through 2E are cross-sectional views sequentially illustrating a method of forming a via hole in a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2A, an interlayer insulating film 13 for electrical insulation between metal layers is formed on the semiconductor substrate 11 on which the first metal wiring layer 12 is formed.

As shown in FIG. 2B, the interlayer insulating layer 13 on the first metal wiring layer 12 is first etched to expose a predetermined portion of the first metal wiring layer 12 to form a first via hole (not shown). do. Subsequently, a photoresist film 14 is formed on the first metal wiring layer 12 and the interlayer insulating film 13 to fill the first via hole.

As shown in FIG. 2C, the photoresist film 14 is removed using an O ₃ plasma so that only a predetermined portion remains in the first via hole. In this case, the photoresist film 14 remaining in the first via hole is about 60 to 70% of the height of the first via hole.

As shown in Fig. 2D, the interlayer insulating film 13 is secondly etched to etch edge portions of the interlayer insulating film 13 on both sides of the first via hole on the photoresist film 14. At this time, the dry etching is performed by plasma The etching proceeds to a blanket, using a high electric field applied to the edge portions of the interlayer insulating layer 13 at both sides of the first via hole, and the side is etched to be inclined.

As shown in FIG. 2E, the photoresist layer 14 remaining in the first via hole is removed using an etch selectivity with the interlayer insulating layer 13, thereby forming a via hole for electrical connection with the first metal wiring layer 12. Complete 15).

According to the above embodiment, as the via holes are formed only by using the photoresist film having different etching selectivity from the interlayer insulating film, the step coverage of the metal wiring layer can be improved, thereby improving the reliability of the device.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (6)

Forming an interlayer insulating film on the semiconductor substrate on which the first conductive layer pattern is formed; Performing first dry etching of the interlayer insulating layer on the first conductive layer pattern to expose a predetermined portion of the first conductive layer pattern; Forming an organic material layer having an etch selectivity different from that of the interlayer insulating layer on the first conductive layer pattern and the interlayer insulating layer so as to be buried in the exposed portion; Removing the organic layer by a first etching process so that only a predetermined portion of the height of the interlayer insulating film on both sides of the exposed portion remains; Second dry etching the interlayer insulating film; And, And forming a via hole by completely removing the remaining organic material layer by a secondary etching process. The method of claim 1, wherein the organic material layer is a photoresist film. The method of claim 2, wherein the first etching process of the organic material layer uses an O ₃ plasma. The method of claim 3, wherein after the first etching process, the organic material leaves about 60 to 70% of the height of the interlayer insulating layer on both sides of the exposed portion. The method of claim 2, wherein the second etching process of the organic material layer is performed using an etch selectivity between the organic material layer and the interlayer insulating layer. The method of claim 1, wherein the secondary dry etching of the interlayer insulating layer is performed by a blanket etching process using plasma.