KR20020055256A - Method of forming a dual damascene pattern in a semiconductor device - Google Patents
Method of forming a dual damascene pattern in a semiconductor device Download PDFInfo
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- KR20020055256A KR20020055256A KR1020000084674A KR20000084674A KR20020055256A KR 20020055256 A KR20020055256 A KR 20020055256A KR 1020000084674 A KR1020000084674 A KR 1020000084674A KR 20000084674 A KR20000084674 A KR 20000084674A KR 20020055256 A KR20020055256 A KR 20020055256A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 230000009977 dual effect Effects 0.000 title claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 1
- 230000035622 drinking Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 듀얼 다마신 패턴 형성 방법에 관한 것으로, 특히 비아 또는 콘택홀 및 트랜치로 이루어진 듀얼 다마신 패턴을 형성하는 과정에서 비아 또는 콘택홀 및 트랜치를 동시에 형성하여 공정의 단계를 줄이고 용이하게 형성할 수 있는 반도체 소자의 듀얼 다마신 패턴 형성 방법에 관한 것이다.The present invention relates to a method for forming a dual damascene pattern of a semiconductor device. In particular, in the process of forming a dual damascene pattern consisting of vias or contact holes and trenches, vias or contact holes and trenches are simultaneously formed to reduce the steps of the process. It relates to a dual damascene pattern forming method of a semiconductor device that can be formed.
일반적으로, 층간 절연막은 하부 요소와 상부 요소와의 전기적 절연을 위하여 형성하며, 동시에 하부 요소에 의해 발생하는 단차를 완화시키는 역할을 한다.In general, the interlayer insulating film is formed for electrical insulation between the lower element and the upper element, and at the same time serves to alleviate the step caused by the lower element.
도 1을 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(11)에는 후속 공정에서 형성될 상부 요소와의 절연 및 평탄화를 위하여 전체 상부에 제 1 절연막(12), 식각 방지막(13) 및 제 2 절연막(14)으로 이루어진 층간 절연막(234)을 형성한다. 그리고, 층간 절연막(234)에는 반도체 기판의 접합면(11a)과 상부 요소와의 수직 배선을 위하여 콘택홀이나 비아(16b)가 형성되고, 상부 요소인 금속 배선 라인을 위한 트랜치(16a)가 형성된다.Referring to FIG. 1, a semiconductor substrate 11 having various elements for forming a semiconductor device includes a first insulating layer 12 and an etch stop layer 13 on the entire upper portion for insulating and planarization with an upper element to be formed in a subsequent process. ) And the second insulating film 14 is formed. A contact hole or via 16b is formed in the interlayer insulating layer 234 to vertically connect the junction surface 11a of the semiconductor substrate and the upper element, and a trench 16a for the metal wiring line, which is the upper element, is formed. do.
이렇게, 층간 절연막(234)에 비아(16b) 및 트랜치(16a)로 이루어지거나, 콘택홀(16b) 및 트랜치(16a)로 이루어진 듀얼 다마신 패턴(16)을 형성하기 위해서는, 층간 절연막이 제 1 절연막(12), 식각 방지막(13), 제 2 절연막(14)으로 이루어진 다층막 구조로 형성되어야 한다. 식각 방지막(13)은 제 2 절연막(14)에 트랜치(16a)를 형성하는 과정에서 제 1 절연막(12)이 식각 되거나 식각 손상이 발생하는 것을 방지하기 위하여 형성한다.In this way, in order to form the dual damascene pattern 16 including the vias 16b and the trenches 16a or the contact holes 16b and the trenches 16a in the interlayer insulating film 234, the interlayer insulating film is formed as a first layer. It should be formed in a multilayered film structure consisting of an insulating film 12, an etch stop film 13, and a second insulating film 14. The etch stop layer 13 is formed to prevent the first insulating layer 12 from being etched or etching damage in the process of forming the trench 16a in the second insulating layer 14.
상기의 공정에서, 층간 절연막(234)에 트랜치(16a) 및 비아 또는 콘택홀(16b)을 형성하기 위해서는 마스크 공정 및 식각 공정의 단계가 각각으로 나뉘어져 복잡한다.In the above process, in order to form the trench 16a and the via or contact hole 16b in the interlayer insulating film 234, the steps of the mask process and the etching process are divided and complicated.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여, 콘택홀 및 트랜치를 형성하기 위한 식각 공정에서, 절연막과 동일한 식각 선택비를 갖는 제 1 및 제 2 레지스트를 콘택홀 및 트랜치 마스크로 사용하여 듀얼 다마신 패턴을 형성함으로써 트랜치 및 비아를 동시에 형성하여 공정을 단순화시킬 수 있는 반도체 소자의 듀얼 다마신 패턴 형성 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problem, the present invention provides a dual die by using first and second resists having the same etching selectivity as the insulating film in the etching process for forming the contact holes and the trenches as the contact holes and the trench masks. An object of the present invention is to provide a method for forming a dual damascene pattern of a semiconductor device capable of simplifying a process by simultaneously forming trenches and vias by forming a drinking pattern.
도 1은 종래의 반도체 소자의 듀얼 다마신 패턴 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도1 is a cross-sectional view of a device sequentially shown in order to explain a method of forming a dual damascene pattern of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 듀얼 다마신 패턴 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도2A through 2D are cross-sectional views sequentially illustrating devices for sequentially forming a dual damascene pattern of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11, 21 : 반도체 기판12 : 제 1 절연막11 and 21: semiconductor substrate 12: first insulating film
13 : 식각 방지막14 : 제 2 절연막13 etching prevention film 14 second insulating film
22 : 층간 절연막23 : 제 1 레지스트22 interlayer insulating film 23 first resist
24 : 아크 레이어25 : 제 2 레지스트24: arc layer 25: second resist
16a, 26a : 트랜치16b, 26b : 비아 또는 콘택홀16a, 26a: trench 16b, 26b: via or contact hole
234, 26 : 듀얼 다마신 패턴234, 26: dual damascene pattern
본 발명에 따른 반도체 소자의 듀얼 다마신 패턴 형성 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상에 층간 절연막을 형성하는 단계, 층간 절연막 상에 층간 절연막과 동일한 식각률을 갖는 제 1 레지스트, 아크 레이어 및 제 2 레지스트를 순차적으로 형성하는 단계, 트랜치 마스크를 이용한 식각 공정으로 제 2 레지스트 및 아크 레이어를 패터닝하여 제 1 레지스트를 노출시키는 단계, 비아 마스크를 이용한 식각 공정으로 제 1 레지스트의 노출된 영역을 패터닝하면서, 층간 절연막까지 소정의 두께로 식각하는 단계, 층간 절연막 상의제 2 레지스트, 아크 레이어, 제 1 레지스트를 식각 공정으로 제거하면서, 제 1 레지스트가 제거되어 노출되는 층간 절연막도 계속적으로 식각하는 식각 공정을 이용해 층간 절연막이 식각되는 시점을 영역별로 달리하여 동시에 트랜치 및 비아로 이루어진 듀얼 다마신 패턴을 형성하는 단계로 이루어진다.A method of forming a dual damascene pattern of a semiconductor device according to the present invention includes forming an interlayer insulating film on a semiconductor substrate on which various elements are formed to form a semiconductor device, a first resist having the same etching rate as that of the interlayer insulating film on the interlayer insulating film, Sequentially forming the arc layer and the second resist, patterning the second resist and the arc layer by an etching process using a trench mask to expose the first resist, and exposing the first resist by an etching process using a via mask. Etching the interlayer insulating film to a predetermined thickness while patterning the region, and removing the second resist, the arc layer, and the first resist on the interlayer insulating film by an etching process, while the interlayer insulating film to which the first resist is removed and exposed is continuously etched. The interlayer insulating film is etched using an etching process At different points for each region it comprises a step of forming a dual damascene pattern consisting of a trench and a via at the same time.
식각 공정은 블랭킷 식각으로 실시한다.The etching process is performed by blanket etching.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 듀얼 다마신 패턴 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.2A to 2D are cross-sectional views of devices sequentially illustrated to explain a method of forming a dual damascene pattern of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(21) 상에 층간 절연막(22)을 형성한다. 이후 층간 절연막(22) 상에 제 1 레지스트(23), 아크 레이어(24) 및 제 2 레지스트(25)를 순차적으로 형성하다.Referring to FIG. 2A, an interlayer insulating layer 22 is formed on a semiconductor substrate 21 on which various elements for forming a semiconductor device are formed. Thereafter, the first resist 23, the arc layer 24, and the second resist 25 are sequentially formed on the interlayer insulating layer 22.
이때, 제 1 , 제 2 레지스트(23 및 25) 및 아크 레이어(25)는 층간 절연막(22)과의 식각 선택비가 동일한 물질을 사용하여 형성하며, 이들 모두의 막두께는 층간 절연막(22)의 막두께와 동일하도록 형성한다.In this case, the first and second resists 23 and 25 and the arc layer 25 are formed using a material having the same etching selectivity with the interlayer insulating film 22, and the film thickness of all of them is formed by the interlayer insulating film 22. It is formed to be equal to the film thickness.
도 2b를 참조하면, 트랜치 마스크를 이용한 식각 공정으로 제 2 레지스트(25) 및 아크 레이어(24)의 소정 영역을 식각하여 패터닝 한다. 이로 인해, 소정 영역의 제 1 레지스트(23)가 노출된다.Referring to FIG. 2B, a predetermined region of the second resist 25 and the arc layer 24 is etched and patterned by an etching process using a trench mask. As a result, the first resist 23 in the predetermined region is exposed.
도 2c를 참조하면, 콘택홀 또는 비아 마스크를 이용한 식각 공정으로 제 1레지스트(23)를 식각하여 제거하고, 이로 인해 노출된 층간 절연막(22)도 소정의 깊이로 식각한다.Referring to FIG. 2C, the first resist 23 is etched and removed by an etching process using a contact hole or a via mask, and thus, the exposed interlayer insulating layer 22 is also etched to a predetermined depth.
이때, 식각 공정은 블랭킷 에치(Blanket etch)법으로 실시하며, 제 1 레지스트(23) 및 층간 절연막(22)이 식각되는 영역이 비아 또는 콘택홀이 형성될 영역이다.In this case, the etching process is performed by a blanket etch method, and a region where the first resist 23 and the interlayer insulating layer 22 are etched is a region where vias or contact holes are to be formed.
도 2d를 참조하면, 식각 공정으로 반도체 기판(21) 전체를 식각하면 제 2 및 제 1 레지스트(25 및 23)가 식각되면서 트렌치 형성 영역(A)의 제 1 레지스트(23)가 완전히 제거되여 층간 절연막(22)이 노출되고, 비아 형성 영역(B)의 층간 절연막(22)도 식각된다. 계속해서 식각 공정을 실시하면, 전체 상의 제 2 레지스트(25) 및 아크 레이어(24)가 완전히 제거되면서 제 2 레지스트(25) 하부의 제 1 레지스트(23)가 노출된다. 이때부터, 트랜치 형성 영역(A)에는 잔류하는 레지스트가 없기 때문에 층간 절연막(22)이 식각되기 시작하고, 비아 형성 영역(B)의 층간 절연막(22)은 계속해서 식각된다. 또한, 그 외의 영역에는 제 1 레지스트(23)가 아직도 잔류하기 때문에 제 1 레지스트(23)가 층간 절연막(22)과 동일한 식각 선택비로 식각되고, 층간 절연막(22)은 식각되지 않는다. 이로 인해, 트랜치 형성 영역(A)과 비아 형성 영역(B)의 층간 절연막(22)에는 식각 두께의 차이가 발생하게 된다. 이렇게, 식각 두께의 차이가 발생하는 것을 이용하여 트랜치와 비아를 동시에 형성할 수 있다.Referring to FIG. 2D, when the entire semiconductor substrate 21 is etched by the etching process, the second and first resists 25 and 23 are etched to completely remove the first resist 23 in the trench formation region A, thereby interlayering the semiconductor substrate 21. The insulating film 22 is exposed, and the interlayer insulating film 22 of the via formation region B is also etched. Subsequently, when the etching process is performed, the first resist 23 under the second resist 25 is exposed while the second resist 25 and the arc layer 24 are completely removed. At this time, since there is no resist remaining in the trench formation region A, the interlayer insulating film 22 begins to be etched, and the interlayer insulating film 22 of the via formation region B is continuously etched. In addition, since the first resist 23 still remains in other regions, the first resist 23 is etched at the same etching selectivity as the interlayer insulating film 22, and the interlayer insulating film 22 is not etched. As a result, a difference in etching thickness may occur between the interlayer insulating layer 22 of the trench formation region A and the via formation region B. FIG. As such, the trench and the via may be simultaneously formed by using a difference in etching thickness.
상기의 식각 공정은 층간 절연막(22)의 두께를 고려하여 반도체 기판(21)의 접합면(21a)이 노출될 시점까지만 실시한다. 접합면(21a)이 노출되어 식각 공정이완료되면, 층간 절연막(22)에는 트렌치(26a) 및 비아(26a)가 동시에 형성되어 듀얼 다마신 패턴(26)이 형성된다. 이후에는 완전히 제거되지 않은 레지스트를 세정 공정 또는 식각 공정으로 완전히 제거한다.The etching process is performed only until the junction surface 21a of the semiconductor substrate 21 is exposed in consideration of the thickness of the interlayer insulating film 22. When the bonding surface 21a is exposed and the etching process is completed, the trench 26a and the via 26a are simultaneously formed in the interlayer insulating layer 22 to form the dual damascene pattern 26. Thereafter, the resist which has not been completely removed is completely removed by a cleaning process or an etching process.
상술한 바와 같이, 본 발명은 트랜치와 비아로 이루어진 듀얼 다마신 패턴을 한번의 식각 공정으로 형성함으로써 공정의 단계를 단순화시키고 용이하게 실시할 수 있는 효과가 있다.As described above, the present invention has the effect of simplifying and easily performing the steps of the process by forming a dual damascene pattern consisting of trenches and vias in one etching process.
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