KR970077522A - Method of forming a barrier metal layer of a semiconductor device - Google Patents

Method of forming a barrier metal layer of a semiconductor device Download PDF

Info

Publication number
KR970077522A
KR970077522A KR1019960017619A KR19960017619A KR970077522A KR 970077522 A KR970077522 A KR 970077522A KR 1019960017619 A KR1019960017619 A KR 1019960017619A KR 19960017619 A KR19960017619 A KR 19960017619A KR 970077522 A KR970077522 A KR 970077522A
Authority
KR
South Korea
Prior art keywords
forming
film
metal layer
barrier metal
semiconductor device
Prior art date
Application number
KR1019960017619A
Other languages
Korean (ko)
Other versions
KR100406676B1 (en
Inventor
안희복
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960017619A priority Critical patent/KR100406676B1/en
Publication of KR970077522A publication Critical patent/KR970077522A/en
Application granted granted Critical
Publication of KR100406676B1 publication Critical patent/KR100406676B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 베리어 금속층 형성방법에 관한 것으로, 소자의 동작시 누설 전류의 발생을 방지하기 위하여 티타늄막 및 TiON막을 순차적으로 형성한 후 열처리 공정을 실시하여 상기 TiNO막의 밀도를 증가시키므로써 소자의 동작시 누설 전류의 발생이 방지되며, 고전압 공급시에도 소자의 신뢰성이 유지될 수 있다. 따라서 콘택 홀이 0.5㎛이하의 크기로 형성되는 고집적 소자의 제조 공정에 적용하므로써 소자의 수율이 향상될 수 있도록 한 반도체 소자의 베리어 금속층 형성 방법에 관한 것이다.The present invention relates to a method of forming a barrier metal layer of a semiconductor device, in which a titanium film and a TiON film are successively formed in order to prevent leakage current during operation of the device, and then a heat treatment process is performed to increase the density of the TiNO film, The generation of leakage current is prevented, and the reliability of the device can be maintained even when the high voltage is supplied. Therefore, the present invention relates to a method of forming a barrier metal layer of a semiconductor device, which can improve device yield by applying the contact hole to a process of manufacturing a highly integrated device having a size of 0.5 탆 or less.

Description

반도체 소자의 베리어 금속층 형성 방법Method of forming a barrier metal layer of a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1A도 내지 제1C도는 본 발명에 따른 반도체 소자의 베리어 금속층 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are sectional views of a device for explaining a method of forming a barrier metal layer of a semiconductor device according to the present invention.

Claims (7)

반도체 소자의 베리어 금속층 형성 방법에 있어서, 접합부가 형성된 실리콘 기판상에 절연층을 형성한 후 상기 접합부가 노출되도록 상기 절연층을 패터닝하여 콘택 홀을 형성하는 단계와, 상기 단계로부터 노출된 상기 실리콘 기판상에 성장된 자연 산화막을 제거시키기 위하여 세정 공정을 실시한 후 전체 상부면에 티타늄막을 형성하는 단계와, 상기 단계로부터 상기 티타늄막상에 TiNO막을 형성하는 단계와, 상기 단계로부터 상기 TiON막이 완전한 조성비를 갖도록 열처리하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.A method of forming a barrier metal layer of a semiconductor device, the method comprising: forming an insulating layer on a silicon substrate having a junction formed thereon; patterning the insulating layer to expose the junction to form a contact hole; Forming a TiNO film on the titanium film from the step of forming a titanium film on the entire upper surface after performing a cleaning process to remove the native oxide film grown on the TiN film; And then heat-treating the barrier metal layer. 제1항에 있어서, 상기 세정 공정은 100:1 BOE용액을 이용하여 100 내지 300초동안 실시하는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method of claim 1, wherein the cleaning process is performed for 100 to 300 seconds using a 100: 1 BOE solution. 제1항에 있어서, 상기 티타늄막은 300 내지 1000A의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method according to claim 1, wherein the titanium film is formed to a thickness of 300 to 1000A. 제1항에 있어서, 상기 TiNO막은 200 내지 300℃의 온도에서 500 내지 1500A의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method of claim 1, wherein the TiNO film is formed to a thickness of 500 to 1500 A at a temperature of 200 to 300 캜. 제1항에 있어서, 상기 TiNO막은 산소 및 질소 가스가 공급되는 분위기하에서 티타늄을 증착하므로써 형성되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method of claim 1, wherein the TiNO film is formed by depositing titanium under an atmosphere in which oxygen and nitrogen gas are supplied. 제5항에 있어서, 상기 공급되는 산소 및 질소 가스의 량은 10 내지 50SCCM인 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.6. The method of claim 5, wherein the amount of oxygen and nitrogen gas to be supplied is 10 to 50 SCCM. 제1항에 있어서, 상기 열처리는 400 내지 450℃의 온도 및 산소와 질소 가스가 공급되는 분위기하에서 25 내지 35분동안 실시되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method of claim 1, wherein the heat treatment is performed at a temperature of 400 to 450 DEG C and an atmosphere of oxygen and nitrogen gas for 25 to 35 minutes. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960017619A 1996-05-23 1996-05-23 Method for forming barrier metal of semiconductor device KR100406676B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960017619A KR100406676B1 (en) 1996-05-23 1996-05-23 Method for forming barrier metal of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960017619A KR100406676B1 (en) 1996-05-23 1996-05-23 Method for forming barrier metal of semiconductor device

Publications (2)

Publication Number Publication Date
KR970077522A true KR970077522A (en) 1997-12-12
KR100406676B1 KR100406676B1 (en) 2004-02-25

Family

ID=37422715

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960017619A KR100406676B1 (en) 1996-05-23 1996-05-23 Method for forming barrier metal of semiconductor device

Country Status (1)

Country Link
KR (1) KR100406676B1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3321896B2 (en) * 1992-04-27 2002-09-09 ソニー株式会社 Al-based material forming method, Al-based wiring structure, method of manufacturing semiconductor device, and semiconductor device

Also Published As

Publication number Publication date
KR100406676B1 (en) 2004-02-25

Similar Documents

Publication Publication Date Title
KR970052233A (en) Metal contact formation method
KR970077522A (en) Method of forming a barrier metal layer of a semiconductor device
KR100369354B1 (en) Method for reducing contact resistance by using low energy dry cleaning and rapid thermal annealing
KR19990003495A (en) Barrier metal layer formation method of semiconductor device
KR100282425B1 (en) Method for fabricating of capacitor
KR100237029B1 (en) Process for forming tungsten plug of semiconductor device
KR19990045196A (en) Semiconductor device manufacturing method
KR970003542A (en) Manufacturing method of semiconductor device
KR970008347A (en) Metal layer formation method of semiconductor device
KR960042961A (en) Method of forming diffusion barrier of semiconductor device
JP2776838B2 (en) Method for manufacturing semiconductor device
KR980005615A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR980005609A (en) Method of forming a contact of a semiconductor device
KR970063670A (en) Method of forming a barrier metal layer of a semiconductor device
KR970063484A (en) Method of forming a barrier metal layer of a semiconductor device
KR970060363A (en) Method for forming diffusion barrier film of semiconductor device
KR980005579A (en) Method of forming a barrier metal layer of a semiconductor device
KR980005532A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR970072084A (en) Method for forming a metal layer of a semiconductor
KR980005369A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR940002966A (en) Method of removing interlayer short circuit by polysilicon etching residue
KR970063735A (en) Method for forming charge storage electrode of semiconductor device
KR960026152A (en) Method of Forming Flattened Metal Wiring of Semiconductor Device
KR19980037177A (en) Manufacturing method of semiconductor device
KR970053512A (en) Method for forming conductive wiring in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101025

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee