KR19980037177A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR19980037177A KR19980037177A KR1019960055893A KR19960055893A KR19980037177A KR 19980037177 A KR19980037177 A KR 19980037177A KR 1019960055893 A KR1019960055893 A KR 1019960055893A KR 19960055893 A KR19960055893 A KR 19960055893A KR 19980037177 A KR19980037177 A KR 19980037177A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- manufacturing
- silicon substrate
- titanium
- heat treatment
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000010936 titanium Substances 0.000 claims abstract description 21
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 3
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 2
- 238000000137 annealing Methods 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 콘택홀이 형성된 실리콘 기판상에 티타늄층을 형성한 후 어닐링 공정을 실시하고, 반응하지 않고 남아있는 티타늄층을 제거한 후 다시 어닐링 공정을 실시하여 완전한 티타늄 실리사이드 층을 형성하고, 또한 산소의 농도를 최소화 시키므로써 콘택저항을 감소시킬 수 있는 효과가 있다.The present invention relates to a method for manufacturing a semiconductor device, which forms a titanium layer on a silicon substrate on which a contact hole is formed, and then performs an annealing process. The silicide layer is formed, and the contact resistance can be reduced by minimizing the concentration of oxygen.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 반도체 소자의 제조공정 중 콘택홀을 형성한 후 콘택저항을 감소시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing contact resistance after forming a contact hole during a manufacturing process of a semiconductor device.
일반적으로 반도체 소자가 고집적화 됨에 따라 콘택홀의 크기가 감소되고 이로 인한 콘택저항을 감소시키는 노력이 행해지고 있다. 종래에는 반도체 소자의 제조공정 중 실리콘 기판 상에 콘택홀을 형성한 후 스퍼터링(Sputtering) 방법으로 티타늄(Ti) 및 티타늄 나이트라이드(TiN)를 순차적으로 형성한 후 반응로(Furnace)를 이용한 질소 분위기 하에서 어닐링 공정을 실시하여 티타늄이 실리콘기판에 함유된 실리콘 원자(Si)와 반응하여 티타늄 실리사이드층을 형성시키게 된다. 그러나 상기와 같은 방법에 의해서는 티타늄이 실리콘 원자와 완전히 반응하지 않고 남아있게 되어 콘택저항이 증가하는 주요 원인이 된다. 또한 어닐링 처리시 반응로 내에는 산소가 존재하므로써 자연적으로 성장된 산화막으로 인해 콘택저항이 증가하는 문제가 발생된다.In general, as semiconductor devices are highly integrated, efforts have been made to reduce the size of contact holes and thereby reduce contact resistance. Conventionally, after forming a contact hole on a silicon substrate during the manufacturing process of a semiconductor device and subsequently forming titanium (Ti) and titanium nitride (TiN) by a sputtering method, a nitrogen atmosphere using a furnace (Furnace) The annealing process is performed at the bottom to form a titanium silicide layer by reacting titanium with silicon atoms (Si) contained in the silicon substrate. However, according to the above method, titanium remains without reacting completely with silicon atoms, which is a major cause of increasing contact resistance. In addition, there is a problem that the contact resistance increases due to the naturally grown oxide film due to the presence of oxygen in the reactor during the annealing treatment.
따라서 본 발명은 반도체 소자의 제조공정 중 콘택홀이 형성된 실리콘 기판상에 티타늄층을 형성한 후 어닐링 공정을 실시하고, 반응하지 않고 남아있는 티타늄층을 제거한 후 다시 어닐링 공정을 실시하므로써 콘택저항을 감소시킬 수 있는 반도체 소자의 제조방법을 제공하는 것을 그 목적으로 한다.Therefore, the present invention reduces the contact resistance by performing an annealing process after forming a titanium layer on the silicon substrate on which the contact hole is formed during the manufacturing process of the semiconductor device, removing the remaining titanium layer without reaction, and then performing an annealing process again. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
상술한 목적을 실현하기 위한 본 발명에 따른 반도체 소자의 제조방법은 소정의 공정을 마친 실리콘 기판상에 콘택홀을 형성하는 단계와, 실리콘 기판의 전체 상부면에 티타늄층을 형성하는 단계와, 실리콘 기판상에 제 1 급속 열처리 공정을 실시하여 실리콘 기판의 접합영역 상에 티타늄 실리사이드층을 형성하는 단계와, 티타늄 실리사이드층 상에 남아있는 티타늄층을 습식 식각공정으로 제거하는 단계와, 실리콘 기판상에 제 2 급속 열처리 공정을 실시하는 단계로 이루어진다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a contact hole on a silicon substrate after a predetermined process; forming a titanium layer on the entire upper surface of the silicon substrate; Performing a first rapid heat treatment process on the substrate to form a titanium silicide layer on the junction region of the silicon substrate, removing the titanium layer remaining on the titanium silicide layer by a wet etching process, and And performing a second rapid heat treatment process.
도 1A 내지 1E는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 실리콘기판2 : 접합영역1: silicon substrate 2: junction area
3 : 절연막4 : 티타늄층3: insulating film 4: titanium layer
5 및 5A : 티타늄 실리사이드층10 : 콘택홀5 and 5A: titanium silicide layer 10: contact hole
이하, 본 발명에 따른 반도체 소자의 제조방법을 첨부도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1A 내지 1E는 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도로서, 도 1A는 접합영역(2)이 형성된 실리콘기판(1)상에 절연막(3)을 형성한 후 접합영역(2)이 노출되도록 절연막(3)을 식각하여 콘택홀(10)을 형성한 상태를 도시한다.1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device. FIG. 1A is a view showing a junction region 2 formed after forming an insulating film 3 on a silicon substrate 1 on which a junction region 2 is formed. A state in which the contact hole 10 is formed by etching the insulating film 3 so as to be exposed.
도 1B는 실리콘 기판(1)의 전체 상부면에 티타늄층(4)을 형성한 상태를 도시한다. 티타늄층(4)은 스퍼터링 방법으로 300 내지 500Å의 두께로 형성된다.FIG. 1B shows a state where the titanium layer 4 is formed on the entire upper surface of the silicon substrate 1. The titanium layer 4 is formed to a thickness of 300 to 500 kPa by the sputtering method.
도 1C는 실리콘 기판(1)상에 제 1 급속 열처리 공정(Rapid Thermal Process)을 실시하여 실리콘 기판(1)의 접합영역(2) 상에 티타늄 실리사이드층(5)을 형성한 상태를 도시한다. 상기 제 1 급속 열처리 공정은 질소 분위기 및 600 내지 650℃의 온도 조건에서 실시된다. 이때, 접합영역(2)상에 형성된 티타늄층(4)은 접합영역(2)내에 함유된 실리콘 원자와 반응하여 티타늄 실리사이드층(5)이 형성되게 되는데, 이 티타늄 실리사이드층(5) 상에는 반응하지 않은 티타늄층(4)이 다소 남게 된다.FIG. 1C shows a state in which the titanium silicide layer 5 is formed on the junction region 2 of the silicon substrate 1 by performing a first rapid thermal process on the silicon substrate 1. The first rapid heat treatment step is carried out in a nitrogen atmosphere and temperature conditions of 600 to 650 ℃. At this time, the titanium layer 4 formed on the junction region 2 reacts with the silicon atoms contained in the junction region 2 to form a titanium silicide layer 5, which does not react on the titanium silicide layer 5. Titanium layer 4 is left slightly.
도 1D는 티타늄 실리사이드층(5) 상에 남아있는 티타늄층(4)을 습식 식각 공정으로 제거한 상태를 도시한다. 상기 습식 식각공정은 5 내지 10%의 수산화 칼륨 용액을 사용하여 실시한다. 이때, 티타늄층(4)의 두께는 티타늄 실리사이드층(5) 상에 남아있는 티타늄층(4)의 제거되는 두께 만큼 감소하게 된다.FIG. 1D shows a state in which the titanium layer 4 remaining on the titanium silicide layer 5 is removed by a wet etching process. The wet etching process is performed using 5-10% potassium hydroxide solution. At this time, the thickness of the titanium layer 4 is reduced by the thickness of the titanium layer 4 remaining on the titanium silicide layer 5.
도 1E는 실리콘 기판(1)상에 제 2 급속 열처리 공정을 실시하여 안정한 티타늄 실리사이드층(5A)을 형성한 상태를 도시한다. 상기 제 2 급속 열처리 공정은 질소 분위기 및 800 내지 850℃의 온도 조건에서 30 내지 100초간 실시된다.FIG. 1E shows a state where a stable titanium silicide layer 5A is formed by performing a second rapid heat treatment process on the silicon substrate 1. The second rapid heat treatment process is carried out for 30 to 100 seconds in a nitrogen atmosphere and temperature conditions of 800 to 850 ℃.
상술한 바와 같이 본 발명에 의하면 콘택홀이 형성된 실리콘 기판상에 티타늄층을 형성한 후 어닐링 공정을 실시하고, 반응하지 않고 남아있는 티타늄층을 제거한 후 다시 어닐링 공정을 실시하여 완전한 티타늄 실리사이드층을 형성하고, 또한 산소의 농도를 최소화 시키므로써 콘택저항을 감소시킬 수 있는 효과가 있다.As described above, according to the present invention, after forming the titanium layer on the silicon substrate on which the contact hole is formed, the annealing process is performed. In addition, there is an effect that can reduce the contact resistance by minimizing the concentration of oxygen.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960055893A KR100447784B1 (en) | 1996-11-21 | 1996-11-21 | Method for manufacturing semiconductor device to reduce contact resistance using two-step annealing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960055893A KR100447784B1 (en) | 1996-11-21 | 1996-11-21 | Method for manufacturing semiconductor device to reduce contact resistance using two-step annealing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980037177A true KR19980037177A (en) | 1998-08-05 |
| KR100447784B1 KR100447784B1 (en) | 2004-11-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960055893A KR100447784B1 (en) | 1996-11-21 | 1996-11-21 | Method for manufacturing semiconductor device to reduce contact resistance using two-step annealing |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100447784B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183942A (en) * | 1985-02-08 | 1986-08-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH1092949A (en) * | 1996-09-10 | 1998-04-10 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
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1996
- 1996-11-21 KR KR1019960055893A patent/KR100447784B1/en not_active IP Right Cessation
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| KR100447784B1 (en) | 2004-11-12 |
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