JP4592864B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a polymetal gate and its manufacture.
[0002]
[Prior art]
As a result of advances in microfabrication technology, today's high-speed semiconductor devices or large-capacity semiconductor memory devices have realized gate lengths of 0.25 μm or less. Recently, a semiconductor device having a gate length of 0.1 μm or less has been prototyped.
[0003]
In such a miniaturized semiconductor device, the width of a conductor pattern such as a word line pattern or a bit line pattern is reduced corresponding to the gate length. However, when an electric signal is transmitted through these conductor patterns. In order to maintain the necessary low resistance, it is necessary to increase the height of the conductor pattern. For this reason, in such a miniaturized semiconductor device, there is a problem that the aspect ratio of the conductor pattern increases. If such a high aspect ratio pattern is to be formed by a photolithography process, a reduction in manufacturing yield is inevitable.
[0004]
Conventionally, a fine conductor pattern such as a gate electrode pattern has been formed by patterning a polysilicon or amorphous silicon layer. However, in order to reduce the resistance value of the conductor pattern due to the above circumstances, polysilicon or amorphous A technique for forming a low-resistance silicide layer on a silicon pattern has been proposed. In order to further reduce the resistance value, it is desirable to form a so-called polymetal wiring structure in which a refractory metal layer such as W or Mo is formed on the polysilicon or amorphous silicon pattern. By adopting such a polymetal wiring structure, it is possible to effectively reduce the aspect ratio of the conductor pattern.
[0005]
In such a polymetal wiring structure, if an amorphous silicon pattern or a polysilicon pattern and the refractory metal layer on the amorphous silicon pattern are in direct contact with each other, they react with each other to form a silicide layer. It is necessary to form a diffusion barrier layer made of conductive nitride.
[0006]
FIG. 1 shows a manufacturing process of a semiconductor device having such a polymetal gate electrode.
[0007]
Referring to FIG. 1A, a gate oxide film 12 is formed on a Si substrate 11 by a wet oxidation process using a pyrogenic method, and amorphous silicon or silicon oxide is formed on the gate oxide film 12 in the step of FIG. A gate electrode film 13A made of polysilicon is formed by a CVD method or a plasma CVD method. Further, a diffusion barrier film 13B made of WN is formed on the gate electrode film 13A by sputtering, and a low resistance film 13C made of W is formed on the diffusion barrier film 13B by CVD or sputtering. The gate electrode film 13A, the diffusion barrier film 13B, and the low resistance film 13C form a wiring layer 13 having a polymetal structure.
[0008]
Next, in the step of FIG. 1C, the wiring layer 13 having the polymetal structure is patterned by dry etching using a resist pattern 14, and as a result, a gate electrode 15 is formed.
[0009]
2D, the resist pattern 14 is removed by ashing, and dry etching residues and ashing residues remaining on the substrate 11 are removed using an etchant such as HF.
[0010]
In the step of FIG. 2D, as a result of the wet etching, the gate oxide film 12 is removed on both sides of the gate electrode 15 to expose the surface of the Si substrate, and in the portion directly under the gate electrode 15. Since the undercut 15A is generated as a result of the wet etching proceeding to the side, so-called light oxidation or selective oxidation is performed in the step of FIG. 2E to cover the surface of the exposed Si substrate and the undercut 15A. The SiO ₂ film 16 is formed so as to fill the film.
[0011]
Further, in the step of FIG. 2F, an impurity element is ion-implanted into the Si substrate 11 through the SiO ₂ film 16 while using the gate electrode 15 as a self-aligned mask. Diffusion regions 11A and 11B are formed adjacent to the gate electrode 15.
[0012]
[Problems to be solved by the invention]
By the way, refractory metal materials such as W, Mo, and Ti constituting the low resistance layer 13C are very easily oxidized in a high temperature oxidizing atmosphere. Therefore, in the selective oxidation step of FIG. In order to avoid oxidation, the oxidation process is performed in a hydrogen atmosphere so that the SiO ₂ film 16 is selectively formed only on the exposed surface of the Si substrate 11 and the side wall surface of the gate electrode film 13A. It is necessary to carry out while supplying 20% or less of oxygen or moisture.
[0013]
However, such an atmosphere mainly composed of hydrogen has a risk of reducing the WN diffusion barrier film 13B between the low resistance layer 13C and the gate electrode film 13A. When the diffusion barrier film 13B is reduced, W or Mo in the low resistance layer 13 reacts with Si in the gate electrode film 13A, and silicide is formed. In this case, W atoms may penetrate deeply into the gate electrode film 13A and cause metal peeling due to stress.
[0014]
Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that solve the above problems.
[0015]
[Means for Solving the Problems]
The present invention solves the above problems by forming a first conductive layer made of silicon on a substrate, depositing a diffusion barrier layer made of refractory metal nitride on the first conductive layer, Depositing a second conductive layer made of a refractory metal on the diffusion barrier layer to form a wiring layer including the first conductive layer, the diffusion barrier layer, and the second conductive layer; A method of forming a wiring pattern by patterning a layer; and a step of selectively oxidizing the wiring pattern to selectively form an oxide film on a sidewall of the first conductive layer. The selective oxidation step includes a step of heating the wiring pattern in a nitrogen atmosphere at a temperature rising rate of 50 to 100 ° C./second, and a temperature rising of the wiring pattern, and then 850 ° C. to 1050 ° C. in the nitrogen atmosphere. While maintaining the temperature of The chromatography down to a heat treatment for 3-5 seconds, a step of converting the refractory metal nitrides of the diffusion barrier layer on the refractory metal珪窒compound, refractory metal nitrides of the diffusion barrier layer on the refractory珪窒product After the conversion, the wiring pattern is solved by a method of heat treatment in an atmosphere in which oxygen or moisture is added to hydrogen.
[0016]
[ Action]
According to the present invention, the conductive pattern having a structure in which the first conductive layer made of polysilicon or amorphous silicon and the second conductive layer made of refractory metal are separated by the diffusion barrier layer made of refractory metal nitride. In the manufacture of the semiconductor device having the above, the diffusion barrier layer is heat-treated in an inert atmosphere prior to the selective oxidation heat treatment in a hydrogen atmosphere where the diffusion barrier layer may be reduced. It becomes possible to form a silicon nitride such as WSiN having high thermal stability in the layer. As a result of forming such a silicon nitride, the diffusion barrier layer is also reduced when a selective oxidation heat treatment is further performed in an oxygen-containing hydrogen atmosphere to selectively form an oxide film around the first conductive layer. Therefore, the problem that the first conductive layer and the second conductive layer react with each other is avoided. By this selective oxidation method, an oxide film is formed on the side wall of the first conductive layer. At the same time, for example, in the case of a MOS transistor using the conductive pattern as a gate electrode, the substrate is adjacent to the gate electrode. An oxide film is also formed on the surface of the diffusion region thus formed.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
3A to 4F show a manufacturing process of a semiconductor device according to an embodiment of the present invention.
[0018]
Referring to FIG. 3A, an SiO ₂ film or SiON film having a thickness of 2 to 4 nm is formed as a gate oxide film 22 on the Si substrate 21, and the gate oxide film is formed in the step of FIG. A gate electrode film 23A made of amorphous silicon or polysilicon is formed on the layer 22 to a thickness of about 80 nm by CVD or plasma CVD. A p-type impurity element such as B ⁺ or an n-type impurity element made of P ⁺ or As ⁺ is introduced into the gate electrode film 23A by ion implantation, and after further removing the natural oxide film, the gate electrode A diffusion barrier film 23B made of WN and a low resistance film 23C made of W are formed on the film 23A by CVD or sputtering with a substrate temperature of about 150 ° C. and a thickness of 5 nm and 50 nm, respectively. . The gate electrode film 23A, the diffusion barrier film 23B, and the low resistance film 23C form a wiring layer 23 having a polymetal structure.
[0019]
Next, in the step of FIG. 3C, after the SiN film 24A is further formed on the polymetal structure wiring layer 23 by a thermal CVD method at 650 to 750 ° C. to a thickness of 100 to 200 nm, A SiON film 24B is formed on the SiN film 24A as an antireflection film with a thickness of 30 to 50 nm by plasma CVD. 2C, the wiring layer 23 is patterned by dry etching using a resist pattern (not shown) together with the antireflection film 24B and the SiN film 24A. As a result, the gate electrode 25 is formed. The
[0020]
Further, in the step of FIG. 4D, the antireflection film 24B is removed by wet etching with an etchant such as HF. By this wet etching step, dry etching residue and ashing residue remaining on the substrate 21 are removed. Removed at the same time.
[0021]
In the step of FIG. 4D, as a result of the wet etching, the gate oxide film 22 is removed on both sides of the gate electrode 25 to expose the surface of the Si substrate, and in the portion immediately below the gate electrode 25. As a result, undercut 25A occurs as a result of the wet etching progressing to the side, so-called light oxidation is performed in the step of FIG. 4E so as to cover the exposed surface of the Si substrate 21 and the undercut 125A. The SiO ₂ film 26 is formed so as to fill the film.
[0022]
FIG. 5 shows the light oxidation heat treatment used in the step of FIG.
[0023]
Referring to FIG. 5, in this embodiment, in stage I, N ₂ is introduced into the heat treatment apparatus having the structure of FIG. 4D at a flow rate of 2.5 to 20 SLM for about 20 to 60 seconds. The atmosphere in the processing apparatus is set to an inert N ₂ atmosphere.
[0024]
Next, in Step II, the structure is rapidly heated to a predetermined temperature in the N ₂ atmosphere at a temperature rising rate of, for example, about 50 to 100 ° C./second. At that time, N ₂ is introduced into the heat treatment apparatus at a flow rate of 2.5 to 10 SLM in the same manner as in Step I to maintain the inert N ₂ atmosphere.
[0025]
Further, in Step III, the N ₂ atmosphere is maintained at the predetermined temperature, for example, 850 to 1050 ° C. for a while, for example, for 3 to 5 seconds, and in Step IV, the atmosphere is gradually switched from H ₂ atmosphere to reducing atmosphere.
[0026]
Furthermore, in step V, O ₂ or H ₂ O is introduced into the atmosphere, and the exposed surface including the exposed surface of the Si substrate 21 and the side wall surface of the gate electrode layer 23A is selectively oxidized for 10 to 30 seconds. The SiO ₂ film 26 is formed to a thickness of 2 to 4 nm. In the illustrated example, O ₂ is added at a ratio of 5 to 20% with respect to the H ₂ atmosphere in the stage V where selective oxidation is performed. Further, when H ₂ O is used instead of O _{2 in} the illustrated example, the addition amount is set to 15%.
[0027]
Further, in Step VI, N ₂ is flowed again at a flow rate of about _2.5 to 20 SLM, the atmosphere is switched to the N ₂ atmosphere, and the substrate temperature is lowered to about room temperature within 20 to 60 seconds.
[0028]
In the heat treatment process of FIG. 5, since the heat treatment is performed in an inert N ₂ atmosphere until the first stages I to III, the WN diffusion barrier film 23B is not reduced to W. In the heat treatment step of FIG. 5, WN constituting the diffusion barrier film 23B reacts in the vicinity of the interface between the polysilicon or amorphous silicon gate electrode film 23A and the films 23A and 23B, particularly in the stage III, and is thermally stable. WSiN is formed as the layer 23b shown in FIG. Since the WSiN layer 23c is stable, it is not reduced even if the atmosphere is switched to the reducing H ₂ atmosphere in the stage IV or V. Therefore, the diffusion barrier film 23B performs its function, and the gate electrode film The reaction between 23A and the W film 23C is effectively suppressed.
[0029]
The WSiN layer 23c can be formed to be localized in the vicinity of the interface by controlling the time of the step III, or can be formed to substantially replace the diffusion barrier film 23B. is there.
[0030]
Further, in the step of FIG. 4F, an impurity element is ion-implanted into the Si substrate 21 through the SiO ₂ film 26 while using the gate electrode 25 as a self-alignment mask. The diffusion regions 21A and 21B are formed adjacent to the gate electrode 25.
[0031]
Further, as shown in the modification of FIG. 6, the entire WN diffusion barrier layer 23B may be replaced with a WSiN layer 23b. However, in FIG. 6, the part demonstrated previously is attached | subjected the same referential mark, and description is abbreviate | omitted.
[0032]
In the present invention, the refractory metal element forming the silicon nitride layer 23b is not limited to W, and may be Mo, Ti, or the like.
[0033]
Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope described in the claims.
[0034]
【The invention's effect】
According to the present invention, the conductive pattern having a structure in which the first conductive layer made of polysilicon or amorphous silicon and the second conductive layer made of refractory metal are separated by the diffusion barrier layer made of refractory metal nitride. In the manufacture of the semiconductor device having the above, the diffusion barrier layer is heat-treated in an inert atmosphere prior to the selective oxidation heat treatment in a hydrogen atmosphere where the diffusion barrier layer may be reduced. It becomes possible to form a silicon nitride such as WSiN having high thermal stability in the layer. As a result of forming such a silicon nitride, the diffusion barrier layer is also reduced when a selective oxidation heat treatment is further performed in an oxygen-containing hydrogen atmosphere to selectively form an oxide film around the first conductive layer. Therefore, the problem that the first conductive layer and the second conductive layer react with each other is avoided. By this selective oxidation method, an oxide film is formed on the side wall of the first conductive layer. At the same time, for example, in the case of a MOS transistor using the conductive pattern as a gate electrode, the substrate is adjacent to the gate electrode. An oxide film is also formed on the surface of the diffusion region thus formed.
[Brief description of the drawings]
FIGS. 1A to 1C are views (No. 1) showing a manufacturing process of a conventional semiconductor device. FIGS.
FIGS. 2D to 2F are views (No. 2) showing a manufacturing process of a conventional semiconductor device. FIGS.
FIGS. 3A to 3C are views (No. 1) showing a manufacturing process of a semiconductor device according to an embodiment of the invention; FIGS.
FIGS. 4D to 4F are views (No. 2) illustrating the manufacturing steps of the semiconductor device according to the embodiment of the invention. FIGS.
FIG. 5 is a diagram illustrating a selective oxidation process used in the present invention.
FIG. 6 is a diagram showing a modification of one embodiment of the present invention.
[Explanation of symbols]
11, 21 Si substrate 11A, 11B, 21A, 21B Diffusion region 12, 22 Gate insulating film 13, 23 Conductive pattern 13A, 23A Polysilicon film (gate electrode film)
13B, 23B Diffusion barrier films 13C, 23C Refractory metal film 14 Resist pattern 15 Gate electrode 15A Undercut 16 SiO ₂ film 24A SiN film 24B Antireflection film 23b Nitride diffusion barrier layer

Claims (2)

Forming a first conductive layer made of silicon on a substrate;
Depositing a diffusion barrier layer of refractory metal nitride on the first conductive layer;
Depositing a second conductive layer made of a refractory metal on the diffusion barrier layer, and forming a wiring layer including the first conductive layer, the diffusion barrier layer, and the second conductive layer;
Patterning the wiring layer to form a wiring pattern;
Selectively oxidizing the wiring pattern to selectively form an oxide film on a sidewall of the first conductive layer;
In a method for manufacturing a semiconductor device including:
The selective oxidation step includes
Heating the wiring pattern in a nitrogen atmosphere at a temperature rising rate of 50 to 100 ° C./second ;
After the wiring pattern is heated, the wiring pattern is heat-treated for 3 to 5 seconds while maintaining a temperature of 850 ° C. to 1050 ° C. in the nitrogen atmosphere , and the refractory metal nitride of the diffusion barrier layer is converted to a refractory metal. Converting to silicon nitride,
Converting the refractory metal nitride of the diffusion barrier layer into a refractory silicon nitride, and then heat-treating the wiring pattern in an atmosphere in which oxygen or moisture is added to hydrogen;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of supplying HF onto the substrate after patterning the wiring layer and before selectively oxidizing the wiring pattern.

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