KR980005615A - METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR - Google Patents

METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR Download PDF

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Publication number
KR980005615A
KR980005615A KR1019960025767A KR19960025767A KR980005615A KR 980005615 A KR980005615 A KR 980005615A KR 1019960025767 A KR1019960025767 A KR 1019960025767A KR 19960025767 A KR19960025767 A KR 19960025767A KR 980005615 A KR980005615 A KR 980005615A
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KR
South Korea
Prior art keywords
metal wiring
cvd
tin
depositing
wiring layer
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Application number
KR1019960025767A
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Korean (ko)
Inventor
서환석
허재영
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960025767A priority Critical patent/KR980005615A/en
Publication of KR980005615A publication Critical patent/KR980005615A/en

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Abstract

본 발명은 반도체 소자의 금속 배선 형성 배선 형성방법에 관한 것으로, 금속 배선의 베리어층으로 사용하는 TiN을 화확 기상증착방법으로 증착한 다음, 질소(N2), 질소와 수소의 혼합 가스(N2+H2), 또는 암모니아(NH3)중의 하나인 분위기에서 급속 열처리를 실시하여 CVD-TiN 내의 탄소의 양을 줄이고 조밀한 TiN박막을 형성하고, 그 상부에 금속 배선층을 증착하여 금속 배선을 형성하는 것이다.The present invention relates to a method of forming a wiring forming metal wiring of a semiconductor device, a deposition of TiN using the barrier layer of the metal wiring in Rubber Products vapor deposition method, and then, nitrogen (N 2), nitrogen and a mixture of hydrogen gas (N 2 + H 2 ), or ammonia (NH 3 ) to reduce the amount of carbon in the CVD-TiN to form a dense TiN film, and a metal wiring layer is deposited thereon to form a metal wiring .

Description

반도체 소자의 금속배선 형성방법METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제5도는 본 발명의 실시예에 의해 실리콘 기판에 콘택되는 금속 배선을 형성하는 단계를 도시한 단면도이다.FIG. 5 is a cross-sectional view showing the step of forming a metal wiring to be contacted with a silicon substrate according to an embodiment of the present invention.

Claims (7)

반도체소자의 금속 배선 형성 방법에 있어서, 실리콘 기판 상부에 절연막을 증착하고, 상기 절연막의 일정부분을 식각하여 콘택홀을 형성하는 단계화 전체적으로 Ti를 증착하는 단계와, 상기 Ti 상부에 CVD-TiN을 증착하는 단계와, 상기CVD-TiN 의 불안정한 요인을 해소하기 위하여 급속열처리(RTA)를 실시하는 단계와, 상기 CVD-TiN 상부에 급속 배선층을 증착하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법.A method of forming a metal wiring of a semiconductor device, comprising the steps of: depositing an insulating film on a silicon substrate; etching a predetermined portion of the insulating film to form a contact hole; depositing Ti on the entire surface; Depositing a rapid-wiring layer on top of the CVD-TiN; and depositing a rapid-wiring layer on top of the CVD-TiN. 제1항에 있어서, 상기 Ti는 PVD또는 CVD방법으로 100-1000Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the Ti is deposited by PVD or CVD to a thickness of 100-1000 Å. 제1항에 있어서, 상기 CVD-TiN은 100-500Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.2. The method of claim 1, wherein the CVD-TiN is deposited to a thickness of 100-500 Angstroms. 제1항에 있어서, 상기 CVD-TiN를 급속 열처리하는 공정은 질소, 질소와 수소의 혼합가스, 또는 암모니아 분위기에서 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method according to claim 1, wherein the CVD-TiN rapid thermal annealing process is performed in a nitrogen gas, a mixed gas of nitrogen and hydrogen, or an ammonia atmosphere. 제1항 또는 제4항에 있어서, 상기 급속 열처리 공정은 400-800℃의 온도에서 10초~3분 동안 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1 or 4, wherein the rapid thermal annealing process is performed at a temperature of 400-800 DEG C for 10 seconds to 3 minutes. 제1항에 있어서, 상기 금속 배선층은 A1또는 W인 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method according to claim 1, wherein the metal wiring layer is Al or W. 제6항에 있어서, 상기 금속 배선층을 물리기상증착(PVD) 또는 화학 기상증착(CVD)법으로 증착하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method according to claim 6, wherein the metal wiring layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025767A 1996-06-29 1996-06-29 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR KR980005615A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025767A KR980005615A (en) 1996-06-29 1996-06-29 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

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Application Number Priority Date Filing Date Title
KR1019960025767A KR980005615A (en) 1996-06-29 1996-06-29 METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472259B1 (en) * 2001-03-28 2005-03-08 샤프 가부시키가이샤 METHOD OF BARRIER METAL SURFACE TREATMENT PRIOR TO Cu DEPOSITION TO IMPROVE ADHESION AND TRENCH FILLING CHARACTERISTICS
KR100480576B1 (en) * 1997-12-15 2005-05-16 삼성전자주식회사 Forming method of metal wiring in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480576B1 (en) * 1997-12-15 2005-05-16 삼성전자주식회사 Forming method of metal wiring in semiconductor device
KR100472259B1 (en) * 2001-03-28 2005-03-08 샤프 가부시키가이샤 METHOD OF BARRIER METAL SURFACE TREATMENT PRIOR TO Cu DEPOSITION TO IMPROVE ADHESION AND TRENCH FILLING CHARACTERISTICS

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