KR970063670A - Method of forming a barrier metal layer of a semiconductor device - Google Patents

Method of forming a barrier metal layer of a semiconductor device Download PDF

Info

Publication number
KR970063670A
KR970063670A KR1019960004778A KR19960004778A KR970063670A KR 970063670 A KR970063670 A KR 970063670A KR 1019960004778 A KR1019960004778 A KR 1019960004778A KR 19960004778 A KR19960004778 A KR 19960004778A KR 970063670 A KR970063670 A KR 970063670A
Authority
KR
South Korea
Prior art keywords
titanium
metal layer
forming
barrier metal
heat treatment
Prior art date
Application number
KR1019960004778A
Other languages
Korean (ko)
Other versions
KR100187675B1 (en
Inventor
문영화
홍흥기
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960004778A priority Critical patent/KR100187675B1/en
Publication of KR970063670A publication Critical patent/KR970063670A/en
Application granted granted Critical
Publication of KR100187675B1 publication Critical patent/KR100187675B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 베리어 금속층 형성 방법에 관한 것으로, 콘택 홀의 크기 감소에 따른 금속층과 접합부간의 접촉 저항의 증가를 방지하기 위하여 접합부와 금속층간의 계면에 몰리브덴티타늄실리콘층을 형성하므로써 반도체 소자의 고집적화에 따라 증가되는 콘택 저항을 감소시켜 소자의 특성이 향상되도록 한 반도체 소자의 베리어 금속층 형성 방법에 관한 것이다.The present invention relates to a method for forming a barrier metal layer of a semiconductor device and a molybdenum titanium silicon layer is formed at the interface between the junction and the metal layer in order to prevent an increase in contact resistance between the metal layer and the junction, To a method of forming a barrier metal layer of a semiconductor device in which characteristics of the device are improved.

Description

반도체 소자의 베리어 금속층 형성 방법Method of forming a barrier metal layer of a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2d도는 본 발명에 따른 반도체 소자의 베리어 금속층 형성 방법을 설명하기 위한 소자의 단면도.FIGS. 2a to 2d are sectional views of a device for explaining a method of forming a barrier metal layer of a semiconductor device according to the present invention.

Claims (8)

반도체 소자의 베리어 금속층 형성 방법에 있어서, 접합부가 형성된 실리콘 기판상에 절연층을 형성하고, 상기 접합부가 노출되도록 상기 절연층을 패터닝하여 콘택 홀을 형성하는 제1단계와, 상기 제1단계로부터 전체 상부면에 몰리브덴티타늄을 증착하는 제2단계와, 상기 제2단계로부터 상기 접합부의 실리콘 기판 및 상기 몰리브덴티타늄의 계면에 몰리브덴티타늄실리콘층이 형성되도록 1차 열처리 공정을 실시하는 제3단계와, 상기 제3단계로부터 상기 제1열처리 공정시 미반응된 티타늄을 제거하는 제4단계와, 상기 제4단계로부터 전체 상부면에 티타늄나이트라이드를 증착한 후 2차 열처리 공정을 실시하는 제5단계로 이루어지는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.A method for forming a barrier metal layer of a semiconductor device, the method comprising: a first step of forming an insulating layer on a silicon substrate having a junction formed thereon and patterning the insulating layer to expose the junction to form a contact hole; A second step of depositing molybdenum titanium on the upper surface and a third step of performing a first heat treatment step so that a molybdenum titanium silicon layer is formed on the interface between the silicon substrate and the molybdenum titanium of the junction from the second step, A fourth step of removing unreacted titanium from the third step in the first heat treatment step, and a fifth step of performing a second heat treatment step after depositing titanium nitride on the entire upper surface from the fourth step Wherein the barrier metal layer is formed on the semiconductor substrate. 제1항에 있어서, 상기 몰리브덴티타늄은 300 내지 500A의 두께로 중착된 것을 특징으로 하는 반도체소자의 베리어 금속층 형성 방법.The method according to claim 1, wherein the molybdenum titanium is deposited at a thickness of 300 to 500 A. 제1항에 있어서, 상기 제1차 열처리 공정은 600 내지 750℃의 온도에서 급속 열처리 방법으로 실시되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method of claim 1, wherein the first annealing process is performed by a rapid thermal annealing process at a temperature of 600 to 750 ° C. 제1항에 있어서, 상기 미반응된 티타늄은 NH4F+H2O2+H2O을 이용한 습식 식각 공정에 의해 제거되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method of claim 1, wherein the unreacted titanium is removed by a wet etching process using NH 4 F + H 2 O 2 + H 2 O. 제1항에 있어서, 상기 티타늄나이트라이드는 1000 내지 1200A의 두께로 중착된 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method of claim 1, wherein the titanium nitride is deposited at a thickness of 1000 to 1200 A. 제1항에 있어서, 상기 2차 열처리 공정은 질소 가스 분위기하에서 실시되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method for forming a barrier metal layer of a semiconductor device according to claim 1, wherein the second heat treatment step is performed in a nitrogen gas atmosphere. 제1항에 있어서, 상기 제4단계로부터 전체 상부면에 티타늄 및 티타늄나이트라이드를 순차적으로 증착한 후 2차 열처리 공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method as claimed in claim 1, wherein the fourth step comprises sequentially depositing titanium and titanium nitride on the entire upper surface, and then performing a second heat treatment process. 제7항에 있어서, 상기 티타늄은 100 내지 400A 두께로 증착되며, 상기 티타늄나이트라이드는 800 내지 1200A 두께로 증착되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성 방법.The method as claimed in claim 7, wherein the titanium is deposited to a thickness of 100 to 400 A, and the titanium nitride is deposited to a thickness of 800 to 1200 A. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960004778A 1996-02-27 1996-02-27 Method of forming barrier metal layer in a semiconductor device KR100187675B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960004778A KR100187675B1 (en) 1996-02-27 1996-02-27 Method of forming barrier metal layer in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960004778A KR100187675B1 (en) 1996-02-27 1996-02-27 Method of forming barrier metal layer in a semiconductor device

Publications (2)

Publication Number Publication Date
KR970063670A true KR970063670A (en) 1997-09-12
KR100187675B1 KR100187675B1 (en) 1999-06-01

Family

ID=19451857

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960004778A KR100187675B1 (en) 1996-02-27 1996-02-27 Method of forming barrier metal layer in a semiconductor device

Country Status (1)

Country Link
KR (1) KR100187675B1 (en)

Also Published As

Publication number Publication date
KR100187675B1 (en) 1999-06-01

Similar Documents

Publication Publication Date Title
KR970052233A (en) Metal contact formation method
KR960002892A (en) Silicon Carbide Semiconductor Device and Manufacturing Method Thereof
KR970063577A (en) Metal wiring structure and formation method
KR950034672A (en) Manufacturing method of semiconductor integrated circuit device
TW429523B (en) Method of manufacturing semiconductor device
KR970063670A (en) Method of forming a barrier metal layer of a semiconductor device
KR970008347A (en) Metal layer formation method of semiconductor device
KR960026205A (en) Metal Wiring Contact Manufacturing Method
KR970052303A (en) Metal wiring formation method of semiconductor device
KR970013219A (en) Barrier metal layer formation method of semiconductor device
KR930011111A (en) Contact manufacturing method using titanium silicide
KR980005519A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR970072084A (en) Method for forming a metal layer of a semiconductor
KR910010629A (en) Metal wiring film formation method
KR970052921A (en) Metal layer formation method of semiconductor device
KR980005528A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR960039282A (en) Wiring Manufacturing Method of Semiconductor Device
KR970063484A (en) Method of forming a barrier metal layer of a semiconductor device
KR970072090A (en) Method for forming wiring layer of semiconductor device
KR980005615A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR970053523A (en) Metal wiring formation method of semiconductor device
KR970077522A (en) Method of forming a barrier metal layer of a semiconductor device
KR970018215A (en) Manufacturing Method of Semiconductor Device
KR970062843A (en) Method of forming a barrier metal layer of a semiconductor device
KR19980055923A (en) Barrier metal layer formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091222

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee