KR960039282A - Wiring Manufacturing Method of Semiconductor Device - Google Patents

Wiring Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR960039282A
KR960039282A KR1019950007654A KR19950007654A KR960039282A KR 960039282 A KR960039282 A KR 960039282A KR 1019950007654 A KR1019950007654 A KR 1019950007654A KR 19950007654 A KR19950007654 A KR 19950007654A KR 960039282 A KR960039282 A KR 960039282A
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KR
South Korea
Prior art keywords
forming
wiring pattern
copper
wiring
film
Prior art date
Application number
KR1019950007654A
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Korean (ko)
Other versions
KR0167237B1 (en
Inventor
박종욱
천성순
김동원
이원준
라사균
이영종
Original Assignee
문정환
엘지반도체 주식회사
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Priority to KR1019950007654A priority Critical patent/KR0167237B1/en
Publication of KR960039282A publication Critical patent/KR960039282A/en
Application granted granted Critical
Publication of KR0167237B1 publication Critical patent/KR0167237B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로, 반도체 기판 상에 절연막을 증착한 후 선택적으로 식각하여 콘택홀을 형성하는 공정과; 상기 기판과 콘택홀 상에 장벽층을 형성하는 공정과; 상기 장벽층 상에 구리막을 형성한 후 장벽층과 구리막을 선택식각하여 배선 패턴을 형성하는 공정 및; 상기 배선 패턴 표면에 선택적으로 구리 실리사이드를 형성하는 공정을 포함하여 반도체 소자의 배선 제로를 완료하므로써, 1) 구리 배선의 장점인 낮은 저항(low resistivtiy)(알루미늄의 저항치;2.65μΩcm, 구리의 저항치;1.7μΩcm) 및 우수한 일렉트로 마이그레이션(dlectromigration) 특성을 가질 수 있으며, 2) 낮은 내산화성 및 유전막과의 낮은 접촉특성 등을 향상시킬 수 있고, 3) 단결성 실리콘내에서의 빠른 확산율 특성을 저하시켜 소자의 특성을 향상시킬 수 있는 고신뢰성의 배선을 구현할 수 있게 된다.The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, comprising: forming a contact hole by selectively etching an insulating film on a semiconductor substrate; Forming a barrier layer on the substrate and the contact hole; Forming a wiring pattern by forming a copper film on the barrier layer and then selectively etching the barrier layer and the copper film; By completing the wiring zero of the semiconductor device including the step of selectively forming a copper silicide on the wiring pattern surface, 1) low resistivtiy (resistance of aluminum; 2.65μ Ωcm, resistance of copper) which is the advantage of copper wiring; 1.7μΩcm) and excellent electromigration characteristics, 2) can improve low oxidation resistance and low contact with dielectric film, and 3) deteriorate fast diffusion characteristics in unitary silicon. It is possible to implement a highly reliable wiring to improve the characteristics of.

Description

반도체 소자의 배선 제조방법Wiring Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2(가)도 내지 제2(라)도는 본 발명에 따른 반도체 소자의 다결정 실리콘을 사용한 구리 실리사이드 배선층 제조방법을 도시한 공정 수순도.2 (a) to 2 (d) are process steps showing a method for manufacturing a copper silicide wiring layer using polycrystalline silicon of a semiconductor device according to the present invention.

Claims (6)

반도체 기판 상에 절연막을 증착한 후 선택적으로 식각하여 콘택홀을 형성하는 공정과; 상기 기판과 콘택홀 상에 장벽층을 형성하는 공정과; 상기 장벽층 상에 구리막을 형성한 후 장벽층과 구리막을 선택식각하여 배선 패턴을 형성하는 공정 및; 상기 배선 패턴 표면에 선택적으로 구리 실리사이드를 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 반도체 소자의 배선 제조방법.Depositing an insulating film on a semiconductor substrate and then selectively etching to form contact holes; Forming a barrier layer on the substrate and the contact hole; Forming a wiring pattern by forming a copper film on the barrier layer and then selectively etching the barrier layer and the copper film; And forming a copper silicide selectively on the surface of the wiring pattern. 제1항에 있어서, 상기 구리 실리사이드는 배선 패턴이 형성된 절연막 상에 다결정 실리콘 또는 비정질실리콘을 증착하고 열처리하여 배선패턴 표면에 선택적으로 구리 실리사이드를 형성하고, 배선 패턴을 제외한 부분에 증착된 다결정 실리콘을 제거하는 공정을 더 포함하여 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the copper silicide is formed by depositing and thermally treating polycrystalline silicon or amorphous silicon on an insulating film on which a wiring pattern is formed, and selectively forming copper silicide on a surface of the wiring pattern, and depositing polycrystalline silicon on a portion other than the wiring pattern. The method for manufacturing a wiring of a semiconductor device, characterized in that it further comprises a step of removing. 제2항에 있어서, 상기 다결정 실리콘막 및 비정질 실리콘막은 SiH4, Si2H6, Si3H8, SiH2Cl2중 선택된 어느 한 소오스 가스를 이용하여 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The wire fabrication of a semiconductor device according to claim 2, wherein the polycrystalline silicon film and the amorphous silicon film are formed using a source gas selected from SiH 4 , Si 2 H 6 , Si 3 H 8 , and SiH 2 Cl 2 . Way. 제2항에 있어서, 상기 다결정 실리콘막 또는 비정질 실리콘막은 배선 패턴 및 절연막 상에 형성한 후 열처리 공정을 실시하여 배선 패턴 표면에 구리 실리사이드를 형성하는 공정을 더 포함하여 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The semiconductor device of claim 2, wherein the polycrystalline silicon film or the amorphous silicon film is formed on a wiring pattern and an insulating film, and then a heat treatment is performed to form copper silicide on the wiring pattern surface. Wiring manufacturing method. 제1항에 있어서, 상기 배선 패턴 표면에 형성되는 구리 실리사이드는 Cu5Si3, CuSi, Cu3Si 중 선택된 어느 하나로 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the copper silicide formed on the surface of the wiring pattern is formed of any one selected from Cu 5 Si 3 , CuSi, and Cu 3 Si. 제2항에 있어서, 상기 다결정 실리콘 또는 비정질 실리콘은 저압화학기상증착법 또는 일렉트론 사이크로트론 레조넌스 화학기상증착법 중 선택된 어느 하나로 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 2, wherein the polycrystalline silicon or the amorphous silicon is formed by any one of a low pressure chemical vapor deposition method and an electron cyclotron resonance chemical vapor deposition method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007654A 1995-04-01 1995-04-01 Method for wiring line on a semiconductor device KR0167237B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007654A KR0167237B1 (en) 1995-04-01 1995-04-01 Method for wiring line on a semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950007654A KR0167237B1 (en) 1995-04-01 1995-04-01 Method for wiring line on a semiconductor device

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KR960039282A true KR960039282A (en) 1996-11-25
KR0167237B1 KR0167237B1 (en) 1999-02-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100357183B1 (en) * 1999-12-31 2002-10-19 주식회사 하이닉스반도체 Method for forming copper thin film of semiconductor device
CN117711918A (en) * 2024-02-05 2024-03-15 中国科学院长春光学精密机械与物理研究所 Low-temperature polysilicon film and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100357183B1 (en) * 1999-12-31 2002-10-19 주식회사 하이닉스반도체 Method for forming copper thin film of semiconductor device
CN117711918A (en) * 2024-02-05 2024-03-15 中国科学院长春光学精密机械与物理研究所 Low-temperature polysilicon film and preparation method thereof
CN117711918B (en) * 2024-02-05 2024-04-09 中国科学院长春光学精密机械与物理研究所 Low-temperature polysilicon film and preparation method thereof

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KR0167237B1 (en) 1999-02-01

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