KR960039283A - Wiring Manufacturing Method of Semiconductor Device - Google Patents

Wiring Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR960039283A
KR960039283A KR1019950007655A KR19950007655A KR960039283A KR 960039283 A KR960039283 A KR 960039283A KR 1019950007655 A KR1019950007655 A KR 1019950007655A KR 19950007655 A KR19950007655 A KR 19950007655A KR 960039283 A KR960039283 A KR 960039283A
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KR
South Korea
Prior art keywords
barrier layer
forming
copper
wiring
film
Prior art date
Application number
KR1019950007655A
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Korean (ko)
Other versions
KR0167238B1 (en
Inventor
박종욱
천성순
김동원
이원준
라사균
이영종
Original Assignee
문정환
엘지반도체 주식회사
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Priority to KR1019950007655A priority Critical patent/KR0167238B1/en
Publication of KR960039283A publication Critical patent/KR960039283A/en
Application granted granted Critical
Publication of KR0167238B1 publication Critical patent/KR0167238B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure

Abstract

본 발명은 반도체 소자의 배선 제조방법에 관한 것으로, 반도체기판 상에 절연막을 증착한 후 선택적으로 식각하여 콘택홀을 형성하는 공정과; 상기 기판 상에 제1장벽층을 형성하는 공정과; 상기 제1장벽층 상에 구리막을 형성하는 공정과; 상기 구리막 상에 제2장벽층을 형성하는 공정과; 상기 제1장벽층, 구리막 및, 제2장벽층을 선택식각하여 배선 패턴을 형성하는 공정 및, 상기 배선 패턴 측벽에 구리 실리사이드 측벽을 형성하는 공정을 거쳐 배선 제조를 완료하므로써, 1) 구리 배선의 장점인 낮은 저항(low resistivity)(알루미늄의 저항치; 2.65μΩcm, 구리의 저항치; 1.7μΩcm) 및 우수한 일렉트로마이그레이션(electromigration) 특성을 가질 수 있으며, 2) 낮은 내산화성 및 유전막과의 낮은 접촉특성 등을 향상시킬 수 있고, 3) 단결정 실리콘내에서의 빠른 확산율 특성을 저하시켜 소자의 특성을 향상시킬 수 있는 고신뢰성의 배선을 구현할 수 있게 된다.The present invention relates to a method for manufacturing a wiring of a semiconductor device, comprising: forming a contact hole by selectively etching an insulating film on a semiconductor substrate; Forming a first barrier layer on the substrate; Forming a copper film on the first barrier layer; Forming a second barrier layer on the copper film; 1) copper wiring by completing the process of forming a wiring pattern by selectively etching the first barrier layer, the copper film, and the second barrier layer, and forming a copper silicide sidewall on the sidewall of the wiring pattern. Low resistivity (resistance of aluminum; 2.65μΩcm, resistivity of copper; 1.7μΩcm) and excellent electromigration characteristics, 2) low oxidation resistance, low contact with dielectric film, etc. It is possible to improve the characteristics of the device and to improve the characteristics of the device by reducing the fast diffusion rate characteristics in the single crystal silicon.

Description

반도체 소자의 배선 제조방법Wiring Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2(가)도 내지 제2(라)도는 본 발명에 따른 반도체 소자의 구리 배선층 제조방법을 도시한 공정수순도.2 (a) to 2 (d) are process flowcharts showing a method for manufacturing a copper wiring layer of a semiconductor device according to the present invention.

Claims (8)

반도체 기판 상에 절연막을 증착한 후 선택적으로 식각하여 콘택홀을 형성하는 공정과; 상기 기판 상에 제1장벽층을 형성하는 공정과; 상기 제1장벽층 상에 구리막을 형성하는 공정과; 상기 구리막 상에 제2장벽층을 형성하는 공정과; 상기 제1장벽층, 구리막 및, 제2장벽층을 선택식각하여 배선 패턴을 형성하는 공정 및; 상기 배선 패턴 측벽에 구리 실리사이드 측벽을 형성하여 공정을 포함하여 이루어짐을 특징으로 하는 반도체 소자의 배선 제조방법.Depositing an insulating film on a semiconductor substrate and then selectively etching to form contact holes; Forming a first barrier layer on the substrate; Forming a copper film on the first barrier layer; Forming a second barrier layer on the copper film; Forming a wiring pattern by selectively etching the first barrier layer, the copper film, and the second barrier layer; And forming a copper silicide sidewall on the sidewall of the wiring pattern. 제1항에 있어서, 상기 구리 실리사이드 측벽을 형성하는 공정은 스퍼터링법 또는 화학기상증착법을 이용하여 배선 패턴이 형성된 기판상에 구리 실리사이드층을 형성한 후 에치백하는 공정을 더 포함하여 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the forming of the copper silicide sidewall further comprises forming a copper silicide layer on the substrate on which the wiring pattern is formed by sputtering or chemical vapor deposition. A wiring manufacturing method of a semiconductor device. 제1항에 있어서, 상기 제2장벽층은 구리 실리사이드로 형성됨을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the second barrier layer is formed of copper silicide. 제1항에 있어서, 상기 제1장벽층은 TiN 또는 TiW 중 선택된 어느 하나로 형성됨을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the first barrier layer is formed of any one selected from TiN and TiW. 제3항에 있어서, 상기 제2장벽층인 구리 실리사이드는 실리콘 이온을 구리막 표면에 주입시키고 열처리하는 방법과, SiH4분위기에서 열처리하는 방법 중 선택된 어느 하나로 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법. 4. The wiring fabrication of claim 3, wherein the copper silicide as the second barrier layer is formed by any one selected from a method of implanting and heat treating silicon ions onto a surface of a copper film and a method of heat treating in an SiH 4 atmosphere. Way. 제1항에 있어서, 상기 반도체 소자의 배선 제조방법은 제2장벽층 위에 절연막을 더 포함하여 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the wiring manufacturing method of the semiconductor device further comprises an insulating film on the second barrier layer. 제1항에 있어서, 상기 제2장벽층은 TiN으로 형성됨을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the second barrier layer is formed of TiN. 제1항에 있어서, 상기 구리 실리사이드 측벽은 TiN으로 대체 가능한 것을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the copper silicide sidewall is replaced with TiN. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007655A 1995-04-01 1995-04-01 Method of wiring line on a semiconductor device KR0167238B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007655A KR0167238B1 (en) 1995-04-01 1995-04-01 Method of wiring line on a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007655A KR0167238B1 (en) 1995-04-01 1995-04-01 Method of wiring line on a semiconductor device

Publications (2)

Publication Number Publication Date
KR960039283A true KR960039283A (en) 1996-11-25
KR0167238B1 KR0167238B1 (en) 1999-02-01

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KR1019950007655A KR0167238B1 (en) 1995-04-01 1995-04-01 Method of wiring line on a semiconductor device

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