KR970072090A - Method for forming wiring layer of semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a wiring layer of a semiconductor device, and in the present invention, an interlayer insulating film is formed on a semiconductor substrate on which active regions of first and second conductivity types are formed in order to form a wiring layer, A first contact hole exposing the active region of the first conductivity type and a second contact hole of a predetermined depth for forming an intermediate wiring layer are formed using the first contact hole and the second contact hole, Depositing a polysilicon film of a first conductivity type with a sufficient thickness and forming a third contact hole exposing the active region of the second conductivity type using a photolithography process on the resultant product, A polysilicon film of a second conductivity type is deposited to a thickness sufficient for deposition, and a CMP (Chemical Mechanical Polishing) process is performed until the top surface of the interlayer insulating film is exposed. According to the present invention, when contacts of different conductivity types are simultaneously formed and used as an intermediate wiring layer, the metal process can be performed more efficiently.

Description

Method for forming wiring layer of semiconductor device

Since this is a trivial issue, I did not include the contents of the text.

FIGS. 1 to 5 are cross-sectional views illustrating a method of forming a wiring layer of a semiconductor device according to the present invention in accordance with a process order.

Claims (3)

A method of manufacturing a semiconductor device, the method comprising: forming an interlayer insulating film on a semiconductor substrate having active regions of first and second conductivity types formed thereon; forming a first contact hole exposing the active region of the first conductivity type on the interlayer insulating film using a photolithography process; Forming a second contact hole having a predetermined depth for forming an intermediate wiring layer; depositing a polysilicon film of a first conductivity type to a thickness sufficient to completely fill the first and second contact holes; Forming a third contact hole exposing the active region of the second conductivity type using a photolithography process on the resultant structure; forming a third contact hole exposing the active region of the second conductivity type using a photolithography process; And a step of performing a CMP (Chemical Mechanical Polishing) process until exposed on the upper surface of the interlayer insulating film. The method according to claim 1, further comprising the steps of: depositing a refractory metal film on the resulting product after the step of performing the CMP process; and conducting a silicidation process on the resultant product to form first and second contacts Forming a metal silicide film on an upper portion of the polysilicon film of the second conductivity type; and removing the refractory metal film remaining on the upper portion of the interlayer insulating film. The method according to claim 2, wherein the refractory metal is Ti, Co, W or Mo. ※ Note: It is disclosed by the contents of the first application.