KR980006342A - Method for manufacturing capacitor of semiconductor device - Google Patents

Method for manufacturing capacitor of semiconductor device Download PDF

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Publication number
KR980006342A
KR980006342A KR1019960024260A KR19960024260A KR980006342A KR 980006342 A KR980006342 A KR 980006342A KR 1019960024260 A KR1019960024260 A KR 1019960024260A KR 19960024260 A KR19960024260 A KR 19960024260A KR 980006342 A KR980006342 A KR 980006342A
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South Korea
Prior art keywords
film
titanium
titanium nitride
thickness
nitrogen
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KR1019960024260A
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Korean (ko)
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KR100235955B1 (en
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홍권
유상호
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 캐패시터 저장전극으로 티타늄과 질소의 비가 1:1인 티타늄나이트라이드를 형성하면 티타늄/티타늄나이트라이드 계면에 질소의 조성 변위를 갖는 티타늄나이트라이드 막을형성시킬 수 있게 된다. 조성변화를 갖는 티타늄나이트라이드 막을 티타늄/티타늄나이트라이드 계면에 형성해 줌으로써 반도체 소자의 열공정시 다결정실리콘 플러그와 티타늄의 고상반응에 의해 형성된 티타늄실라시이드의 형성에 의한 인장응력으로 금속확산 방지막인 티타늄나이트라이드의 파괴현상을 억제하고, 또한 입계를 통한 실리콘의 확산을 방지하여 캐패시터의 전기적 특성을 향상시킬 수 있게 된다.The present invention relates to a method for fabricating a capacitor of a semiconductor device, in which titanium nitride having a ratio of titanium to nitrogen of 1: 1 is formed as a capacitor storage electrode, thereby forming a titanium nitride film having a nitrogen composition shift at the titanium / titanium nitride interface . A titanium nitride film having a compositional change is formed on the titanium / titanium nitride interface so that a tensile stress due to the formation of titanium silacide formed by the solid-phase reaction of the polycrystalline silicon plug and the titanium during thermal processing of the semiconductor device, The breakdown phenomenon of the ridges can be suppressed and diffusion of silicon through the grain boundaries can be prevented, so that the electrical characteristics of the capacitor can be improved.

Description

반도체 소자의 캐패시터 제조방법Method for manufacturing capacitor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도 내재 제6도는 본 발명의 일 실시예에 따른 캐패시터를 제조하는 단계를 도시한 단면도.FIG. 6 is a cross-sectional view illustrating a step of manufacturing a capacitor according to an embodiment of the present invention. FIG.

Claims (10)

반도체 소자의 캐패시터 제조방법에 있어서, 반도체기판의 상부에 층간절연막을 증착하고, 상기 층간 절연막의 일정부분을 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀에 다결정실리콘 플러그를 형성하는 단계와, 전체기판 상부에 금속확산방지막으로 이용되는 티타늄 막 형성하는 단계와, 상기 티타늄 막 상부에 질소의 조성변위를 갖는 티타늄나이트라이드막을 형성하는 단계와, 제1저장전극 마스크를 이용한 식각 공정으로 상기 다결정실리콘 플러그와 접속되는 티타늄 패턴과 티타늄나이트라이드 패턴을 형성하는 단계와, 루테늄 막과 이산화 루테늄 막을 적층하고, 제2저장전극 마스크를 이용한 식각 공정으로 상기 티타늄 패턴과 티타늄나이트라이드 패턴의 상부 및 측벽에 남는 루테늄 패턴과 이산화 루테늄 패턴을 형성하는 단계와, 전체 구조 상부에 고유전체 막을 증착한 후, 그 상부에 상부전극으로 사용되는 내산화성 금속막을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법.A method of manufacturing a capacitor of a semiconductor device, comprising the steps of: depositing an interlayer insulating film on an upper surface of a semiconductor substrate and etching a predetermined portion of the interlayer insulating film to form a contact hole; forming a polysilicon plug in the contact hole; Forming a titanium nitride film having a compositional shift of nitrogen on the titanium film; forming a titanium nitride film on the entire upper surface of the substrate by using an etching process using a first storage electrode mask; Forming a titanium nitride pattern and a titanium nitride pattern, which are connected to the plug; depositing a ruthenium film and a ruthenium dioxide film; and etching the titanium nitride film and the ruthenium dioxide film on the upper and side walls of the titanium pattern and the titanium nitride pattern, Forming a ruthenium pattern and a ruthenium dioxide pattern; Depositing a high dielectric film on top of the structure, and then forming an oxidation-resistant metal film used as an upper electrode on the high dielectric film. 제1항에 있어서, 상기 다결정실리콘 플러그는 화학기상증착법으로 500A 내지 3000A두께의 다결정실리콘층을 증착한 후 전면 식각으로 에치백하여 상기 콘택홀 내에만 다결정실리콘이 남도록 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.2. The semiconductor device according to claim 1, wherein the polycrystalline silicon plug is formed by depositing a polycrystalline silicon layer having a thickness of 500A to 3000A by a chemical vapor deposition method and then etching back the polycrystalline silicon layer by front etching so that polycrystalline silicon is left only in the contact hole. Lt; / RTI > 제1항에 있어서, 상기 티타늄 막은 100A 내지 1000A의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the titanium film is deposited to a thickness of 100A to 1000A. 제1항에 있어서, 상기 질소의 조성변위를 갖는 티타늄나이트라이드막 상부면에 상기 티타늄과 질소의 비가1:1인 티타늄나이트라이드 막을 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein a titanium nitride film having a titanium to nitrogen ratio of 1: 1 is deposited on the top surface of the titanium nitride film having the compositional shift of nitrogen. 제4항에 있어서, 상기 질소의 조성변위를 갖는 티타늄나이트라이드막(Til-xNx)의 질소 조성비는 0.1에서 0.5이고 100A 내지 500A의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.5. The method according to claim 4, wherein the nitrogen composition ratio of the titanium nitride film (Til-xNx) having the compositional shift of nitrogen is 0.1 to 0.5 and the thickness is 100A to 500A. 제1항에 있어서, 상기 티타늄과 질소의 비가1:1인 티타늄나이트라이드막은 200A 내지 2000A의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The method of claim 1, wherein the titanium nitride film having a ratio of titanium to nitrogen of 1: 1 is deposited to a thickness of 200A to 2000A. 제1항에 있어서, 상기 루테늄 막은 100A 내지 1000A의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the ruthenium film is deposited to a thickness of 100A to 1000A. 제1항에 있어서, 상기 이산화 루테늄 막은 500A 내지 5000A의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the ruthenium dioxide film is deposited to a thickness of 500A to 5000A. 제1항에 있어서, 상기 고 유전체막은 300A 내지 2000A 두께의 STO 또는 BST로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.2. The method of claim 1, wherein the high dielectric film is deposited with STO or BST having a thickness of 300A to 2000A. 제1항에 있어서, 상기 내산화성 금속막은 화학기상증착법으로 500A 내지 2000A 두께의 이산화루테늄 또는 백금으로 중착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the oxidation-resistant metal film is doped with ruthenium dioxide or platinum to a thickness of 500A to 2000A by chemical vapor deposition.
KR1019960024260A 1996-06-27 1996-06-27 Method for manufacturing capacitor semiconductor device KR100235955B1 (en)

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US8828821B2 (en) * 2009-09-18 2014-09-09 Intermolecular, Inc. Fabrication of semiconductor stacks with ruthenium-based materials

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US5381302A (en) * 1993-04-02 1995-01-10 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same

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