KR980005570A - Method of forming plug of semiconductor element - Google Patents

Method of forming plug of semiconductor element Download PDF

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Publication number
KR980005570A
KR980005570A KR1019960024938A KR19960024938A KR980005570A KR 980005570 A KR980005570 A KR 980005570A KR 1019960024938 A KR1019960024938 A KR 1019960024938A KR 19960024938 A KR19960024938 A KR 19960024938A KR 980005570 A KR980005570 A KR 980005570A
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KR
South Korea
Prior art keywords
metal
forming
plug
etching
semiconductor device
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KR1019960024938A
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Korean (ko)
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KR100221584B1 (en
Inventor
최경근
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김주용
현대전자산업 주식회사
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Priority to KR1019960024938A priority Critical patent/KR100221584B1/en
Priority to TW086108491A priority patent/TW350129B/en
Priority to JP9165857A priority patent/JPH1065005A/en
Publication of KR980005570A publication Critical patent/KR980005570A/en
Application granted granted Critical
Publication of KR100221584B1 publication Critical patent/KR100221584B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

본 발명은 반도체 소자의 플러그 형성 방법에 관한 것으로, 플러그(Plug)를 형성하기 위한 식각 공정시 금속의 표면 거칠기에 의해 발생되는 불균일 식각을 방지하기 위하여 콘택 홀이 매립되도록 제1금속을 증착한 후 상기 제1금속막상에 상기 제1금속과의 식각 선택비가 크며 층 덮힘 특성이 열악한 제2금속을 증착한다. 그러므로 플러그를 형성하기 위한 식각 공정시 상기 제1금속의 표면 거칠기에 의해 발생되는 불균일 식각이 방지되어 잔류물의 생성이 방지되며, 따라서 금속층간의 접촉이 안정되어 소자의 전기적 특성 및 수율이 향상될 수 있는 반도체 소자의 플러그 형성 방법에 관한 것이다.The present invention relates to a method for forming a plug of a semiconductor device, in which a first metal is deposited so that a contact hole is buried in order to prevent uneven etching caused by surface roughness of a metal during an etching process for forming a plug Depositing a second metal on the first metal film having a high etch selectivity to the first metal and poor layer coverage characteristics. Therefore, in the etching process for forming the plug, the uneven etching caused by the surface roughness of the first metal is prevented to prevent the formation of the residue, so that the contact between the metal layers can be stabilized and the electrical characteristics and yield of the device can be improved To a method of forming a plug of a semiconductor element.

Description

반도체 소자의 플러그(Plug) 형성 방법Method of forming plug of semiconductor element

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3a 내지 제3e도는 본 발명에 따른 반도체 소자의 플러그 형성 방법을 설명하기 위한 소자의 단면도.Figs. 3A to 3E are sectional views of a device for explaining a method of forming a plug of a semiconductor device according to the present invention. Fig.

Claims (10)

반도체 소자의 플러그 형성 방법에 있어서, 접합부가 형성된 실리콘 기판상에 절연층을 형성한 후 상기 접합부가 노출되도록 상기 절연층을 패터닝하여 콘택 홀을 형성하는 제1단계와 상기 제1단계로부터 전체 상부면에 베리어 금속층을 형성한 후 상기 콘택 홀이 매립되도록 전체 상부면에 제1금속을 증착하는 제2단계와 상기 제2단계로부터 상기 제1금속상에 상기 제1금속과의 식각 선택비가 크며 층 덮힘 특성이 열악한 제2금속을 증착하는 제3단계와 상기 제3단계로부터 식각 선택비 차이를 이용하여 상기 제2및 제1금속을 소정 두께 식각하는 제4단계와, 상기 제4단계로부터 상기 절연층의 표면이 노출되는 시점까지 나머지 두께의 상기 제1금속 및 베리어 금속층을 순차적으로 식각하는 제5단계로 이루어지는 것을 특징으로하는 반도체 소자의 플러그 형성 방법.A method of forming a plug of a semiconductor device, the method comprising: a first step of forming an insulating layer on a silicon substrate on which a bonding portion is formed, and then patterning the insulating layer to expose the bonding portion to form a contact hole; A second step of depositing a first metal on the entire upper surface so that the contact hole is buried after forming a barrier metal layer on the first metal and a second step of etching the first metal from the second step, A third step of depositing a second metal having poor characteristics and a fourth step of etching the second and first metals to a predetermined thickness using an etch selection ratio difference from the third step, And a fifth step of sequentially etching the first metal and the barrier metal layer of the remaining thickness until the surface of the semiconductor element is exposed. / RTI > 제1항에 있어서 상기 베리어 금속층은 티타늄(Ti) 및 티타늄 나이트라이드(TiN)가 순차적으로 증착된 것을 특징으로 하는 반도체 소자의 플라그 형성 방법.The method of claim 1, wherein the barrier metal layer is formed by sequentially depositing titanium (Ti) and titanium nitride (TiN). 제1항에 있어서 상기 제1금속은 텅스텐(W)인 것을 특징으로 하는 반도체 소자의 플러그 형성방법.The method of claim 1, wherein the first metal is tungsten (W). 제1항에 있어서 상기 제2금속은 티타늄 나이트라이드(TiN), 코발트(Co), 크롬(Cr), 구리(Cu), 루테늄(Ru) 중 하나인 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.The method of claim 1, wherein the second metal is one of titanium nitride (TiN), cobalt (Co), chromium (Cr), copper (Cu), and ruthenium (Ru). 제1 또는 제4항에 있어서 상기 제2금속은 스퍼터링 방법에 의해 30 내지 100Å의 두께로 증착되는 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.The method for forming a plug of a semiconductor device according to claim 1 or 4, wherein the second metal is deposited to a thickness of 30 to 100 ANGSTROM by a sputtering method. 제1항에 있어서 상기 제1금속과 상기 제2금속의 식각 선택비는 10내지 100:1인 것을 특징으로하는 반도체 소자의 플러그 형성 방법.The method of claim 1, wherein the etch selectivity of the first metal and the second metal is 10 to 100: 1. 상기 제1금속과 상기 제2금속의 식각 선택비는 5 내지 50:1인 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.Wherein the etch selectivity of the first metal and the second metal is 5 to 50: 1. 제1항에 있어서 상기 제4 및 제5단계의 식각 공정은 반응성 이온 식각 방법으로 실시되는 것을 특징으로 하는 반도체 소자의 플러그 형성방법.The method for forming a plug of a semiconductor device according to claim 1, wherein the etching process of the fourth and fifth steps is performed by a reactive ion etching method. 제1항에 있어서 상기 제4 및 5단계의 식각 공정은 화학적 기계적 연마 방법으로 실시되는 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.The method for forming a plug of a semiconductor device according to claim 1, wherein the etching process of the fourth and fifth steps is performed by a chemical mechanical polishing method. 제1항에 있어서 상기 제4 및 5단계의 식각 공정은 반응성 이온 식각 방법 및 화학적 기계적 연마 방법이 병행되어 실시되는 것을 특징으로 하는 반도체 소자의 플러그 형성방법.The method for forming a plug of a semiconductor device according to claim 1, wherein the etching steps of the fourth and fifth steps are performed by a reactive ion etching method and a chemical mechanical polishing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960024938A 1996-06-28 1996-06-28 Forming method for plug of semiconductor device KR100221584B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019960024938A KR100221584B1 (en) 1996-06-28 1996-06-28 Forming method for plug of semiconductor device
TW086108491A TW350129B (en) 1996-06-28 1997-06-18 Manufacturing method of semiconductor formation latches the invention relates to a manufacturing method of semiconductor formation latches
JP9165857A JPH1065005A (en) 1996-06-28 1997-06-23 Method for forming semiconductor element plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024938A KR100221584B1 (en) 1996-06-28 1996-06-28 Forming method for plug of semiconductor device

Publications (2)

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KR980005570A true KR980005570A (en) 1998-03-30
KR100221584B1 KR100221584B1 (en) 1999-09-15

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TW (1) TW350129B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100671561B1 (en) * 2004-12-27 2007-01-19 동부일렉트로닉스 주식회사 Method of forming interconnection line for semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472722B1 (en) * 1999-06-30 2005-03-07 주식회사 하이닉스반도체 Method for forming line and plug metal wire capable of reducing damage of under layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100671561B1 (en) * 2004-12-27 2007-01-19 동부일렉트로닉스 주식회사 Method of forming interconnection line for semiconductor device

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TW350129B (en) 1999-01-11
KR100221584B1 (en) 1999-09-15
JPH1065005A (en) 1998-03-06

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