KR970018115A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR970018115A
KR970018115A KR1019950031375A KR19950031375A KR970018115A KR 970018115 A KR970018115 A KR 970018115A KR 1019950031375 A KR1019950031375 A KR 1019950031375A KR 19950031375 A KR19950031375 A KR 19950031375A KR 970018115 A KR970018115 A KR 970018115A
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KR
South Korea
Prior art keywords
forming
metal wiring
film
insulating film
thickness
Prior art date
Application number
KR1019950031375A
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Korean (ko)
Inventor
조경원
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950031375A priority Critical patent/KR970018115A/en
Publication of KR970018115A publication Critical patent/KR970018115A/en

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Abstract

본 발명은 1차 금속배선막의 측벽에 스페이서를 형성하여 2차 금속배선막의 단차 피복비를 향상시켜 금속배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속배선 형성방법에 관한 것으로서, 반도체 기판상에 절연막을 형성하는 공정과, 절연막상에 1차 금속배선막을 형성하는 공정과, 1차 금속배선막의 측벽에 스페이서를 형성하는 공정과, 층간 절연막을 기판 전면에 형성하는 공정과, 층간 절연막상에 2차 금속배선막을 형성하는 공정을 포함한다.The present invention relates to a method for forming a metal wiring of a semiconductor device capable of improving the reliability of the metal wiring by forming a spacer on the sidewall of the primary metal wiring film to improve the step coverage ratio of the secondary metal wiring film. Forming, forming a primary metal wiring film on the insulating film, forming a spacer on the sidewall of the primary metal wiring film, forming an interlayer insulating film on the entire substrate, and forming a secondary metal on the interlayer insulating film. A step of forming a wiring film is included.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(A)∼(E)는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성 공정도이다.2A to 2E are process diagrams for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

Claims (7)

반도체 기판상에 절연막을 형성하는 공정과, 절연막상에 1차 금속배선막을 형성하는 공정과, 1차 금속배선막의 측벽에 스페이서를 형성하는 공정과, 층간 절연막을 기판 전면에 형성하는 공정과, 층간 절연막상에 2차 금속배선막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Forming an insulating film on the semiconductor substrate, forming a primary metal wiring film on the insulating film, forming a spacer on the sidewall of the primary metal wiring film, forming an interlayer insulating film on the entire surface of the substrate, And forming a secondary metal wiring film on the insulating film. 제1항에 있어서, 스페이서는 고융점 금속, 전이 금속 또는 금속 화합물중 하나를 증착한 후 이방성 건식식각하여 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the spacer is formed by depositing one of a high melting point metal, a transition metal, or a metal compound, followed by anisotropic dry etching. 제2항에 있어서, 스페이서 형성용으로 증착되는 막의 두께는 1차 금속배선막의 증착 두께에 따라 정해지는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.3. The method of claim 2, wherein the thickness of the film deposited for spacer formation is determined according to the deposition thickness of the primary metal wiring film. 제3항에 있어서, 증착되는 막의 두께는 100 내지 20000Å인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.4. The method of claim 3, wherein the deposited film has a thickness of 100 to 20000 GPa. 제1항에 있어서, 스페이서는 절연막을 증착한 후 이방성 건식식각하여 스페이서를 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the spacers are anisotropically dry etched after depositing an insulating film to form the spacers. 제5항에 있어서, 스페이서 형성용 절연막의 두께는 1차 금속배선막의 증착 두께에 따라 정해지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 5, wherein the thickness of the insulating film for forming a spacer is determined according to the deposition thickness of the primary metal wiring film. 제6항에 있어서, 절연막의 두께는 100 내지 20000Å인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.7. The method of forming a metal wiring of a semiconductor device according to claim 6, wherein the insulating film has a thickness of 100 to 20000 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950031375A 1995-09-22 1995-09-22 Metal wiring formation method of semiconductor device KR970018115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950031375A KR970018115A (en) 1995-09-22 1995-09-22 Metal wiring formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950031375A KR970018115A (en) 1995-09-22 1995-09-22 Metal wiring formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR970018115A true KR970018115A (en) 1997-04-30

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Application Number Title Priority Date Filing Date
KR1019950031375A KR970018115A (en) 1995-09-22 1995-09-22 Metal wiring formation method of semiconductor device

Country Status (1)

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KR (1) KR970018115A (en)

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