KR950007100A - How to form self-aligned contacts - Google Patents
How to form self-aligned contacts Download PDFInfo
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- KR950007100A KR950007100A KR1019930016622A KR930016622A KR950007100A KR 950007100 A KR950007100 A KR 950007100A KR 1019930016622 A KR1019930016622 A KR 1019930016622A KR 930016622 A KR930016622 A KR 930016622A KR 950007100 A KR950007100 A KR 950007100A
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- conductive material
- self
- contact
- spacer
- depositing
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 기관(1)상에 하두전도층 패턴(4)이 형성된 웨이퍼상의 자기정렬 콘택 형성 방법에 있어서, 웨이퍼 전체구조 상부에 평탄화된 절연막(7)을 형성하고 상기 평탄화된 절연막(7)상에 이후에 콘택되는 제2전도물(8)과 같은 물질인 제1전도물(9)을 증착하는 단계, 상기 제1전도물(9) 및 절연막(7)을 자기정렬 콘택 마스크(10)를 이용 식각하여 콘택 홀을 형성하는 단계, 웨이퍼 전체구조 상부에 스페이서 형서용 산화막(11)을 증착하는 단계, 상기 제1전도물(9)을 식각 정지층으로 하여 상기 스페이서 형성용 산화막(11)을 식각하되 형성되어 있는 콘택 홀내의 가장자리 벽에 스페이서 산화막(11′)을 형성하도록 스페이서 식각하는 단계, 웨이퍼 전체구조 상부에 제2전도물(8)은 증착하여 반도체 기판상에 제2전도물(8)을 자기정렬 콘택시키는 것을 특징으로 하는 자기정렬 콘택 형성 방법에 관한 것으로, 자기정렬 콘택 형성시 스페이서 산화막을 사용하여 하부 전도층과의 브리지를 방지함으로써 반도체 소자의 특성 및 수율을 향상시키는 효과가 있다.The present invention provides a method for forming a self-aligned contact on a wafer on which a lower head conductive layer pattern (4) is formed on a semiconductor engine (1), wherein the planarized insulating film (7) is formed on the entire wafer structure. Depositing a first conductive material 9 of the same material as the second conductive material 8 which is subsequently contacted on the first conductive material 9 and the insulating film 7 by the self-aligned contact mask 10. Forming a contact hole by etching, depositing a spacer type oxide film 11 on the entire structure of the wafer, and forming the spacer film 11 using the first conductive material 9 as an etch stop layer. Etching to form a spacer oxide film 11 ′ on the edge wall of the contact hole, wherein the second conductive material 8 is deposited on the entire wafer structure to deposit the second conductive material on the semiconductor substrate. 8) self-aligning contact By self alignment on the contact forming method, by using a self-aligned contact is formed when the spacer oxide film prevents a bridge between the lower conductive layer has the effect of improving the characteristics of the semiconductor element and the yield.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2A도 내지 제2E도는 본 발명의 자기정렬 콘택 형성 방법에 따른 비트라인 형성 공정도.2A through 2E are bit line forming process diagrams according to the self-aligned contact forming method of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930016622A KR950007100A (en) | 1993-08-25 | 1993-08-25 | How to form self-aligned contacts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930016622A KR950007100A (en) | 1993-08-25 | 1993-08-25 | How to form self-aligned contacts |
Publications (1)
Publication Number | Publication Date |
---|---|
KR950007100A true KR950007100A (en) | 1995-03-21 |
Family
ID=66817750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930016622A KR950007100A (en) | 1993-08-25 | 1993-08-25 | How to form self-aligned contacts |
Country Status (1)
Country | Link |
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KR (1) | KR950007100A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100382727B1 (en) * | 2000-12-07 | 2003-05-09 | 삼성전자주식회사 | Method for fabricating pad without void using self-aligned contact etch process in semiconductor device |
-
1993
- 1993-08-25 KR KR1019930016622A patent/KR950007100A/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100382727B1 (en) * | 2000-12-07 | 2003-05-09 | 삼성전자주식회사 | Method for fabricating pad without void using self-aligned contact etch process in semiconductor device |
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