KR950015592A - Tungsten Plug Formation Method - Google Patents

Tungsten Plug Formation Method Download PDF

Info

Publication number
KR950015592A
KR950015592A KR1019930024236A KR930024236A KR950015592A KR 950015592 A KR950015592 A KR 950015592A KR 1019930024236 A KR1019930024236 A KR 1019930024236A KR 930024236 A KR930024236 A KR 930024236A KR 950015592 A KR950015592 A KR 950015592A
Authority
KR
South Korea
Prior art keywords
tungsten
contact hole
etching
forming
depositing
Prior art date
Application number
KR1019930024236A
Other languages
Korean (ko)
Other versions
KR970007823B1 (en
Inventor
황성보
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR93024236A priority Critical patent/KR970007823B1/en
Publication of KR950015592A publication Critical patent/KR950015592A/en
Application granted granted Critical
Publication of KR970007823B1 publication Critical patent/KR970007823B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 기억소자 또는 논리 (Logic) 소자의 제조 공정에 있어서 콘택홀의 폭이 상이한 두 콘택홀에 텅스텐 플러그를 형성할때 텅스텐을 2차에 걸쳐서 증착하고 에치백 공정으로 텅스텐 플러그를 형성함으로써 텅스텐의 낭비를 감소시키고, 콘택홀에 완전하게 테워진 플러그를 형성하는 공정기술이다.According to the present invention, when a tungsten plug is formed in two contact holes having different widths of contact holes in a semiconductor memory device or a logic device manufacturing process, the tungsten is deposited twice and the tungsten plug is formed by an etch back process. It is a process technology to reduce the waste of waste and to form a fully opened plug in the contact hole.

Description

텅스텐 플러그 형성방법Tungsten Plug Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따리 폭이 상이한 콘택홀에 대하여 2차 증착으로 텅스텐을 입힌 상태의 단면도.2 is a cross-sectional view of tungsten coated by secondary deposition for contact holes of different widths according to the present invention.

제3a도 내지 제3e도는 본 발명에 따라 폭이 상이한 콘택홀에 대하여 텅스텐을 2차로 증착하여 텅스텐 플러그를 제조하는 단계를 도시한 단면도.3a to 3e are cross-sectional views showing a step of manufacturing a tungsten plug by secondary deposition of tungsten for the different width of the contact hole in accordance with the present invention.

Claims (3)

반도체 소자 제조공정중 폭이 상이한 두 콘택홀에 대하여 전면성 텅스텐 플러그를 형성하는 방법에 있어서, 실리콘 기판 또는 전도체 위의 절연막에 서로 폭이 상이한 콘택홀을 형성하는 단계와. 전면성 텅스텐 증착을 위해 전체구조 상부에 접합층을 형성하는 단계와, 폭이좁은 콘택홀에 태울수 있는 두께로 텅스텐을 상기 접합층 상부에 1차로 증착하는 단계와, 상기 텅스텐과 식각 선택도를 달리하는 식각 방지층을 7차 텅스텐 상부에 증착하는 단계와, 폭이 넓은 콘택홀의 좁혀진 폭을 채울수 있는 두께로 텅스텐을 식각 방지층 상부에 2차 증착하는 단계와, 상기 2차로 증착된 텅스텐을 에치백하되 식각방지층까지 식각하는 단계와, 노출된 식각 방지층을 선택적으로 식각하는 단계와, 노출된 텅스덴을 에치백하되 상부에 있는 접합층이 노출되기까지 식각하는 단계와, 노출된 접합층을 식각하여 폭이 좁은 콘택홀과 폭이 넓은 콘택홀에 텅스텐이 패워진 플러그를 형성하는 단계로 이루어지는 것을 특징으로 하는 텅스텐 플리그 형성방법.A method of forming a full-tungsten plug for two contact holes of different widths during a semiconductor device manufacturing process, the method comprising: forming contact holes of different widths in an insulating film on a silicon substrate or a conductor; Forming a bonding layer on top of the entire structure for depositing full-tungsten tungsten, depositing tungsten on top of the bonding layer with a thickness that can be burned in a narrow contact hole, and forming the etching selectivity with the tungsten Depositing a different etch stop layer on top of the seventh tungsten, depositing tungsten on top of the etch stop layer to a thickness sufficient to fill the narrow width of the wide contact hole, and etching back the second deposited tungsten, Etching to the etch stop layer, selectively etching the exposed etch stop layer, etching back the exposed tungsten but etching until the bonding layer on the top is exposed, and etching the exposed bonding layer to the width And forming a tungsten-embedded plug in the narrow contact hole and the wide contact hole. 제7항에 있어서, 상기 1차로 증착되는 텅스텐의 두께는 좁은 콘택홀 폭의 50% 내지 60%로 하는 것을 특징으로 하는 텅스텐 플러그 형성방법.8. The method of claim 7, wherein the thickness of the first deposited tungsten is 50% to 60% of the narrow contact hole width. 제1항에 있어서. 상기 2차로 증착되는 텅스텐의 두께는 넓은 콘택홀에 1차로 텅스텐을 증착하고 남아있는 폭의 50% 내지 60%로 하는 것을 특징으로 하는 텅스텐 플러그 형성방법.The method of claim 1. The thickness of the tungsten to be deposited secondly is a tungsten plug forming method characterized in that the first depositing tungsten in a wide contact hole to 50% to 60% of the remaining width. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93024236A 1993-11-15 1993-11-15 Forming method of tungsten plug KR970007823B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93024236A KR970007823B1 (en) 1993-11-15 1993-11-15 Forming method of tungsten plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93024236A KR970007823B1 (en) 1993-11-15 1993-11-15 Forming method of tungsten plug

Publications (2)

Publication Number Publication Date
KR950015592A true KR950015592A (en) 1995-06-17
KR970007823B1 KR970007823B1 (en) 1997-05-17

Family

ID=19368082

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93024236A KR970007823B1 (en) 1993-11-15 1993-11-15 Forming method of tungsten plug

Country Status (1)

Country Link
KR (1) KR970007823B1 (en)

Also Published As

Publication number Publication date
KR970007823B1 (en) 1997-05-17

Similar Documents

Publication Publication Date Title
KR940020531A (en) Manufacturing method of metal plug in contact hole
KR900005589A (en) Semiconductor integrated circuit device and manufacturing method thereof
KR950021084A (en) Simultaneous Formation of Metal Wires and Contact Plugs
KR930009023A (en) Contact filling method by two-step deposition of selective tungsten thin film
KR950015592A (en) Tungsten Plug Formation Method
KR950025908A (en) Semiconductor device manufacturing method
KR930024106A (en) Contact Forming Method of Semiconductor Device
KR930011116A (en) Manufacturing Method of Semiconductor Device
KR950007100A (en) How to form self-aligned contacts
KR950025868A (en) Bit line formation method of semiconductor device
KR940016504A (en) Contact manufacturing method of semiconductor device
KR950006994A (en) Via plug formation method of semiconductor device
KR960019511A (en) Manufacturing Method of Semiconductor Device
KR950021285A (en) Metal wiring layer formation method
KR950001899A (en) Contact formation method during PLUG process
KR930006837A (en) Tungsten Selective Deposition Using Metal Bonding Layer
KR960002582A (en) Manufacturing method of semiconductor device
KR20010064076A (en) A method for forming electrode in semiconductor device
KR970052930A (en) Metal wiring film formation method of semiconductor device
KR20010004259A (en) A method for fabricating semiconductor device
KR970054239A (en) Nonvolatile Memory Device and Manufacturing Method
KR950009924A (en) Via plug formation method of semiconductor device
KR970077349A (en) Structure of Metal Wiring in Semiconductor Device and Manufacturing Method Thereof
KR970052188A (en) Metal wiring formation method of semiconductor device
KR960002547A (en) Contact hole formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100726

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee