KR950009924A - Via plug formation method of semiconductor device - Google Patents

Via plug formation method of semiconductor device Download PDF

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Publication number
KR950009924A
KR950009924A KR1019930018525A KR930018525A KR950009924A KR 950009924 A KR950009924 A KR 950009924A KR 1019930018525 A KR1019930018525 A KR 1019930018525A KR 930018525 A KR930018525 A KR 930018525A KR 950009924 A KR950009924 A KR 950009924A
Authority
KR
South Korea
Prior art keywords
forming
tungsten
semiconductor device
metal layer
via plug
Prior art date
Application number
KR1019930018525A
Other languages
Korean (ko)
Other versions
KR100188645B1 (en
Inventor
최경근
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930018525A priority Critical patent/KR100188645B1/en
Priority to US08/305,306 priority patent/US5409861A/en
Priority to JP6221490A priority patent/JP2786115B2/en
Priority to GB9425300A priority patent/GB2296128B/en
Publication of KR950009924A publication Critical patent/KR950009924A/en
Priority to US08/734,784 priority patent/USRE36475E/en
Priority to HK98110979A priority patent/HK1010423A1/en
Priority to US09/293,207 priority patent/USRE38383E1/en
Application granted granted Critical
Publication of KR100188645B1 publication Critical patent/KR100188645B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 비아 플러그(Via Plug) 형성방법에 관하여 기술한 것으로, 비아홀 저면을 이루는 금속층 계면에 텅스텐 핵(W-nuclei)을 형성한 후 습식식각방법으로 텅스텐 핵 사이로 노출된 금속층을 식각하여 다수의 식각홈을 형성하여 비아홀 저면의 표면적을 증가시키므로써 후공정인 비아 플러그 형성시 접촉면에서 접착력을 향상시키고 비아 저항을 감소시킬 수 있는 반도체 소자의 비아 플러그 형성방법에 관하여 기술된다.The present invention relates to a method of forming a via plug of a semiconductor device, and forms a tungsten nucleus (W-nuclei) at a metal layer interface forming a bottom of a via hole, and then wets a metal layer exposed between the tungsten nuclei by a wet etching method. By forming a plurality of etching grooves to increase the surface area of the bottom surface of the via hole, the method for forming a via plug of a semiconductor device capable of improving adhesion at the contact surface and reducing via resistance at the time of forming a via plug, which is a post-process.

Description

반도체 소자의 비아 플러그 형성방법Via plug formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (2)

반도체 소자의 비아 플러그 형성방법에 있어서, 기판(1)에 제1금속층(2)을 형성한 후, 전체구조 상부에 제1, 2 및 3절연층(3, 4 및 5)을 순차적으로 적층하여 평탄화하는 단계와, 상기 단계로부터 콘택 마스크를 이용하여 상기 제1금속층(2)을 상부의 소정부분이 노출될 때까지 상기 제3, 2 및 1 절연층(5, 4 및 3)을 식각하여 비아홀(6)을 형성하는 단계와, 상기 단계로부터 상기 비아홀(6)을 건식 처리한 후, 텅스텐 증착 반응기로 비아홀(6) 저면의 제1금속층(2) 계면부에 텅스텐을 증착하여 텅스텐 핵(7)을 형성하는 단계와, 상기 단계로부터 텅스텐과 식각 선택도가 다른 습식식각용액을 사용하여 상기 텅스텐 핵(7) 사이로 노출된 제 1금속층(2)을 식각하여 제1금속층(2) 표면에 다수의 식각홈(8)을 형성하는 단계와, 상기 단계로부터 상기 비아홀(6)을 LPCVD 반응기로 비아 플러그(9)를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 비아 플러그 형성방법.In the method for forming a via plug of a semiconductor device, after forming the first metal layer 2 on the substrate 1, the first, second and third insulating layers 3, 4 and 5 are sequentially stacked on the entire structure. Planarizing and etching the third, second and first insulating layers 5, 4 and 3 until the predetermined portion of the first metal layer 2 is exposed using a contact mask from the step. (6) forming and drying the via hole 6 from the step, and then depositing tungsten at the interface of the first metal layer 2 at the bottom of the via hole 6 with a tungsten deposition reactor to obtain a tungsten nucleus 7 ) And etching the first metal layer 2 exposed between the tungsten nuclei 7 using a wet etching solution having a different etching selectivity from tungsten. Forming an etch groove (8) of the via, and from the step the ratio of the via holes (6) to the LPCVD reactor Via plug forming a semiconductor device characterized in that comprising the step of forming a plug (9). 제1항에 있어서, 상기 텅스텐 핵(7)은 텅스텐 증착 반응기로 핵 하나 하나의 크기가 500∼1000Å 정도가 되돌고 증착하는 것을 특징으로 하는 반도체 소자의 비아 플러그 형성방법.The method of forming a via plug of a semiconductor device according to claim 1, wherein the tungsten nucleus (7) is deposited with a tungsten deposition reactor having a size of about 500 to 1000 micrometers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930018525A 1993-09-15 1993-09-15 Via plug forming method of semiconductor device KR100188645B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019930018525A KR100188645B1 (en) 1993-09-15 1993-09-15 Via plug forming method of semiconductor device
US08/305,306 US5409861A (en) 1993-09-15 1994-09-15 Method of forming a via plug in a semiconductor device
JP6221490A JP2786115B2 (en) 1993-09-15 1994-09-16 Method for forming via flag of semiconductor device
GB9425300A GB2296128B (en) 1993-09-15 1994-12-19 Method of forming a via plug in a semiconductor device and a semiconductor device using its method
US08/734,784 USRE36475E (en) 1993-09-15 1996-10-15 Method of forming a via plug in a semiconductor device
HK98110979A HK1010423A1 (en) 1993-09-15 1998-09-25 Method of forming a via plug in a semiconductor device and a semiconductor device using its method
US09/293,207 USRE38383E1 (en) 1993-09-15 1999-04-16 Method for forming a via plug in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930018525A KR100188645B1 (en) 1993-09-15 1993-09-15 Via plug forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950009924A true KR950009924A (en) 1995-04-26
KR100188645B1 KR100188645B1 (en) 1999-06-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930018525A KR100188645B1 (en) 1993-09-15 1993-09-15 Via plug forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100188645B1 (en)

Also Published As

Publication number Publication date
KR100188645B1 (en) 1999-06-01

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