KR100188645B1 - Via plug forming method of semiconductor device - Google Patents

Via plug forming method of semiconductor device Download PDF

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Publication number
KR100188645B1
KR100188645B1 KR1019930018525A KR930018525A KR100188645B1 KR 100188645 B1 KR100188645 B1 KR 100188645B1 KR 1019930018525 A KR1019930018525 A KR 1019930018525A KR 930018525 A KR930018525 A KR 930018525A KR 100188645 B1 KR100188645 B1 KR 100188645B1
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South Korea
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forming
metal layer
tungsten
semiconductor device
via plug
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KR1019930018525A
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Korean (ko)
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KR950009924A (en
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최경근
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김영환
현대전자산업주식회사
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Priority to KR1019930018525A priority Critical patent/KR100188645B1/en
Priority to US08/305,306 priority patent/US5409861A/en
Priority to JP6221490A priority patent/JP2786115B2/en
Priority to GB9425300A priority patent/GB2296128B/en
Publication of KR950009924A publication Critical patent/KR950009924A/en
Priority to US08/734,784 priority patent/USRE36475E/en
Priority to HK98110979A priority patent/HK1010423A1/en
Priority to US09/293,207 priority patent/USRE38383E1/en
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Publication of KR100188645B1 publication Critical patent/KR100188645B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 비아 플러그(Via Plug)형성방법에 관하여 기술한 것으로 비아홀 저면을 이루는 금속층 계면에 텅스텐 핵(W-nuclei)을 형성한 후 습식식각방법으로 텅스텐 핵 사이로 노출된 금속층을 식각사여 다수의 식각홈을 형성하여 비아홀 저면의 표면적을 증가시키므로써 후공정인 비아 플러그 형성시 접촉면에서 접착력을 향상시키고 비아저항을 감소시킬 수 있는 반도체 소자의 비아 플러그 형성방법에 관하여 기술된다.The present invention relates to a method of forming a via plug of a semiconductor device, and after forming a tungsten nucleus (W-nuclei) at a metal layer interface forming a bottom of a via hole, the metal layer exposed between the tungsten nuclei is etched by a wet etching method. Disclosed is a method of forming a via plug of a semiconductor device capable of improving the adhesion at the contact surface and reducing the via resistance by forming a plurality of etching grooves to increase the surface area of the bottom surface of the via hole.

Description

반도체 소자의 비아 플러그 형성방법Via plug formation method of semiconductor device

제1a도 내지 제1e도는 본 발명에 의한 반도체 소자의 비아 플러그를 형성하는 단계를 도시한 단면도.1A to 1E are cross-sectional views showing steps of forming a via plug of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2: 제1금속층1: substrate 2: first metal layer

3 : 제1절연층 4 : 제2절연층3: first insulating layer 4: second insulating layer

5 : 제1절연층 6 : 비아홀5: first insulating layer 6: via hole

7 : 텅스텐 핵 8 : 식각홈7: tungsten core 8: etching groove

9 : 비아 플러그 10 : 제2금속층9: via plug 10: second metal layer

본 발명은 반도체 소자의 비아 플러그(Via Plug) 형성방법에 관한 것으로, 특히 비아홀 저면을 이루는 금속층 계면에 텅스텐 핵(W-nuclei)을 형성한 후 습식식각방법으로 텅스텐 핵 사이로 노출된 금속층을 식각하여 다수의 식각홈을 형성하여 비아홀 저면의 표면적을 증가시키므로써 후공정인 비아 플러그 형성시 접촉면에서 접착력을 향상시키고 비아 저항을 감소시킬 수 있는 반도체 소자의 비아 플러그 형성방법에 관한 것이다.The present invention relates to a method of forming a via plug of a semiconductor device. In particular, after forming a tungsten nucleus (W-nuclei) at a metal layer interface forming a bottom of a via hole, the metal layer exposed between the tungsten nuclei is etched by a wet etching method. By forming a plurality of etching grooves to increase the surface area of the bottom surface of the via hole, the present invention relates to a method of forming a via plug of a semiconductor device capable of improving adhesion at a contact surface and reducing via resistance when forming a via plug.

일반적으로, 반도체 소자가 고집적화 됨에 따라 비아홀의 크기는 작아지고 단차비는 증가하게 되며 비아홀의 깊이가 서로 다르게 형성되어 비아홀에 텅스텐등으로 비아 플러그를 형성하게 되는데, 비아 플러그를 형성할 때 균일하고 완벽한 비아 플러그 형성을 위해 전처리가 중요하다. 습식이나 식각 전처리시 불균일한 표면처리는 비아홀 저면을 이루는 금속층 계면에 자연 산화막, 폴리머등과 같은 이물질이 존재하게 되어 비아 저항의 증가를 초래할 뿐만 아니라 비아 플러그용 텅스텐이 불균일하게 성장되어 추후 공정에 악영향을 미쳐 반도체 소자의 특성저하를 유발하는 요인이 된다.In general, as semiconductor devices become highly integrated, the size of via holes decreases, the step ratio increases, and the depths of via holes are formed differently to form via plugs with tungsten or the like in the via holes. Pretreatment is important for via plug formation. Non-uniform surface treatment during wet or etching pretreatment results in the presence of foreign materials such as natural oxide film and polymer at the metal layer interface forming the bottom of the via-holes, resulting in increased via resistance, and uneven growth of via plug tungsten, which adversely affects subsequent processes. This causes the deterioration of the characteristics of the semiconductor device.

따라서 본 발명은 비아홀 저면을 이루는 금속층 계면에 형성되는 불소(F)계 이물질 및 자연 산화막과 같은 이물질은 제거하고, 접촉면의표면적을 증가시켜 비아 저항의 감소 및 접착력을 향상시킬 수 있도록 금속층계면에 텅스턴 핵을 형성한 후 습식식각방법으로 텅스텐 핵 사이로 노출된 금속층을 식각하여 이물질을 제거하는 동시에 접촉면의 표면적을 증가시키는 방법으로 후공정인 비아 플러그 형성시 비아 저항이 감소되고 접착력을 향상시킬 수 있는 반도체 소자의 비아 플러그 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention removes foreign substances such as fluorine (F) -based foreign substances and natural oxide film formed at the metal layer interface forming the bottom of the via hole, and increases the surface area of the contact surface to reduce via resistance and improve adhesion. After forming the stun nucleus, the metal layer exposed between the tungsten nucleus is etched by the wet etching method to remove foreign substances and at the same time increasing the surface area of the contact surface. It is an object of the present invention to provide a method for forming a via plug of a semiconductor device.

이러한 목적을 달성하기 위하여 본 발명의 비아 플러그 형성방법은 기판(1)에 제1금속층(2)을 형성한 후, 전체구조 상부에 제1, 2 및 3절연층(3, 4 및 5)을 순차적으로 적층하여 평탄화하는 단계와, 상기 단계로부터 콘택 마스크를 이용하여 상기 제1금속층(2) 상부의 소정부분이 노출될 때까지 상기 제 3, 2 및 1 절연층(5, 4 및 3)을 식각하여 비아홀(6)을 형성하는 단계와, 상기 단계로부터 상기 비아홀(6)을 건식 전처리한 후, 텅스텐 증착 반응기로 비아홀(6) 저면의 제1금속층(2) 계면부에 텅스텐을 증착하여 텅스텐 핵(7)을 형성하는 단계와, 상기 단계로부터 텅스텐과 식각 선택도가 다른 습식식각용액을 사용하여 상기 텅스텐 핵(7) 사이로 노출된 제1금속층(2)을 식각하여 제1금속층(2) 표면에 다수의 식각홈(8)을 형성하는 단계와, 상기 단계로부터 상기 비아홀(6)을 LPCVD 반응기로 비아 플러그(9)를 형성하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the via plug forming method of the present invention forms the first metal layer 2 on the substrate 1, and then forms the first, second and third insulating layers 3, 4, and 5 on the entire structure. Stacking and planarizing sequentially, and from the step, using the contact mask, the third, second and first insulating layers 5, 4 and 3 are exposed until a predetermined portion of the upper portion of the first metal layer 2 is exposed. Etching to form the via holes 6, dry pre-treating the via holes 6 from the step, and depositing tungsten at the interface of the first metal layer 2 at the bottom of the via holes 6 with a tungsten deposition reactor. Forming a nucleus (7), and etching the first metal layer (2) exposed between the tungsten nuclei (7) by using a wet etching solution having a different etching selectivity from tungsten. Forming a plurality of etching grooves (8) in the surface, and from the step the via holes (6) Characterized by comprising the LPCVD reactor at a step of forming a via plug (9).

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1a도 내지 제1e도는 본 발명에 의한 반도체 소자의 비아 플러그를 형성하는 단계를 도시한 단면도로서, 제1a도는 기판(1)에 제1금속층(2)을 서로 이격되게 형성한 후, 전체구조상부에 제1절연층(3), 제2절연층(4) 및 제3절연층(5)을 순차적으로 적층하여 평탄화한 상태를 도시한 것이다.1A to 1E are cross-sectional views illustrating a step of forming a via plug of a semiconductor device according to the present invention. FIG. 1A is a diagram showing an overall structure after forming a first metal layer 2 spaced apart from each other on a substrate 1. The first insulating layer 3, the second insulating layer 4, and the third insulating layer 5 are sequentially stacked and planarized thereon.

제1b도는 상기 제1금속층(2)에 후공정에서 형성될 때 제2금속층을 연결하기 위하여 콘택 마스크를 사용해 제1금속층(2)상의 소정부분의 제3절연층(5), 제2절연층(4) 및 제1절연층(3)을 순차적으로 습식 및 건식식각으로 식각하여 단차가 다른 비아홀(6)을 형성한 상태를 도시한 것이다.FIG. 1B illustrates a third insulating layer 5 and a second insulating layer of a predetermined portion on the first metal layer 2 using a contact mask to connect the second metal layer when the first metal layer 2 is formed in a later process. (4) and the first insulating layer 3 are sequentially etched by wet and dry etching to form via holes 6 having different steps.

제1c도는 상기 형성된 비아홀(6)을 RIF(Reactive Ion Etcher) 반응기에서 1분정도 건식 전처리(NF3, SF6, Ar 스퍼터등)한 후, 텅스텐 증착 반응기에서 1분정도 텅스텐을 증착하여 비아홀(6) 저면을 이루는 제1금속층(2) 계면에 텅스텐 핵(7)을 500∼1000Å정도의 크기로 형성한 상태를 도시한 것이다.FIG. 1c is a 1 minute dry pretreatment (NF 3 , SF 6 , Ar sputter, etc.) of the formed via hole 6 in a reactive ion reactor (RIF) reactor, followed by depositing tungsten for 1 minute in a tungsten deposition reactor. 6) The state in which the tungsten nucleus 7 is formed to a size of about 500 to 1000 mm 3 at the interface of the first metal layer 2 forming the bottom surface.

상기 건식 전처리시 제1금속층(2) 계면에 불소(F)계 화합물이나 이물질 및 자연산화막등이 발생되어 후공정에 악영향을 초래한다.In the dry pretreatment, a fluorine (F) -based compound, a foreign substance, and a natural oxide film are generated at the interface of the first metal layer 2, thereby adversely affecting the post-process.

제1d도는 상기 제1c도의 구조하에서 텅스텐과 식각 선택도가 다른 습식식각용액 예를들어, BOD(Buffered Oxide Etchant)를 사용해 텅스텐 핵(7)은 식각하지 않고 부분적으로 노출된 제1금속층(2)을 식각하여 제1금속층(2) 표면에 다수의 식각홈(8)으 형성한 상태를 도시한 것이다.FIG. 1D illustrates a wet etching solution having a different etching selectivity from tungsten under the structure of FIG. 1C. For example, a first metal layer 2 partially exposed without etching the tungsten nucleus 7 using a buffered oxide etchant (BOD). 2 by etching to form a plurality of etching grooves (8) on the surface of the first metal layer (2).

상기 습식식각공정으로 부분적으로 노출된 제1금속층(2) 표면에 식각홈(8)을 형성하므로써 접촉면적이 증가될 뿐만 아니라 제1금속층(2) 계면에 형성된 불소계 화합물이나 이물질 및 자연산화막등의 제거효과도 얻을 수 있어 결국 후공정인 비아 플러그 형성시 비아 저항을 감소시키고 접착력을 향상시킬 수 있다.By forming the etching groove 8 on the surface of the first metal layer 2 partially exposed by the wet etching process, the contact area is increased, and the fluorine-based compound, foreign matter, and natural oxide film formed on the interface of the first metal layer 2 are increased. The removal effect can also be obtained, which in turn can reduce via resistance and improve adhesion during via plug formation.

제1e도는 상기 제1d도의 구조하에서 상기 비아홀(6)을 LPCVD반응기로 비아 플러그(9)를 형성하고, 상기 비아 플러그(9)에 접속되도록 제2금속층(10)을 형성한 상태를 도시한 것이다.FIG. 1E illustrates a state in which the via hole 6 is formed by the LPCVD reactor using the LPCVD reactor under the structure of FIG. 1D, and the second metal layer 10 is formed to be connected to the via plug 9. .

상술한 바와 같이 본 발명은 비아홀에 텅스텐 핵을 형성한 후 습식식각 방법으로 텅스텐 핵 사이로 노출된 하부 금속층에 식각홈을 형성하므로써 접촉면적을 증가시킬 뿐만 아니라 비아 저항의 증가를 초래하는 이물질등도 제거하여 비아 저항을 감소시키고 접착력을 향상시켜 반도체 소자의 특성을 향상시킨다.As described above, the present invention forms an etching groove in the lower metal layer exposed between the tungsten nuclei by a wet etching method after forming the tungsten nucleus in the via hole, thereby increasing the contact area as well as removing foreign matters that increase the via resistance. Thereby reducing via resistance and improving adhesion to improve semiconductor device characteristics.

Claims (2)

반도체 소자의 비아 플러그 형성방법에 있어서, 기판(1)에 제1금속층(2)을 형성한 후, 전체구조 상부에 제1, 2 및 절연층(3, 4 및 5)을 순차적으로 적층하여 평탄화하는 단계와, 상기 단계로부터 콘택 마스크를 이용하여 상기 제1금속층(2) 상부의 소정부분이 노출될 때까지 상기 제3, 2 및 1절연층(5, 4 및 3)을 식각하여 비아홀(6)을 형성하는 단계와, 상기 단계로부터 상기 비아홀(6)을 건식 전처리한 후, 텅스텐 증착반응기로 비아홀(6) 저면의 제1금속층(2) 계면부에 텅스텐을 증착하여 텅스텐 핵(7)을 형성하는 단계와, 상기 단계로부터 텅스텐과 식각 선택도가 다른 습식식각용액을 사용하여 상기 텅스텐 핵(7) 사이로 노출된 제1금속층(2)을 식각하여 제1금속층(2) 표면에 다수의 식각홈(8)을 형성하는 단계와, 상기 단계로부터 상기 비아홀(6)을 LPCVD 반응기로 비아 플러그(9)를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 비아 플러그 형성방법.In the method for forming a via plug of a semiconductor device, after the first metal layer 2 is formed on the substrate 1, the first, second and insulating layers 3, 4, and 5 are sequentially stacked on the entire structure to be planarized. And etching the third, second, and first insulating layers 5, 4, and 3 until the predetermined portion of the upper portion of the first metal layer 2 is exposed by using a contact mask from the step. ) And dry pretreatment of the via hole (6) from the step, and depositing tungsten at the interface of the first metal layer (2) at the bottom of the via hole (6) with a tungsten deposition reactor to form a tungsten nucleus (7). Forming a plurality of etchings on the surface of the first metal layer 2 by etching the first metal layer 2 exposed between the tungsten nuclei 7 using a wet etching solution having a different etching selectivity from tungsten. Forming a groove (8), from which the via hole (6) can be Via plug forming a semiconductor device characterized in that comprising the step of forming a lug (9). 상기 텅스텐 핵(7)은 텅스텐 증착 반응기로 핵 하나 하나의 크기가 500∼1000Å 정도가 되록 증착하는 것을 특징으로 하는 반도체 소자의 비아 플러그 형성방법.The tungsten nucleus (7) is a tungsten deposition reactor is a method for forming a via plug of a semiconductor device, characterized in that the deposition of each nucleus to the size of 500 ~ 1000Å.
KR1019930018525A 1993-09-15 1993-09-15 Via plug forming method of semiconductor device KR100188645B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019930018525A KR100188645B1 (en) 1993-09-15 1993-09-15 Via plug forming method of semiconductor device
US08/305,306 US5409861A (en) 1993-09-15 1994-09-15 Method of forming a via plug in a semiconductor device
JP6221490A JP2786115B2 (en) 1993-09-15 1994-09-16 Method for forming via flag of semiconductor device
GB9425300A GB2296128B (en) 1993-09-15 1994-12-19 Method of forming a via plug in a semiconductor device and a semiconductor device using its method
US08/734,784 USRE36475E (en) 1993-09-15 1996-10-15 Method of forming a via plug in a semiconductor device
HK98110979A HK1010423A1 (en) 1993-09-15 1998-09-25 Method of forming a via plug in a semiconductor device and a semiconductor device using its method
US09/293,207 USRE38383E1 (en) 1993-09-15 1999-04-16 Method for forming a via plug in a semiconductor device

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KR1019930018525A KR100188645B1 (en) 1993-09-15 1993-09-15 Via plug forming method of semiconductor device

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KR950009924A KR950009924A (en) 1995-04-26
KR100188645B1 true KR100188645B1 (en) 1999-06-01

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