KR940002955A - Plug formation method in semiconductor wiring process - Google Patents

Plug formation method in semiconductor wiring process Download PDF

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Publication number
KR940002955A
KR940002955A KR1019920012910A KR920012910A KR940002955A KR 940002955 A KR940002955 A KR 940002955A KR 1019920012910 A KR1019920012910 A KR 1019920012910A KR 920012910 A KR920012910 A KR 920012910A KR 940002955 A KR940002955 A KR 940002955A
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South Korea
Prior art keywords
barrier metal
contact hole
tungsten
depositing
plug
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KR1019920012910A
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Korean (ko)
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KR950014270B1 (en
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라관구
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문정환
금성일렉트론 주식회사
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Priority to KR1019920012910A priority Critical patent/KR950014270B1/en
Publication of KR940002955A publication Critical patent/KR940002955A/en
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Publication of KR950014270B1 publication Critical patent/KR950014270B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 배선공정에서의 플러그형성방법으로서, (1)반도체기판(30)상에 배선공정을 위한 절연층(32)을 데포지션한후, 배선접속을 만들고자하는 부분에 콘택홀을 형성하고, 그 위에 배리어메탈을 충분히 두껍게 증착하는 단계, (2)이 베리어메탈을 RF 에치를 실시하여 웨이퍼 표면의 배리어메탈을 제거하고 배리어메탈을 콘택홀 내에만 남겨서 콘택홀입구부분이 경사진 배리어메탈콘택부를 형성하는 단계, (3)웨이퍼상에 W을 두껍게 데포지션하여 콘택홀 부분에 W이 완전히 채워질 수 있도록 한다음, 텅스텐을 식각하여 콘택홀 부분의 텅스텐만 남기고 그 이외의 텅스텐을 제거하는 단계, (4)웨이퍼위에 배선용 메탈을 증착시켜 포토/에치공정으로 배선을 형성하는 단계로 이루어지는 반도체 배선공정에서의 플러그형성방법이다.The present invention provides a method of forming a plug in a semiconductor wiring process, comprising (1) depositing an insulating layer 32 for a wiring process on a semiconductor substrate 30, and then forming contact holes in a portion to make a wiring connection. And depositing a barrier metal thickly thereon, (2) RF etching the barrier metal to remove the barrier metal on the wafer surface and leaving the barrier metal only in the contact hole so that the contact hole inlet is inclined. Forming a portion, (3) thickly depositing W on the wafer so that the W can be completely filled in the contact hole portion, and then etching tungsten, leaving only the tungsten in the contact hole portion and removing other tungsten, (4) A plug formation method in a semiconductor wiring process comprising the step of depositing a wiring metal on a wafer to form wiring in a photo / etch process.

특히 배리어메탈은 리프렉토리 메탈을사용하여 두께 150옹스트롬 이상이 되게 증착하는 것이 좋고, 텅스텐의 식각은 습식식각으로 식각용액은 H2O2를 사용하는 것이 좋다. 그리고, 텅스텐의 데포지션 방법은 CVD 증착방법을 사용하고, RF 에치는 베리어메탈을 증착하는 증착로에서 바로 연속적으로, 증착로의 진공상태를 그대로 유지하면서 웨이퍼에 고주파전압을 가하면서 아르곤 프라즈마로 에치한다.In particular, the barrier metal is preferably deposited to have a thickness of 150 angstroms or more using a directory metal, and the etching of tungsten is preferably wet etching and the etching solution is preferably H 2 O 2 . In addition, the deposition method of tungsten uses a CVD deposition method, and the RF etch is continuously performed in the deposition furnace for depositing the barrier metal, and etched with argon plasma while applying a high frequency voltage to the wafer while maintaining the vacuum state of the deposition furnace. do.

Description

반도체 배선공정에서의 플러그(plug)형성 방법Plug formation method in semiconductor wiring process

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 공정을 설명하기 위한 도면.2 is a view for explaining the process of the present invention.

Claims (7)

반도체 배선공정에서의 플러그형성방법에 있어서, (1) 반도체기판(30)상에 배선공정을 위한 절연층(32)을 데포지션한후, 배선접속을 만들고자하는 부분에 콘택홀을 형성하고, 그 위에 배리어메탈을 충분히 두껍게 증착하는 단계, (2) 이 베리어메탈을 RF에치를 실시하여 웨이퍼 표면의 배리어메탈을 제거하고 배리어메탈을 콘택홀 내에만 남겨서 콘택홀입구부분이 경사진 배리어메탈콘택부를 형성하는 단계, (3) 웨이퍼 상에 W을 두껍게 데포지션하여 콘택홀 부분에 W이 완전히 채워질 수 있도록 한 다음, 텅스텐을 식각하여 콘택홀 부분의 텅스텐만 남기고 그 이외의 텅스텐을 제거하는 단계, (4) 웨이퍼위에 배선용 메탈을 증착시켜 포토/에치공정으로 배선을 형성하는 단계로 이루어지는 반도체 배선공정에서의 플러그형성방법.In the method for forming a plug in a semiconductor wiring process, (1) after depositing an insulating layer 32 for a wiring process on a semiconductor substrate 30, a contact hole is formed in a portion where a wiring connection is to be made. (2) depositing barrier metal on the barrier layer sufficiently (2) RF-etching the barrier metal to remove the barrier metal on the wafer surface and leaving the barrier metal only in the contact hole to form a barrier metal contact portion having an inclined contact hole inlet. (3) thickly depositing W on the wafer so that the W can be completely filled in the contact hole portion, and then etching tungsten, leaving only the tungsten in the contact hole portion and removing other tungsten, (4 A method of forming a plug in a semiconductor wiring process, comprising: forming a wiring by a photo / etch process by depositing a wiring metal on a wafer. 제1항에 있어서, 제(1)단계에서 배리어메탈을 리프렉토리 메탈을 사용하여 두께 150옹스트롬 이상이 되게 증착하는 것이 특징인 반도체 배선공정에서의 플러그형성방법.2. The method for forming a plug in a semiconductor wiring process according to claim 1, wherein in step (1), the barrier metal is deposited to have a thickness of 150 angstroms or more using a directory metal. 제1항에 있어서, 제(3)단계에서 텅스텐의 식각은 습식식각으로 하는 것이 특징인 반도체 배선공정에서의 플러그형성방법.The method of claim 1, wherein the etching of tungsten in the step (3) is a wet etching. 제3항에 있어서, 제(3)단계에서 팅스텐을 식각하는 습식 식각용액은 H202를 사용하는 것이 특징인 반도체 배선공정에서의 플러그형성방법.The method of claim 3, wherein the wet etching solution for etching the tincture in the step (3) uses H 2 O 2 . 제1항에 있어서, 제(3)단계에서 텅스텐의 데포지션 방법은 CVD 증착방법을 사용하는 것이 특징인 반도체배선공정에서의 플러그형성방법 .The method for forming a plug in a semiconductor wiring process according to claim 1, wherein the deposition method of tungsten in the step (3) uses a CVD deposition method. 제1항에 있어서, 제(2)단계에서 RF에치는 베리어메탈을 증착하는 증착로에서 바로 연속적으로, 증착로의 진공상태를 그대로 유지하면서 웨이퍼에 고주파전압을 가하면서 아르곤 플라즈마로 에치하는 것 이 특징인 반도체 배선공정에서의 플러그형성방법.The method of claim 1, wherein the RF etch in step (2) is etched with argon plasma while applying a high frequency voltage to the wafer while maintaining the vacuum state of the deposition furnace immediately in a deposition furnace for depositing barrier metal. The plug formation method in the semiconductor wiring process characterized by the above-mentioned. 반도체의 소정부분과 콘택홀을 통하여 전기배선과를 연결하는 플러그로서, 콘택흘내에 형성된 콘택홀입구 부분이 경사지게 식각된 배리어메탈콘택부와, 상기 배리어메탈콘택부위에 콘택흘을 완전히 채운 텅스텐으로 이루어지는 것이 특징인 반도체 배선공정에서의 콘택홀플러그.A plug that connects a predetermined portion of a semiconductor to an electrical wiring through a contact hole, comprising a barrier metal contact portion in which a contact hole inlet portion formed in a contact groove is etched obliquely, and tungsten completely filled with a contact hole on the barrier metal contact portion. A contact hole plug in a semiconductor wiring process characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920012910A 1992-07-20 1992-07-20 Plug forming method of semiconductor device KR950014270B1 (en)

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Application Number Priority Date Filing Date Title
KR1019920012910A KR950014270B1 (en) 1992-07-20 1992-07-20 Plug forming method of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019920012910A KR950014270B1 (en) 1992-07-20 1992-07-20 Plug forming method of semiconductor device

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KR940002955A true KR940002955A (en) 1994-02-19
KR950014270B1 KR950014270B1 (en) 1995-11-24

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