KR0167251B1 - Method of making the interconnection layer in a semiconducor device - Google Patents
Method of making the interconnection layer in a semiconducor device Download PDFInfo
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- KR0167251B1 KR0167251B1 KR1019950024922A KR19950024922A KR0167251B1 KR 0167251 B1 KR0167251 B1 KR 0167251B1 KR 1019950024922 A KR1019950024922 A KR 1019950024922A KR 19950024922 A KR19950024922 A KR 19950024922A KR 0167251 B1 KR0167251 B1 KR 0167251B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
Abstract
본 발명은 반도체 소자의 배선구조 및 그 제조방법에 관한 것으로, 단차를 갖는 기판 위의 절연막 상에 토폴로지가 낮은 부분과 토폴로지가 높은 부분에서 서로 다른 두께를 가지도록 배선 패턴을 형성하므로써, 배선 패턴의 평탄도 향상으로 인해 단차가 개선된 평탄한 상태에서 사진식각공정을 적용할 수 있게 되어 정밀하고 정확한 패턴을 형성할 수 있을 뿐 아니라 부분적으로 배선 패턴의 두께가 증가한 부분이 존재하므로 전기저항을 감소시킬 수 있는 장점을 가지게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor element and a method of manufacturing the same. The improved flatness allows the photolithography process to be applied in a flat state where the step height is improved, thereby not only forming a precise and accurate pattern but also partially increasing the thickness of the wiring pattern, thereby reducing electrical resistance. You have the advantage.
Description
제1(a)도 내지 제1(f)도는 본 발명의 제 1 실시예에 따른 반도체 소자의 배선 형성방법을 도시한 공정수순도.1 (a) to 1 (f) are process flowcharts showing a wiring forming method of a semiconductor device according to a first embodiment of the present invention.
제2(a)도 내지 제2(g)도는 본 발명의 제2 실시예에 따른 반도체 소자의 배선 형성방법을 도시한 공정수순도.2 (a) to 2 (g) are process flowcharts showing the wiring forming method of the semiconductor device according to the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 도전성 영역1 semiconductor substrate 2 conductive region
3 : 전도선 4 : 절연막3: conductive wire 4: insulating film
5 : 단차 6 : 접속구멍5 step 6: connection hole
7 : 하부 도전성막 8 : 상부 도전성막7: lower conductive film 8: upper conductive film
9 : 감광막 패턴 10 : 배선 패턴9: photosensitive film pattern 10: wiring pattern
본 발명은 반도체 소자의 배선구조 및 그 제조방법에 관한 것으로, 특히 고단차를 갖는 반도체 기판 위의 배선 공정에 있어서의 평탄성을 개선한 반도체 배선구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor wiring structure and a method for manufacturing the same in a wiring process on a semiconductor substrate having a high step.
반도체 접적회로의 고집적화가 진행됨에 따라 최소 설계 선폭이 감소하게 되므로 토폴로지(topology)가 있는 기판을 사용하여 사진식각공정 진행시 촛점 심도(depth of focus) 및 해상도(resolution)의 한계에 근접하게 되어, 단차부를 중심으로 패턴 왜곡이나 과노광(over-exposure) 또는 노광 부족(under-exposure) 등에 기인한 오픈(open) 및 쇼트(short) 등과 같은 소자의 불량 현상이 발생하게 된다.As the integration density of semiconductor integrated circuits progresses, the minimum design line width decreases, so that the depth of focus and resolution are approached during the photolithography process using a substrate with topology. Defects of the device such as open and short due to pattern distortion, over-exposure or under-exposure, etc., occur around the stepped portion.
따라서, 단차를 감소시키고 기판의 토폴로지를 완화시키기 위하여 유동성이 높은 SOG(spin on glass) 등의 도포성 절연막이나 표면 유동특성이 우수한 O3-TEOS 등의 증착 절연막을 적용하는 연구와, 절연막을 형성한 후 화학적물리적연마(chemical mechanical polishing:이하, CMP라 한다)법을 적용하는 연구가 활발하게 진행되고 있다.Therefore, in order to reduce the step height and to reduce the topology of the substrate, a study is applied to a coating insulating film of high flowability, such as spin on glass (SOG), or a deposition insulating film of O3-TEOS, which has excellent surface flow characteristics. Afterwards, researches applying chemical mechanical polishing (hereinafter referred to as CMP) method are actively conducted.
그러나 위에서 예시된 이들 공정들 또한 단차와 기판 토폴로지를 감소시키기 위해서는 유동성이 우수한 절연막을 포함하여 다층 구조의 절역만을 적용해야 하므로 공정이 추가되는 단점을 가지게 되며, 또한 CMP를 적용할 경우에는 슬러리(slurry) 등에 의한 화학적 오염과 연마 단계에서 기계적 손상(mechnical damage)이 발생되는 등의 단점을 가지게 된다.However, these processes exemplified above also have the disadvantage of adding a process because only the multi-layered cutout must be applied to reduce the step height and the substrate topology, and when CMP is applied, a slurry Chemical contamination and mechanical damage in the polishing step.
이에 본 발명은 상기와 같은 단점을 해결하기 위하여 이루어진 것으로, 배선 형성시 도전성막의 두께를 선택적으로 조절하므로써 단차를 개선할 수 있게 되어 소자의 평탄성을 향상시킬 수 있도록 한 반도체 소자의 배선구조 및 그 제조방법을 제공함에 목적이 있다.Accordingly, the present invention has been made to solve the above disadvantages, and by adjusting the thickness of the conductive film selectively during wiring formation, the step structure can be improved to improve the flatness of the device and its structure It is an object to provide a manufacturing method.
상기와 같은 목적을 달성하기 위한 본 발명의 제1 및 제2 실시예에 따른 반도체 소자의 배선구조는 임의의 도전성 영역을 포함하는 반도체 기판과; 전도선을 포함하며, 단차를 가지고 상기 기판 상에 형성된 절연막 및; 토플로지가 낮은 부분과 토폴로지가 높은 부분에서 서로 다른 두께를 가지도록 상기 절연막 상에 형성된 평탄화된 구조의 배션 패턴을 구비하여 이루어진 것을 특징으로 한다.The wiring structure of the semiconductor device according to the first and second embodiments of the present invention for achieving the above object is a semiconductor substrate including any conductive region; An insulating film including a conductive line and formed on the substrate with a step difference; And a bastion pattern having a flattened structure formed on the insulating layer to have different thicknesses in a portion having a low topography and a portion having a high topology.
한편, 상기와 같은 목적을 달성하기 위한 본 발명의 제1 및 제2 실시예에 따른 반도체 소자의 배선 제조방법은 단차를 갖는 기판 위의 절연막 상에 토폴로지가 낮은 부분과 토폴로지가 높은 부분에서 서로 다른 두께를 가지도록 도전성막의 배선 패턴을 형성하는 것을 특징으로 한다.On the other hand, the wiring manufacturing method of the semiconductor device according to the first and second embodiments of the present invention for achieving the above object is different in the low topology and high topology on the insulating film on the substrate having a step A wiring pattern of the conductive film is formed to have a thickness.
상기와 같은 목적을 달성하기 위한 본 발명의 제1 실시예에 따른 반도체 소자의 배선 제조방법은 임의의 도전성 영역이 형성된 반도체 기판 상에 전도선을 포함하는 절연막을 형성하는 공정과; 상기 전도선 및 도전성 영역의 표면이 노출되도록 접속 구멍을 형성하는 공정과; 상기 접속구멍을 포함한 절연막 상에 하부 도전성막 및 상부 도전성막을 형성하는 공정 및; 높은 토폴로지 부분의 상부 도전성막을 선택 식각하는 공정을 구비하여 이루어진 것을 특징으로 한다.According to a first aspect of the present invention, there is provided a method of manufacturing a wiring of a semiconductor device, the method including: forming an insulating film including conductive lines on a semiconductor substrate on which an arbitrary conductive region is formed; Forming a connection hole so that the surfaces of the conductive line and the conductive region are exposed; Forming a lower conductive film and an upper conductive film on the insulating film including the connection hole; And a step of selectively etching the upper conductive film of the high topology portion.
상기와 같은 목적을 달성하기 위한 본 발명의 제2 실시예에 따른 반도체 소자의 배선 제조방법은 임의의 도전성 영역이 형성된 반도체 기판 상에 전도선을 포함하는 절연막을 형성하는 공정과; 상기 전도선 및 도전성 영역의 표면이 노출되도록 접속 구멍을 형성하는 공정과; 상기 접속구멍을 포함한 절연막 상에 하부 도전성막을 형성하는 공정과; 상기 하부 도전성막을 선택 식각하여 평탄화하는 공정과; 상부 도전성막을 형성하는 공정 및; 도전성막 패턴을 형성하는 공정을 구비하여 이루어진 것을 특징으로 한다.According to a second aspect of the present invention, there is provided a method of manufacturing a wiring of a semiconductor device, the method including: forming an insulating film including conductive lines on a semiconductor substrate on which an arbitrary conductive region is formed; Forming a connection hole so that the surfaces of the conductive line and the conductive region are exposed; Forming a lower conductive film on the insulating film including the connection hole; Selectively etching and etching the lower conductive film; Forming an upper conductive film; It is characterized by comprising a step of forming a conductive film pattern.
상기 구성 및 공정 결과, 소자의 배선 신뢰성을 향상시킬 수 있게 된다.As a result of the above configuration and process, it is possible to improve the wiring reliability of the device.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
본 발명은 단차를 갖는 반도체 기판 위에 배선을 형성함에 있어서, 낮은 토폴로지 부분의 배선 두께를 높은 토폴로지 부분의 배선 두께보다 상대적으로 두껍게 형성하므로써 단차를 감소시킬 수 있도록 한 구조를 가지도록 소자를 제조토록 한 것으로, 이를 제1도 및 제2도에 도시된 실시예를 참조하여 구체적으로 살펴보면 다음과 같다.According to the present invention, in forming a wiring on a semiconductor substrate having a step, the device is manufactured to have a structure such that the step thickness can be reduced by forming the wiring thickness of the low topology portion relatively thicker than the wiring thickness of the high topology portion. This will be described in detail with reference to the embodiments shown in FIGS. 1 and 2 as follows.
먼저, 제1 실시예로서 제1(a)도 내지 제1(f)도에 도시된 공정수순도를 살펴본다.First, a process flow chart shown in FIGS. 1 (a) to 1 (f) will be described as a first embodiment.
우선, 제1(a)도에 도시된 바와 같이 임의의 도전성 영역(2)이 형성된 반도체 기판(1) 상에 전도선(3)을 포함하는 기저절연막(4)을 형성한 후, 상기 도전성 영역(2)과 전도선(3)을 상층 전도선에 연결하기 위하여 도전성 영역(2) 및 전도선(3)의 표면 일부가 드러나도록 접속구멍(contact hole)을 기저절연막(4)에 형성하여 제1(b)도에 도시된 바와 같은 패턴을 형성한다. 이때, 발생되는 기판의 단차(5)를 T라 한다.First, as shown in FIG. 1 (a), a base insulating film 4 including a conductive line 3 is formed on a semiconductor substrate 1 on which an arbitrary conductive region 2 is formed. In order to connect (2) and the conductive line (3) to the upper conductive line, a contact hole is formed in the base insulating film (4) so that a part of the surface of the conductive region (2) and the conductive line (3) is exposed. A pattern as shown in Fig. 1 (b) is formed. At this time, the step 5 of the generated substrate is referred to as T.
그후, 제1(c)도에 도시된 바와 같이 단차(5)부에도 증착 두께가 현격히 감소되지 않도록 화학기상증착(chemical vapour deposition:이하, CVD라 한다)법 등을 이용하여 하부 도전성막(7)을 등각(conformal)으로 증착한다.Subsequently, as shown in FIG. 1 (c), the lower conductive film 7 may be formed by chemical vapor deposition (hereinafter, referred to as CVD) so as not to significantly reduce the deposition thickness on the step 5. ) Is deposited conformally.
이때, 상기 하부 도전성막은, Al, Cu, W등의 금속성 물질이나 TiSi2, WSi2등의 금속화합물, 또는 도핑된 실리콘막 등의 반도체 물질로 형성된다.In this case, the lower conductive film is formed of a metallic material such as Al, Cu, W, a metal compound such as TiSi 2 , WSi 2 , or a semiconductor material such as a doped silicon film.
그 다음, 제1(d)도에 도시된 바와 같이 상기 하부 도전성막(7) 상에 기존의 스퍼터링법 등으로 알루미늄 등의 상부 도전성막(8)을 형성한다. 이 도전성막(8)의 두께가 바로 배선의 평탄도를 개선하는 정도를 결정하게 된다.Then, as shown in FIG. 1 (d), an upper conductive film 8 such as aluminum is formed on the lower conductive film 7 by a conventional sputtering method or the like. The thickness of the conductive film 8 immediately determines the extent to which the flatness of the wiring is improved.
이어서, 제1(e)도에 도시된 바와 같이 상부 도전성막(8) 상에 감광막을 증착한 후, 낮은 토폴로지를 갖는 부위의 상부 도전성막(8) 상에만 선택적으로 남도록 감광막 패턴(9)을 형성하고, 이를 마스크로 높은 토폴로지를 갖는 부위의 상부 도전성막(8)을 Cl2등의 가스를 이용한 건식식각법이나 HNO3등의 산성용액을 포함하는 습식식각법을 적용하여 제거한다.Subsequently, after the photoresist film is deposited on the upper conductive film 8 as shown in FIG. 1 (e), the photoresist pattern 9 is selectively removed so as to remain selectively only on the upper conductive film 8 in the region having the low topology. The upper conductive film 8 having a high topology is removed using a dry etching method using a gas such as Cl 2 or a wet etching method including an acid solution such as HNO 3 as a mask.
결과적으로, 낮은 토폴로지를 갖는 부분이 상부 도전성막(8)의 두께만큼 상승하여 단차가 개선되는 효과를 나타내게 된다.As a result, the portion having the low topology rises by the thickness of the upper conductive film 8, thereby exhibiting the effect of improving the level difference.
계속해서 제1(f)도에 도시된 바와 같이 감광막 패턴(9)을 제거하여 하부 도전성막 및 상부 도전성막으로 이루어진 배선 패턴(10)을 형성하므로써 본 공정을 완료한다.Subsequently, as shown in FIG. 1 (f), the process is completed by removing the photosensitive film pattern 9 to form the wiring pattern 10 composed of the lower conductive film and the upper conductive film.
이때, 상기 배선 패턴(10)은 두께가 부분적으로 다르게 조절된 구조를 가지므로 단차(5)가 배선을 형성하기 전의 T에서 t로 감속하게 되어 배선의 평탄도가 개선되므로 후속 공정을 실시하는데 있어서 사진식각공정의 신뢰성을 향상시킬 수 있게 된다.At this time, since the wiring pattern 10 has a structure in which the thickness is partially differently controlled, the step 5 decelerates from T to t before forming the wiring, thereby improving the flatness of the wiring. The reliability of the photolithography process can be improved.
본 공정에 있어서의 평탄도의 개선은 상기 공정에서 알 수 있듯이 상부 도전성막(8)의 증착 두께와 산택마스크인 감광막 패턴(9)을 이용한 도전성막의 식각 정도에 따라 결정됨을 알 수 있다.It can be seen that the improvement of the flatness in this step is determined by the deposition thickness of the upper conductive film 8 and the etching degree of the conductive film using the photosensitive film pattern 9 which is a picking mask.
특히, 하부 도전성막(7)과 상부 도전성막(8) 물질로서 서로 식각특성이 다른 물질을 적용하면, 예컨대 하부 도전성막으로 W를, 상부 도전성막으로 Al을 적용하게 되면, Al막의 식각에 대하여 W막이 에치 스톱퍼(etch stopper)로서 작용하므로 식각량, 즉 평탄도의 조절이 더욱 용이하게 된다.In particular, when a material having different etching characteristics is applied as the material of the lower conductive film 7 and the upper conductive film 8, for example, W is applied to the lower conductive film and Al is applied to the upper conductive film. Since the W film acts as an etch stopper, the etching amount, that is, the flatness is more easily adjusted.
한편, 이를 다소 변형한 제2 실시예로서 제2(a)도 내지 제2(g)도에 도시된 공정수순도를 살펴보면 다음과 같다.On the other hand, as a second embodiment somewhat modified to look at the process flow chart shown in Figure 2 (a) to 2 (g) as follows.
상기 실시예에서 제2(a)도 및 제2(b)도에 도시된 공정까지는 제1 실시예의 제1(a)도 및 제1(b)도에 도시된 공정과 동일한 수순에 의해 제조되므로 여기서는 설명을 생략한다.In the above embodiment, the processes shown in FIGS. 2A and 2B are manufactured by the same procedures as those shown in FIGS. 1A and 1B of the first embodiment. The description is omitted here.
이후, 제2(c)도에 도시된 바와 같이 하부 도전성막(7)의 두께를 단차(5) T에 해당하는 두께로 형성하고, 제2(d)도에 도시된 바와 같이 상기 하부 도전성막(7)을 CMP법으로 에치-백하여 평탄화시킨 후, 제2(e)도에 도시된 바와 같이 기저 절연막(1)을 포함한 평탄화된 하부 도전성막(7) 상에 상부 도전성막(8)을 증착한다.Thereafter, as shown in FIG. 2 (c), the thickness of the lower conductive film 7 is formed to a thickness corresponding to the step 5 T, and as shown in FIG. 2 (d), the lower conductive film (7) is etched back by CMP to planarize, and then the upper conductive film 8 is deposited on the planarized lower conductive film 7 including the base insulating film 1 as shown in FIG. Deposit.
그 다음, 제2(f)도에 도시된 바와 같이 상기 상부 도전성막(8) 상에 감광막 패턴(9)을 형성하고, 이를 마스크로 상부 도전성막(8) 및 하부 도전성막(7)을 차례로 식각한 후 상기 감광막 패턴(9)을 제거하여 제2(g)도에 도시된 바와 같이 배선 패턴(10)을 형성하므로써 본 공정을 완료한다.Next, as shown in FIG. 2 (f), a photosensitive film pattern 9 is formed on the upper conductive film 8, and the upper conductive film 8 and the lower conductive film 7 are sequentially formed using the mask. After etching, the process is completed by removing the photoresist pattern 9 and forming the wiring pattern 10 as shown in FIG. 2 (g).
상술한 바와 같이 본 발명에 의하면, 배선 패턴의 평탄도 향상으로 인해 단차가 개선된 평탄한 상태에서 사진식각공정을 적용할 수 있게 되어 정밀하고 정확한 패턴을 형성할 수 있을 뿐 아니라 부분적으로 배선 패턴의 두께가 증가한 부분이 존재하므로 전기저항을 감소시킬 수 있는 장점을 가지게 된다.As described above, according to the present invention, it is possible to apply a photolithography process in a flat state in which the step is improved due to the improved flatness of the wiring pattern, thereby forming a precise and accurate pattern as well as the thickness of the wiring pattern partially. Since there is an increased portion has the advantage that can reduce the electrical resistance.
Claims (16)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950024922A KR0167251B1 (en) | 1995-08-12 | 1995-08-12 | Method of making the interconnection layer in a semiconducor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950024922A KR0167251B1 (en) | 1995-08-12 | 1995-08-12 | Method of making the interconnection layer in a semiconducor device |
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| Publication Number | Publication Date |
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| KR970013213A KR970013213A (en) | 1997-03-29 |
| KR0167251B1 true KR0167251B1 (en) | 1999-02-01 |
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| KR1019950024922A KR0167251B1 (en) | 1995-08-12 | 1995-08-12 | Method of making the interconnection layer in a semiconducor device |
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