KR970013213A - Wiring structure of semiconductor device and manufacturing method thereof - Google Patents

Wiring structure of semiconductor device and manufacturing method thereof Download PDF

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KR970013213A
KR970013213A KR1019950024922A KR19950024922A KR970013213A KR 970013213 A KR970013213 A KR 970013213A KR 1019950024922 A KR1019950024922 A KR 1019950024922A KR 19950024922 A KR19950024922 A KR 19950024922A KR 970013213 A KR970013213 A KR 970013213A
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conductive
conductive film
topology
film
forming
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KR0167251B1 (en
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전영권
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문정환
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 배선구조 및 그 제조방법에 관한 것으로, 단차를 갖는 기판 위의 절연막 상에 토폴로지가 낮은 부분과 토폴로지가 높은 부분에서 서로 다른 두께를 가지도록 배선 패턴을 형성하므로써, 배선 패턴의 평탄도 향상으로 인해 단차가 개선된 평탄한 상태에서 사진식각공정을 적용할 수 있게 되어 정밀하고 정확한 패턴을 형성할 수 있을 뿐 아니라 부분적으로 배선 패턴의 두께가 증가한 부분이 존재하므로 전기저항을 감소시킬 수 있는 장점을 가지게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor element and a method of manufacturing the same. The improved flatness allows the photolithography process to be applied in a flat state where the step height is improved, thereby not only forming a precise and accurate pattern but also partially increasing the thickness of the wiring pattern, thereby reducing electrical resistance. You have the advantage.

Description

반도체 소자의 배선구조 및 그 제조방법Wiring structure of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1(가)도 내지 제1(바)도는 본 발명의 제1실시예에 따른 반도체 소자의 배선 형성방법을 도시한 공정수순도1 (a) to 1 (bar) are process flowcharts showing a wiring forming method of a semiconductor device according to a first embodiment of the present invention.

Claims (16)

임의의 도전성 영역을 포함하는 반도체 기판과; 전도선을 포함하며, 단차를 가지고 상기 기판상에 형성된 절연막 및; 토폴로지가 낮은 부분과 토폴로지가 높은 부분에서 서로 다른 두께를 가지도록 상기 절연막 상에 형성된 평탄화된 구조의 배선 패턴을 구비하여 이루어진 것을 특징으로 하는 반도체 소자의 배선구조A semiconductor substrate comprising any conductive region; An insulating film including a conductive line and formed on the substrate with a step; A wiring structure of a semiconductor device, comprising a wiring pattern having a flattened structure formed on the insulating layer so as to have a different thickness in a portion having a low topology and a portion having a high topology. 제1항에 있어서, 상기 배선 패턴은 제1도전성막 및 제2도전성막이 연속 증착된 구조로 이루어진 것을 특징으로 하는 반도체 소자의 배선구조The semiconductor device wiring structure of claim 1, wherein the wiring pattern has a structure in which a first conductive film and a second conductive film are continuously deposited. 제2항에 있어서, 상기 제1도전성막과 제2도전성막은 서로 식각 선택성이 다른 물질로 이루어진 것을 특징으로 하는 반도체 소자의 배선구조The wiring structure of claim 2, wherein the first conductive film and the second conductive film are made of materials having different etching selectivities. 제1항에 있어서, 상기 배선 패턴은 토폴로지가 높은 부분에 대해 토폴로지가 낮은 부분이 상대적으로 더 두껍게 형성된 구조를 갖는 것을 특징으로 하는 반도체 소자의 배선구조The wiring structure of a semiconductor device according to claim 1, wherein the wiring pattern has a structure in which a portion having a low topology is relatively thicker than a portion having a high topology. 단차를 갖는 기판 위의 절연막 상에 토폴로지가 낮은 부분과 토폴로지가 높은 부분에서 서로 다른 두께를 가지도록 배선 패턴을 형성하는 것을 특징으로 하는 반도체 소자의 배선 제조방법A wiring manufacturing method of a semiconductor device, characterized in that the wiring pattern is formed on the insulating film on the substrate having a step so as to have a different thickness in a portion having a low topology and a portion having a high topology. 제5항에 있어서, 상기 배선 패턴은 토폴로지가 높은 부분에 대해 토폴로지가 낮은 부분이 상대적으로 더 두껍게 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법The method of claim 5, wherein the wiring pattern is formed to be relatively thicker in a portion having a higher topology than a portion having a high topology. 임의의 도전성 영역의 형성된 반도체 기판 상에 전도선을 포함하는 절연막을 형성하는 공정과; 상기 전도선 및 도전성 영역의 표면이 노출되도록 접속 구멍을 형성하는 공정과; 상기 접속구멍을 포함한 절연막 상에 하부 도전성막 및 상부 도전성막을 형성하는 공정 및; 높은 토폴로지 부분의 상부 도전성막을 선택 식각하는 공정을 구비하여 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법Forming an insulating film including conductive lines on the formed semiconductor substrate of any conductive region; Forming a connection hole so that the surfaces of the conductive line and the conductive region are exposed; Forming a lower conductive film and an upper conductive film on the insulating film including the connection hole; And a step of selectively etching the upper conductive film of the high topology portion, wherein the wiring manufacturing method of the semiconductor device is formed. 제7항에 있어서, 상기 하부 도전성막은 화학기상증착법에 의해 등각으로 증착되는 것을 특징으로 하는 반도체 소자의 배선 제조방법The method of claim 7, wherein the lower conductive film is deposited at a conformal rate by chemical vapor deposition. 제7항에 있어서, 상기 하부 도전성막은 AI, Cu, W 등의 금속성 물질이나 TiSi2, WSi2 등의 금속화합물, 또는 도핑된 실리콘막 등의 반도체 물질 중 선택된 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법The semiconductor device according to claim 7, wherein the lower conductive film is formed of any one selected from a metallic material such as AI, Cu, W, a metal compound such as TiSi2, WSi2, or a semiconductor material such as a doped silicon film. Wire manufacturing method 제7항 또는 제9항에 있어서, 상기 하부 및 상부 도전성막은 서로 식각 선택성이 다른 물질로 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법10. The method of claim 7 or 9, wherein the lower and upper conductive layers are formed of materials having different etching selectivities. 제7항에 있어서, 상기 높은 토폴로지 부분의 상부 도전성막을 선택 식각하는 공정은 토폴로지가 낮은 기판 위의 상부 도전성막 상에 감광막 패턴을 형성하는 공정과; 상기 감광막 패턴을 마스크로 상부 도전성막을 선택 식각하는 공정을 더 포함하여 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법The method of claim 7, wherein the selective etching of the upper conductive film of the high topology portion comprises: forming a photoresist pattern on the upper conductive film on the substrate having a low topology; And further etching the upper conductive film using the photosensitive film pattern as a mask. 임의의 도전성 영역이 형성된 반도체 기판 상에 전도선을 포함하는 절연막을 형성하는 공정과; 상기 전도선 및 도전성 영역의 표면이 노출되도록 접속 구멍을 형성하는 공정과; 상기 하부 도전성막을 선택 식각하여 평탄화하는 공정과; 상부 도전성막을 형성하는 공정 및; 도전성막 패턴을 형성하는 공정을 구비하여 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법Forming an insulating film including conductive lines on a semiconductor substrate on which any conductive region is formed; Forming a connection hole so that the surfaces of the conductive line and the conductive region are exposed; Selectively etching and etching the lower conductive film; Forming an upper conductive film; And a step of forming a conductive film pattern. 제12항에 있어서, 상기 하부 도전성막은 기판 위에 발생된 단차에 해당하는 두께로 형성하는 것을 특징으로 하는 반도체 소자의 배선 제조방법The method of claim 12, wherein the lower conductive layer is formed to a thickness corresponding to a step generated on a substrate. 제12항에 있어서, 상기 하부 도전성막은 화학적물리적연마법으로 에치-백하여 평탄화하는 것을 특징으로 하는 반도체 소자의 배선 제조방법The method of claim 12, wherein the lower conductive layer is etched back by a chemical physical polishing method to planarize the lower conductive layer. 제12항에 있어서, 상기 하부 도전성막은 AI, Cu, W 등의 금속성 물질이나 TiSi2, WSi2 등의 금속화합물, 또는 도핑된 실리콘막 등의 반도체 물질 중 선택된 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법The semiconductor device of claim 12, wherein the lower conductive layer is formed of any one selected from a metallic material such as AI, Cu, W, a metal compound such as TiSi 2, WSi 2, or a semiconductor material such as a doped silicon film. Wire manufacturing method 제12항 또는 제15항에 있어서, 상기 하부 및 상부 도전성막은 서로 식각 선택성이 다른 물질로 형성되는 것을 특징으로 하는 반도체 소자의 배선 제조방법The method of claim 12, wherein the lower and upper conductive layers are formed of materials having different etching selectivities.
KR1019950024922A 1995-08-12 1995-08-12 Method of making the interconnection layer in a semiconducor device KR0167251B1 (en)

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