KR950006994A - Via plug formation method of semiconductor device - Google Patents

Via plug formation method of semiconductor device Download PDF

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Publication number
KR950006994A
KR950006994A KR1019930016645A KR930016645A KR950006994A KR 950006994 A KR950006994 A KR 950006994A KR 1019930016645 A KR1019930016645 A KR 1019930016645A KR 930016645 A KR930016645 A KR 930016645A KR 950006994 A KR950006994 A KR 950006994A
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KR
South Korea
Prior art keywords
bonding layer
forming
via plug
semiconductor device
layer
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Application number
KR1019930016645A
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Korean (ko)
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KR960015498B1 (en
Inventor
최경근
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019930016645A priority Critical patent/KR960015498B1/en
Publication of KR950006994A publication Critical patent/KR950006994A/en
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Publication of KR960015498B1 publication Critical patent/KR960015498B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 비아 플러그(Via Plug) 형성방법을 기술한 것으로, 특히 비아 홀(Via Hole) 저면에만 접합층(Glue Layer)을 형성시켜 텅스텐(W)이 비아 홀 저면으로부터 성장되게 하므로써, 텅스텐의 조직이 조밀하게 되어 비아 플러그의 특성을 향상시킬 수 있는 반도체 소자의 비아 플러그 형성방법에 관하여 기술된다.The present invention describes a method of forming a via plug of a semiconductor device. In particular, by forming a bonding layer only on a bottom of a via hole, tungsten (W) is grown from a bottom of a via hole. A method of forming a via plug of a semiconductor device in which a structure of tungsten can be densified to improve the characteristics of the via plug is described.

Description

반도체 소자의 비아 플러그 형성방법Via plug formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4A도 내지 제4E도는 본 발명에 의한 반도체 소자의 비아 플러그를 형성하는 단계를 도시한 단면도.4A to 4E are cross-sectional views showing steps of forming a via plug of a semiconductor device according to the present invention.

Claims (2)

반도체 소자의 비아 플러그 형성방법에 있어서, 소정의 금속층과 콘택될 실리콘 기판 또는 금속층의 콘택기판(10)상에 제1접합층(11)을 얇게 형성하는 단계와, 상기 제1접합층(11) 상부에 산화막(12)을 두껍게 증착한 후, 상기 산화막(12) 상부에 제2접합층(13)을 얇게 형성하는 단계와, 상기 단계로부터 콘택 마스크를 이용하여 상기 제2접합층(13) 및 산화막(12)을 하부의 제1접합층(11)이 노출될 때까지 식각하여 비아 홀(14)을 형성하는 단계와, 상기 비아 홀(14) 및 제2접합층(13) 상부에 비아플러그용 텅스텐(15)을 증착하는 단계와, 상기 텅스텐(15)을 블랭켓 에치 백 공정으로 전면 식각하여 비아 홀(14)내에 비아 플러그(16)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 비아 플러그 형성방법.A method of forming a via plug of a semiconductor device, comprising: forming a thin first bonding layer 11 on a silicon substrate to be contacted with a predetermined metal layer or a contact substrate 10 of a metal layer, and forming the first bonding layer 11. After the oxide film 12 is thickly deposited on the upper portion, the second bonding layer 13 is thinly formed on the oxide film 12, and the second bonding layer 13 and the contact mask are formed using the contact mask. Etching the oxide film 12 until the lower first bonding layer 11 is exposed to form a via hole 14, and a via plug on the via hole 14 and the second bonding layer 13. Depositing tungsten (15) for etching and forming a via plug (16) in the via hole (14) by etching the entire surface of the tungsten (15) by a blanket etch back process. How to Form Via Plugs. 제1항에 있어서, 상기 제1접합층(11) 및 제2접합층(13)은 PVD반응기로 TiN을 각각 1000Å 및 700Å 두께로 증착한 것을 특징으로 하는 반도체 소자의 비아 플러그 형성방법.The method of claim 1, wherein the first junction layer (11) and the second junction layer (13) are formed by depositing TiN at a thickness of 1000 kPa and 700 kPa with a PVD reactor, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016645A 1993-08-26 1993-08-26 Via plug forming method of semiconductor device KR960015498B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930016645A KR960015498B1 (en) 1993-08-26 1993-08-26 Via plug forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016645A KR960015498B1 (en) 1993-08-26 1993-08-26 Via plug forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950006994A true KR950006994A (en) 1995-03-21
KR960015498B1 KR960015498B1 (en) 1996-11-14

Family

ID=19361988

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930016645A KR960015498B1 (en) 1993-08-26 1993-08-26 Via plug forming method of semiconductor device

Country Status (1)

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KR (1) KR960015498B1 (en)

Also Published As

Publication number Publication date
KR960015498B1 (en) 1996-11-14

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