KR910013464A - Contact hole formation method for multilayer wiring - Google Patents

Contact hole formation method for multilayer wiring Download PDF

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Publication number
KR910013464A
KR910013464A KR1019890020712A KR890020712A KR910013464A KR 910013464 A KR910013464 A KR 910013464A KR 1019890020712 A KR1019890020712 A KR 1019890020712A KR 890020712 A KR890020712 A KR 890020712A KR 910013464 A KR910013464 A KR 910013464A
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KR
South Korea
Prior art keywords
contact hole
forming
film
layer
wiring layer
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Application number
KR1019890020712A
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Korean (ko)
Inventor
안용철
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020712A priority Critical patent/KR910013464A/en
Publication of KR910013464A publication Critical patent/KR910013464A/en

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Abstract

내용 없음.No content.

Description

다층배선시 콘택트 홀 형성방법Contact hole formation method for multilayer wiring

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2G도는 본 발명에 의한 다층배선시 콘택트 홀 형성방법을 도시한 공정순서도.2A to 2G are process flowcharts showing a method for forming contact holes in multilayer wiring according to the present invention.

Claims (7)

반도체기판에 절연되게 하부 배선층을 형성하고, 이 하부 배선층위에 평탄화된 절연막을 형성하여, 상기 하부 배선층상의 절연막에 콘택트 홀을 형성하는 다층 배선시 콘택트 홀 형성방법에 있어서, 상기 콘택트 홀에 측벽 스페이서를 형성함을 특징으로 하는 다층배선시 콘택트 홀 형성방법.A method for forming a contact hole in a multilayer wiring in which a lower wiring layer is formed to be insulated from a semiconductor substrate, and a flattened insulating film is formed on the lower wiring layer, thereby forming contact holes in the insulating film on the lower wiring layer. Forming a contact hole in the multi-layer wiring, characterized in that the forming. 제1항에 있어서, 상기 측벽 스페이서는 플라즈마 실리콘 나이트라이드로 하는 것을 특징으로 하는 다층 배선시 콘택트 홀 형성방법.The method of claim 1, wherein the sidewall spacers are formed of plasma silicon nitride. 제1항에 있어서, 상기 측벽 스페이서는 플라즈마 실리콘 옥시나이트라이드로 하는 것을 특징으로 하는 다층 배선시 콘택트 홀 형성방법.The method of claim 1, wherein the sidewall spacers are made of plasma silicon oxynitride. 제1항에 있어서, 상기 측벽 스페이서는 저압 및 상압 증착하여 생성된 실리콘 나이트라이드계로 하는 것을 특징으로 하는 다층배선시 콘택트 홀 형성방법.The method of claim 1, wherein the sidewall spacers are formed of silicon nitride based on low pressure and atmospheric pressure deposition. 반도체기판에 절연되게 형성된 하부 배선층위에 제1산화막을 피복하고, 이후 평탄화를 위한 SOG막, 제2산화막을 차례로 적층하여, 상기 하부 배선층상의 소정 부위에 콘택트 홀을 형성하는 다층배선시 콘택트 홀 형성방법에 있어서, 상기 하부 배선층상의 SOG막 및 제2산화막을 식각하여 1차 콘택트 홀을 형성하는 공정과; 상기 1차 콘택트 홀을 형성할때 세정공정에서 SOG막 속에 침투된 수분의 발산을 막기 위하여, 상기 1차 콘택트 홀의 내측벽을 따라 저지막을 형성하는 공정과, 상기 저지막을 마스크로 사용하여 1차 배선층상의 제1산화막을 식각함으로서 콘택트 홀을 형성하는 공정으로 이루어지는 것을 특징으로 하는 다층배선시 콘택트 홀 형성방법.A method for forming a contact hole in a multilayer wiring in which a first oxide film is coated on a lower wiring layer insulated from a semiconductor substrate, and then a SOG film for planarization and a second oxide film are sequentially stacked to form contact holes in predetermined portions on the lower wiring layer. Forming a primary contact hole by etching the SOG film and the second oxide film on the lower wiring layer; Forming a blocking film along the inner wall of the primary contact hole to prevent the release of moisture penetrated into the SOG film in the cleaning process when forming the primary contact hole, and using the blocking film as a mask to form a primary wiring layer And forming a contact hole by etching the first oxide film on the phase. 제5항에 있어서, 상기 저지막은 제2산화막 및 1차 콘택트 홀에, 플라즈마 실리콘 나이트라이드를 증착한 후 에치백 공정을 통하여, 상기 1차 콘택트 홀의 SOG막 및 제2산화막의 측벽을 따라 형성된 측벽 스페이서임을 특징으로 하는 다층배선시 콘택트 홀 형성방법.The sidewall of claim 5, wherein the blocking layer is formed by depositing plasma silicon nitride in the second oxide layer and the primary contact hole, and then performing an etchback process to form a sidewall of the SOG layer and the second oxide layer of the primary contact hole. Method for forming a contact hole in the multilayer wiring, characterized in that the spacer. 제5항에 있어서, 상기 지지막은 SOG막속에 침투되 수분의 발산을 저지하기 위한 재료로 하는 것을 특징으로 하는 다층배선시 콘택트 홀 형성방법.6. The method of claim 5, wherein the support film is made of a material for penetrating into the SOG film and preventing the release of moisture. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020712A 1989-12-30 1989-12-30 Contact hole formation method for multilayer wiring KR910013464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020712A KR910013464A (en) 1989-12-30 1989-12-30 Contact hole formation method for multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020712A KR910013464A (en) 1989-12-30 1989-12-30 Contact hole formation method for multilayer wiring

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KR910013464A true KR910013464A (en) 1991-08-08

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KR1019890020712A KR910013464A (en) 1989-12-30 1989-12-30 Contact hole formation method for multilayer wiring

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434713B1 (en) * 1996-12-27 2004-09-01 주식회사 하이닉스반도체 Method of manufacturing semiconductor device with corrosion-free metal line and defect-free via hole

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434713B1 (en) * 1996-12-27 2004-09-01 주식회사 하이닉스반도체 Method of manufacturing semiconductor device with corrosion-free metal line and defect-free via hole

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