KR960002681A - How to Form Multilayer Metal Wiring - Google Patents

How to Form Multilayer Metal Wiring Download PDF

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Publication number
KR960002681A
KR960002681A KR1019940015011A KR19940015011A KR960002681A KR 960002681 A KR960002681 A KR 960002681A KR 1019940015011 A KR1019940015011 A KR 1019940015011A KR 19940015011 A KR19940015011 A KR 19940015011A KR 960002681 A KR960002681 A KR 960002681A
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KR
South Korea
Prior art keywords
forming
film
interlayer insulating
layer
metal
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Application number
KR1019940015011A
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Korean (ko)
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KR0127689B1 (en
Inventor
최승봉
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김주용
현대전자산업 주식회사
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Priority to KR1019940015011A priority Critical patent/KR0127689B1/en
Publication of KR960002681A publication Critical patent/KR960002681A/en
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Publication of KR0127689B1 publication Critical patent/KR0127689B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure

Abstract

본 발명은 콘택홀 깊이를 완화하여 스텝커버리지 특성을 개선하고, SOG막이 금속막에 접하게 되는 것을 방지하기 위한 다층 금속배선 형성방법에 관한 것으로 하부금속막(21)을 형성한 후 층간절연막(22), SOG막(23)을 형성하는 단계; 마스크 없이 금속막(21)위에 소정정도의 층간절연막(22)이 전류하도록 상기 SOG막(23), 층간절연막(22)을 식각한 후 전체구조 상부에 다시 층간절연막(24)을 형성하는 단계; 배선형성 부위의 상기 층간절연막(24,22)을 선택식각한 후 금속막(25)을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for forming a multi-layered metal wiring for reducing the contact hole depth to improve step coverage characteristics and to prevent the SOG film from coming into contact with the metal film. After forming the lower metal film 21, the interlayer insulating film 22 is formed. Forming a SOG film 23; Etching the SOG film 23 and the interlayer insulating film 22 so that a predetermined amount of the interlayer insulating film 22 is current on the metal film 21 without a mask, and then forming the interlayer insulating film 24 over the entire structure; And forming a metal film 25 after selectively etching the interlayer insulating films 24 and 22 of the wiring forming portion.

Description

다층 금속배선 형성방법How to Form Multilayer Metal Wiring

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 일실시예의 이층 금속배선 형성 공정 단면도,2 is a cross-sectional view of a two-layer metallization process of an embodiment according to the present invention;

제3도는 본 발명의 다른 실시예에 따른 금속배선 형성 공정 단면도,3 is a cross-sectional view of a metallization process according to another embodiment of the present invention;

제4도는 본 발명의 또다른 실시예에 따른 금속배선 형성 공정 단면도.4 is a cross-sectional view of a metallization process according to another embodiment of the present invention.

Claims (6)

반도체 소자 제고공정 중 다층 금속배선 형성방법에 있어서, 하부금속막(21)을 형성한 후 층간절연막(22), SOG막(23)을 형성하는 단계; 마스크 없이 금속막(21)위에 소정정도의 층간절연막(22)이 잔류하도록 상기 SOG막(23), 층간절연막(22)을 식각한 후 전체구조 상부에 다시 층간절연막(24)을 형성하는 단계; 배선형 부위의 상기 층간절연막(24,22)을 선택식각한 후 금속막(25)을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 다층 금속배선 형성방법.A method of forming a multi-layer metal wiring during a semiconductor device manufacturing process, the method comprising: forming an interlayer dielectric layer 22 and an SOG layer 23 after forming a lower metal layer 21; Etching the SOG film 23 and the interlayer insulating film 22 so that a predetermined level of the interlayer insulating film 22 remains on the metal film 21 without a mask, and then forming the interlayer insulating film 24 on the entire structure again; And forming a metal film (25) after selectively etching the interlayer insulating film (24,22) in the wiring region. 반도체 소자 제조공정 중 다층 금속배선 형성방법에 있어서, 하부금속막(31)을 형성한 후 층간절연막(32), SOG막(33)을 형성하는 단계; 마스크 없이 금속막(31)이 노출되도록 상기 SOG막(33), 층간절연막(32)을 식각한 후 전체구조 상부에 다시 층간절연막(34)을 형성하는 단계; 상기 층간절연막(34)을 마스크 없이 식각한 후 금속막(35)을 증착하여 금속배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 다층 금속배선 형성방법.A method of forming a multi-layer metal wiring in a semiconductor device manufacturing process, the method comprising: forming an interlayer insulating layer 32 and an SOG layer 33 after forming a lower metal layer 31; Etching the SOG film 33 and the interlayer insulating film 32 so that the metal film 31 is exposed without a mask, and then forming the interlayer insulating film 34 on the entire structure again; And etching the interlayer dielectric layer (34) without a mask and then depositing a metal layer (35) to form metal lines. 제2항에 있어서, 상기 하부금속막(31)은 15000 내지 20000Å 두께로 형성되는 것을 특징으로 하는 다층 금속배선 형성방법.3. The method of claim 2, wherein the lower metal film (31) is formed to a thickness of 15000 to 20000 Å. 제2항에 있어서, 상기 층간절연막(32)은 플라즈마화학기상증착(PECVD)법으로 형성되는 것을 특징으로 하는 다층 금속배선 형성방법.3. The method of claim 2, wherein the interlayer dielectric layer (32) is formed by plasma chemical vapor deposition (PECVD). 제2항에 있어서, 상기 SOG막(33) 도포 후 350 내지 430℃의 온도에서 커링(curing)하여 안정화시키는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 다층 금속배선 형성방법.3. The method of claim 2, further comprising curing and stabilizing at a temperature of 350 to 430 ° C after applying the SOG film (33). 제2항에 있어서, 상기 층간절연막(34)을 마스크 없이 식각한 후 장벽금속막(47)을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 다층 금속배선 형성방법.3. The method of claim 2, further comprising forming a barrier metal film (47) after etching the interlayer insulating film (34) without a mask. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940015011A 1994-06-28 1994-06-28 Forming method for multi layered metal line KR0127689B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940015011A KR0127689B1 (en) 1994-06-28 1994-06-28 Forming method for multi layered metal line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940015011A KR0127689B1 (en) 1994-06-28 1994-06-28 Forming method for multi layered metal line

Publications (2)

Publication Number Publication Date
KR960002681A true KR960002681A (en) 1996-01-26
KR0127689B1 KR0127689B1 (en) 1997-12-29

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Application Number Title Priority Date Filing Date
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