KR0127689B1 - Forming method for multi layered metal line - Google Patents
Forming method for multi layered metal lineInfo
- Publication number
- KR0127689B1 KR0127689B1 KR1019940015011A KR19940015011A KR0127689B1 KR 0127689 B1 KR0127689 B1 KR 0127689B1 KR 1019940015011 A KR1019940015011 A KR 1019940015011A KR 19940015011 A KR19940015011 A KR 19940015011A KR 0127689 B1 KR0127689 B1 KR 0127689B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- metal wiring
- entire structure
- insulating film
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 종래방법에 따라 형성된 이층 금속배선의 단면도.1 is a cross-sectional view of a two-layer metal wiring formed according to a conventional method.
제2도는 본 발명의 일실시예에 따른 다층 금속배선 형성 공정 단면도.2 is a cross-sectional view of a multi-layer metallization process according to an embodiment of the present invention.
제3도는 본 발명의 다른 실시예에 따른 다층 금속배선 형성 공정 단면도.3 is a cross-sectional view of a multilayer metallization process according to another embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
31, 41 : 하부 금속배선32, 34, 42, 44 : IMO31, 41: Lower metal wiring 32, 34, 42, 44: IMO
33, 43 : SOG막35, 45 : 상부 금속배선33, 43: SOG films 35, 45: upper metal wiring
47 : TiN막47: TiN film
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 소자 제조공정 중 다층 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a multi-layered metal wiring during a semiconductor device manufacturing process.
일반적으로, 반도체 소자의 고집적화에 따라 층간의 전기적 접속을 위하여 다층 금속배선 공정은 일반화되어 있다.In general, multilayer metallization processes are common for electrical connection between layers due to high integration of semiconductor devices.
종래의 다층 금속배선 공정에서 층간절연막에 SOG(spin on glass)막이 포함될 경우 측벽의 SOG막이 상부 금속막 증착시의 고온에 의해 가스를 배출(out-gassing)하게 되고, 이로 인해 금속막 증착이 불안정해지는 포이즌 비아(poisoned via) 현상이 발생한다.In the conventional multi-layer metallization process, when the interlayer insulating film includes a spin on glass (SOG) film, the SOG film on the sidewall causes out-gassing due to the high temperature during deposition of the upper metal film. Poisoned vias occur.
첨부된 도면 제1도는 종래방법에 따라 형성된 이층 금속배선의 단면도로서, 이를 통하여 종래 기술을 개략적으로 설명하면 다음과 같다.1 is a cross-sectional view of a two-layer metal wiring formed according to a conventional method, and through this, the prior art is schematically described as follows.
도면에 도시된 바와 같이 10000Å정도 두께의 하부 금속배선(1) 위에 IMO(inter-metallic oxide, 2)를 증착하고, SOG 도포 및 소성(curing)고정을 통해 SOG막(3)을 형성하여 평탄화를 이루고, 다시 IMO(4)를 증착한 후 비아홀 형성용 마스크를 이용하여 IMO(4), SOG막(3) 및 IMO(2)를 차례로 선택 식각함으로써 비아홀을 형성한다. 계속하여, 전체구조 상부에 금속막을 증착하고, 이를 패터닝하여 상부 금속배선(5)을 형성하여 이층 금속배선을 형성하게 된다.As shown in the figure, an inter-metallic oxide (IMO) 2 is deposited on the lower metal wiring 1 having a thickness of about 10000 kPa, and the SOG film 3 is formed by SOG coating and curing. After the deposition of the IMO 4, the via hole is formed by selectively etching the IMO 4, the SOG film 3, and the IMO 2 using the via hole forming mask. Subsequently, a metal film is deposited on the entire structure, and patterned to form the upper metal wiring 5 to form a two-layer metal wiring.
그러나, 이러한 종래의 다층 금속배선 형성방법을 사용할 경우, 반도체 소자의 고집적화에 따른 비아홀을 종횡비(aspect ratio) 증가에 의해 단차피복성이 불량해지고, 폴리머(polymer)가 유발되는 문제점이 있었으며, 앞서 설명한 바와 같이 SOG막이 금속콘택과 직접적으로 접촉함으로 인해 포이즌 비아 현상을 유발하는 문제점이 있었다.However, when using the conventional multi-layered metal wiring formation method, the step coverage is poor due to the increase in aspect ratio of the via hole due to the high integration of the semiconductor device, and there is a problem that polymer is caused. As described above, there is a problem in that the poison via phenomenon occurs due to the SOG film directly contacting the metal contact.
본 발명은 비아홀 형성을 필요로 하지 않으며, 금속막이 SOG막에 직접적으로 노출되지 않는 다층 금속배선 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a multi-layered metal wiring, which does not require via hole formation, and in which the metal film is not directly exposed to the SOG film.
상기 목적을 달성하기 위하여 본 발명의 다층 금속배선 형성방법은 반도체 기판 상에 형성된 소정의 하부층 상부에 하부 금속배선을 형성하는 단계 ; 전체구조 상부에 제1절연막 및 스핀-온-글래스막을 차례로 형성하는 단계 ; 상기 스핀-온-글래스막 및 상기 제1절연막을 전면성 식각하여 상기 하부 금속배선의 일부를 노출시키는 단계 ; 전체구조 상부에 제2절연막을 형성하는 단계 ; 상기 제2절연막을 전면성 식각하여 상기 하부 금속배선의 일부를 노출시키는 단계 ; 및 전체구조 상부에 금속막을 형성하고 이를 패터닝하여 상부 금속배선을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of forming a multi-layered metal wiring, including forming a lower metal wiring on a predetermined lower layer formed on a semiconductor substrate; Sequentially forming a first insulating film and a spin-on-glass film on the entire structure; Etching the spin-on-glass film and the first insulating film to be entirely etched to expose a portion of the lower metal wiring; Forming a second insulating film over the entire structure; Etching the entire surface of the second insulating layer to expose a portion of the lower metal wiring; And forming a metal film on the entire structure and patterning the metal film to form an upper metal wiring.
또한, 본 발명의 다층 금속배선 형성방법은 반도체 기판 상에 형성된 소정의 하부층 상부에 하부 금속배선을 형성하는 단계 ; 전체구조 상부에 절연막 및 스핀-온-글래스막을 차례로 형성하는 단계 ; 상기 스핀-온-글래스막 및 상기 절연막을 전면성 식각하여 상기 하부 금속배선의 일부를 노출시키는 단계 ; 전체 구조 상부에 장벽금속막을 형성하는 단계 ; 및 전체구조 상부에 주금속막을 형성하고 상기 장벽금속막 및 상기 주금속막을 패터닝하여 상부 금속배선을 형성하는 단계를 포함하여 이루어진다.In addition, the method of forming a multi-layer metal wiring of the present invention comprises the steps of forming a lower metal wiring on a predetermined lower layer formed on a semiconductor substrate; Sequentially forming an insulating film and a spin-on-glass film on the entire structure; Etching the spin-on-glass film and the insulating film on the entire surface to expose a portion of the lower metal wiring; Forming a barrier metal film on the entire structure; And forming a main metal film on the entire structure and patterning the barrier metal film and the main metal film to form an upper metal wiring.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2A도 내지 제2C도는 본 발명의 일실시예에 따른 이층 금속배선 형성 공정 단면도로서, 먼저 제2A도에 도시된 바와 같이 실리콘 기판(도시되지 않음) 상에 형성된 소정의 하부층(도시되지 않음) 상부에 하부 금속배선(31)을 17000Å정도로 두껍게 형성한 후, 전체구조 상부에 플라즈마 화학기상증착(PECVD) 방식을 사용하여 IMO(32)를 증착하고, SOG막(33)을 도포하고 400℃의 온도에서 소성(curing) 공정을 진행한다.2A to 2C are cross-sectional views of a two-layer metallization process according to an embodiment of the present invention, and a predetermined lower layer (not shown) formed on a silicon substrate (not shown) first as shown in FIG. 2A. After forming the lower metal wiring 31 thickly on the upper side of about 17000Å, IMO (32) is deposited on the whole structure by using a plasma chemical vapor deposition (PECVD) method, and the SOG film 33 is applied and 400 DEG C of Curing process is performed at temperature.
이어서, 제2B도에 도시된 바와 같이 하부 금속배선(31)이 1000 내지 2000Å 정도 노출되도록 SOG막(33) 및 IMO(32)를 전면식각한 후, 전체구조 상부에 다시 IMO(34)를 6000Å 이상의 두께로 증착한다.Subsequently, as shown in FIG. 2B, the SOG film 33 and the IMO 32 are completely etched so that the lower metal wiring 31 is exposed to about 1000 to 2000 mV, and then the IMO 34 is again 6000 m over the entire structure. It deposits to the thickness more than.
끝으로, 제2C에 도시된 바와 같이 IMO(34)를 전면성 식각하여 하부 금속배선(31)을 노출시키고, 하부 금속배선(31)에 접속되는 상부 금속배선(35)을 형성한다.Finally, as shown in FIG. 2C, the IMO 34 is etched entirely to expose the lower metal wiring 31 and form the upper metal wiring 35 connected to the lower metal wiring 31.
첨부된 도면 제3A도 내지 제3C도는 본 발명의 다른 실시예에 따른 금속배선 형성 공정 단면도로서, 먼저, 제3A도에 도시된 바와 같이 실리콘 기판(도시되지 않음) 상에 형성된 소정의 하부층(도시되지 않음) 상부에 하부 금속배선(31)을 17000Å 정도로 두껍게 형성한 후, 전체구조 상부에 플라즈마 화학기상증착 방식을 사용하여 IMO(42)를 증착하고, SOG막(43)을 도포하고 350 내지 430℃의 온도에서 소성(curing) 공정을 진행한다.3A to 3C are cross-sectional views of a metal wiring forming process according to another embodiment of the present invention. First, a predetermined lower layer (not shown) formed on a silicon substrate (not shown) is illustrated as shown in FIG. 3A. After the lower metal wiring 31 is formed to a thickness of about 17000 kPa, the IMO 42 is deposited on the entire structure by using a plasma chemical vapor deposition method, and the SOG film 43 is coated and 350 to 430 Curing process is performed at a temperature of ℃.
이어서, 제3B도에 도시된 바와 같이 마스크 없이 하부 금속배선(41)이 500 내지 1500Å 이상 노출되도록 SOG막(43) 및 IMO(42)를 전면 식각한 후, 전체구조 상부에 장벽금속막인 TiN막(47)을 500 내지 1000Å두께로 증착한다. 이 때, 티타늄(Ti)과 질소(N)의 비율이 동일하도록 증착하여 N2가스를 많이 사용한다.Subsequently, as shown in FIG. 3B, the SOG film 43 and the IMO 42 are etched entirely so that the lower metal wiring 41 is exposed to 500 to 1500 mV or more without a mask, and then TiN, which is a barrier metal film, is formed on the entire structure. The film 47 is deposited to a thickness of 500 to 1000 mm 3. At this time, the deposition of titanium (Ti) and nitrogen (N) is the same to use a lot of N 2 gas.
끝으로, 제3C도에서 전체구조 상부에 금속막(45)을 증착하고, TiN막(47) 및 금속막(45)을 선택 식각하여 상부 금속배선(45)을 형성한다.Finally, in FIG. 3C, the metal film 45 is deposited on the entire structure, and the TiN film 47 and the metal film 45 are selectively etched to form the upper metal wiring 45.
상기와 같이 이루어지는 본 발명은 층간절연막의 전면성 식각을 통해 비아홀을 형성을 생략할 수 있게 되어 단차피복성 문제를 극복할 수 있으며, SOG막이 비아홀 측벽에 노출되지 않게 됨으로써 SOG막의 수분에 의한 영향을 배제할 수 있다. 또한, 마스크 공정을 생략할 수 있으므로 공정 간소화를 기대할 수 있다.According to the present invention as described above, the via hole can be omitted through the entire surface etching of the interlayer insulating film, thereby overcoming the step coverage problem, and the SOG film is not exposed to the sidewalls of the via hole. Can be excluded. In addition, since the mask process can be omitted, process simplification can be expected.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940015011A KR0127689B1 (en) | 1994-06-28 | 1994-06-28 | Forming method for multi layered metal line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940015011A KR0127689B1 (en) | 1994-06-28 | 1994-06-28 | Forming method for multi layered metal line |
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| Publication Number | Publication Date |
|---|---|
| KR960002681A KR960002681A (en) | 1996-01-26 |
| KR0127689B1 true KR0127689B1 (en) | 1997-12-29 |
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| KR1019940015011A KR0127689B1 (en) | 1994-06-28 | 1994-06-28 | Forming method for multi layered metal line |
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| KR (1) | KR0127689B1 (en) |
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1994
- 1994-06-28 KR KR1019940015011A patent/KR0127689B1/en not_active IP Right Cessation
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| KR960002681A (en) | 1996-01-26 |
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