KR100235947B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR100235947B1 KR100235947B1 KR1019970017012A KR19970017012A KR100235947B1 KR 100235947 B1 KR100235947 B1 KR 100235947B1 KR 1019970017012 A KR1019970017012 A KR 1019970017012A KR 19970017012 A KR19970017012 A KR 19970017012A KR 100235947 B1 KR100235947 B1 KR 100235947B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000002994 raw material Substances 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 235000013547 stew Nutrition 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 48
- 238000000151 deposition Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000010936 titanium Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 다층의 금속배선을 구비하고 금속배선간 절연막으로 SOG층을 사용하는 반도체소자에서 금속배선간을 연결시키는 비아콘택홀 형성시 SOG막의 리세스(recess)된 부분을 단차피복성 및 산화막과의 접착성이 우수한 PECVD법으로 W층을 형성하여 리세스된 부분을 메우고, 그 상부에 WNX층을 형성한 다음 Al층을 증착하여 비아콘택홀을 매립하거나, 비아콘택홀을 형성한 다음 PECVD법으로 W층을 형성하고 CVD법으로 W층을 형성하여 비아콘택홀을 매립한 후 AI층을 형성하여 제2금속배선을 형성함으로서 비아콘택홀의 매립실패에 의한 불량률을 감소시켜 반도체 소자의 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, wherein a recess of a SOG film is formed when a via contact hole is formed in a semiconductor device having a multi-layered metal wiring and using an SOG layer as an insulating film between metal wirings. Form the W layer by filling the recessed portion with PECVD, which has high step coverage and adhesion to the oxide film, and fills the recessed portion, forms a WN X layer on the top, and then deposits an Al layer to fill the via contact hole. After the via contact hole is formed, the W layer is formed by PECVD, the W layer is formed by the CVD method, the via contact hole is embedded, and the AI layer is formed to form the second metal wiring. The present invention relates to a technology capable of improving the reliability of a semiconductor device by reducing a defective rate.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 금속배선간을 연결시키는 비아콘택홀을 형성시 에스오지(Spin On Glass 이하, SOG)막의 리세스된 부분을 플라즈마 화학기상증착법(Plasma Enhanced Chemical Vapor Deposition 이하, PECVD)으로 텅스텐(W)층을 형성하여 메우거나 PECVD법으로 W층을 형성한 후 화학기상증착법(Chemical Vapor Deposition 이하, CVD)으로 W층을 형성하여 비아콘택홀을 메운다음, WNx층을 형성하고 알루미늄(Al)층을 형성하여 제2금속배선을 형성함으로서 안정된 비아콘택 저항특성에 의해 반도체 소자의 신뢰성을 향상시킬 수 있는 기술에 관한 것이다BACKGROUND OF THE
반도체 소자에서 상하의 도전배선을 연결하는 콘택홀은 자체의 크기와 주변 배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)는 증가한다.In the semiconductor device, the contact hole connecting the upper and lower conductive wirings is reduced in size and spacing between peripheral wirings, and an aspect ratio, which is a ratio of the diameter and the depth of the contact hole, is increased.
따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소한다Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
제1도는 종래 기술에 따른 반도체 소자의 공정단면도이다.1 is a process cross-sectional view of a semiconductor device according to the prior art.
먼저, 반도체 기판(1) 상부에 소정의 하부 구조물들, 예컨대 소자분리 산화막과, 모스 전계효과 트랜지스터, 비트선, 캐패시터등을 형성하고, 상기 구조의 전표면에 제1평탄화막(도시 않됨)을 형성한다.First, predetermined lower structures such as a device isolation oxide film, a MOS field effect transistor, a bit line, and a capacitor are formed on the
다음, 상기 제1평탄화막 상부에 금속배선(2)을 형성하고, 산화막으로 이루어진 제1층간절연막(3)을 형성한 다음, 제2평탄화막인 SOG막(4)을 형성하고, 산화막의 재질로 이루어진 제2층간절연막(5)을 형성한다.Next, a
그 다음, 상기 제2층간절연막(5) 상부에 비아콘택 식각마스크용 감광막패턴(도시 않됨)을 형성하고, 순차적으로 식각하여 금속배선(2)의 상측을 노출시키는 비아 콘택홀(6)을 형성한다.Next, a photoresist layer pattern (not shown) for a via contact etching mask is formed on the second interlayer insulating layer 5, and the
다음, 상기 구조의 전표면에 접합층으로서 티타늄(Ti,7)막을 형성한 다음, 알루미늄(Al)합금을 증착하여 제2금속배선(도시 않됨)을 형성한다.Next, a titanium (Ti, 7) film is formed on the entire surface of the structure as a bonding layer, and then an aluminum (Al) alloy is deposited to form a second metal wiring (not shown).
상기와 같은 종래기술에 따른 반도체 소자의 제조방법은 비아콘택홀을 형성한 후 감광막패턴을 제거하는 과정에서 수분 및 탄소의 함유성분이 SOG막 내부로 확산되어 비아콘택홀 측면의 SOG 층이 움푹 들어가게 된다.In the method of manufacturing a semiconductor device according to the related art as described above, in the process of removing the photoresist pattern after forming the via contact hole, moisture and carbon-containing components diffuse into the SOG film so that the SOG layer on the side of the via contact hole is recessed. do.
따라서, 접착층으로 쓰이는 Ti막 증착시 리세스(recess)된 부분에는 Ti층이 형성되지 않으며, 후속공정의 Al막을 증착할 때 비아콘택홀이 제대로 일어나지 않게 되어 불량을 유발하게 된다.Therefore, the Ti layer is not formed in the recessed portion during the deposition of the Ti film used as the adhesive layer, and the via contact hole does not occur properly when the Al film is deposited in a subsequent process, thereby causing a defect.
또한, SOG층의 리세스를 없애기 위하여 SOG층을 증착한 후 이온주입, 이-빔(e-beam)공정을 진행하여 SOG층의 수분 및 탄소를 제거하면서 고밀화(densify)시키는 방법이 검토되고 있으나. 이는 산화막(oxide)층에 손상(damage)를 주게 되어 Vt저하 및 shift등 소자의 신뢰성을 저하시키는 문제점이 있다.In addition, in order to remove the recess of the SOG layer, a method of densify while removing moisture and carbon from the SOG layer by performing ion implantation and e-beam process after depositing the SOG layer is being studied. . This causes damage to the oxide layer, which causes a problem of lowering the reliability of the device such as V t reduction and shift.
이에,본 발명은 상기한 문제점을 해결하기 위한 것으로 비아콘택홀을 형성 후 감광막 제거과정에서 생기는 SOG막의 리세스된 부분을 단차피복성 및 산화막과의 접착성이 우수한 PECVD법으로 W층을 형성하여 리세스된 부분을 메우고, 그 상부에 WNx층을 형성한 다음 Al층을 증착하여 비아콘택홀을 매립하거나. 비아콘택홀을 형성 후 PECVD법으로 W층을 형성하고 CVD법으로 W층을 형성하여 비아콘택홀을 매립한 다음 AI층을 형성하여 제2금속층을 형성함으로서 비아콘택홀의 매립실패에 의한 불량률을 감소기켜 반도체 소자의 신뢰성을 향상시키는 반도체 소자의 제조방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention is to solve the above problems by forming the W layer by PECVD method to the stepped coating and the adhesion of the oxide film to the recessed portion of the SOG film generated during the photoresist film removal process after forming the via contact hole Filling the recessed portion, forming a WNx layer on top thereof, and then depositing an Al layer to fill the via contact hole. After the via contact hole is formed, the W layer is formed by PECVD, the W layer is formed by CVD, and the via contact hole is filled, and then the AI layer is formed to form the second metal layer, thereby reducing the defect rate due to the buried failure of the via contact hole. It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device.
제1도 는 종래 기술에 따른 반도체 소자의 공정 단면도.1 is a process cross-sectional view of a semiconductor device according to the prior art.
제2a도 내지 제2b도 는 본 발명의 일실시예에 따른 반도체 소자의 제조공정단면도.2a to 2b is a cross-sectional view of the manufacturing process of the semiconductor device according to an embodiment of the present invention.
제3a도 내지 제3b도 는 본 발명의 다른 실시예에 따른 반도체 소자의 제조공정 단면도.3A to 3B are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 기판 12 : 제1금속배선10
14 : 제1산화막 16 : SOG막14: first oxide film 16: SOG film
18 : 제2산화막 20 : 비아콘택홀18: second oxide film 20: via contact hole
22, 30 : PECVD - W층 24, 34 : WNx층22, 30: PECVD-
26, 36 : 제2금속배선 32 : CVD-W층26, 36: second metal wiring 32: CVD-W layer
상기 목적을 달성하기 위해 본 발명의 일실시예에 따른 반도체 소자의 제조방법은 반도체 기판 상부에 제1금속배선을 형성하는 공정과, 상기 구조의 전표면에 제1산화막을 형성하는 공정과. 상기 제1산화막 상부에 SOG막을 형성하는 공정과, 상기 SOG막 상부에 제2산화막을 형성하는 공정과, 상기 제1금속배선과의 콘택으로 예정되어 있는 부분을 식각하여 제1금속배선 상측을 노출시키는 비아콘택을 형성하는 공정과, 상기 구조의 전표면에 PECVD법으로 상기 SOG막의 리세스된 부분을 메우는 W층을 형성하는 공정과, 상기 구조의 전표면에 PECVD법으로 WNx층을 형성하는 공정과, 상기 WNx층 상부에 상기 비아콘택홀을 매립하는 제2금속배선을 형성하는 공정을 특징으로 한다In order to achieve the above object, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a first metal wiring on a semiconductor substrate, and forming a first oxide film on the entire surface of the structure. Forming a SOG film on the first oxide film, a process of forming a second oxide film on the SOG film, and etching a portion which is intended to be in contact with the first metal wire, thereby exposing an upper side of the first metal wire. Forming a via contact, forming a W layer filling the recessed portion of the SOG film on the entire surface of the structure by PECVD, and forming a WNx layer on the entire surface of the structure by PECVD. And forming a second metal wiring buried in the via contact hole on the WNx layer.
또한, 본 발명의 다른 실시예에 따른 반도체 소자의 제조방법은 반도체 기판 상부에 제1금속배선을 형성하는 공정과, 상기 구조의 전표면에 제1산화막을 형성하는 공정과, 상기 제1산화막 상부에 SOG막을 형성하는 공정과, 상기 SOG막 상부에 제2산화막을 형성하는 공정과, 상기 제1금속배선과의 콘택으로 예정되어 있는 부분을 식각하여 제1금속배선 상측을 노출시키는 비아콘택홀을 형성하는 공정과, 상기 구조의 전표면에 PECVD법으로 상기 SOG막의 리세스된 부분을 메우는 W층을 형성하는 공정과, 상기 구조의 전표면에 CVD법으로 W층을 형성하여 상기 비아콘택홀을 매립하는 공정과, 상기 구조의 전표면에 PECVD법으로 WNx층을 형성하는 공정과, 상기 WNx층 상부에 제2금속배선을 형성하는 공정을 특징으로 한다.In addition, a method of manufacturing a semiconductor device according to another embodiment of the present invention is a step of forming a first metal wiring on the semiconductor substrate, a step of forming a first oxide film on the entire surface of the structure, and the top of the first oxide film Forming a second oxide film on the top of the SOG film; and a via contact hole exposing an upper portion of the first metal wiring by etching a portion scheduled as a contact with the first metal wiring. Forming a W layer on the entire surface of the structure by PECVD to fill the recessed portion of the SOG film; and forming a W layer on the entire surface of the structure by CVD to form the via contact hole. And a step of forming a WNx layer on the entire surface of the structure by PECVD and a step of forming a second metal wiring on the WNx layer.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2c도 는 본 발명의 일실시예에 따른 반도체 소자의 제조 공정 단면도이다.2A through 2C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체 기판(10) 상부에 소정의 하부 구조물들, 예컨대 소자분리 산화막과, 모스 전계효과 트랜지스터, 비트선, 캐패시터등을 형성하고, 상기 구조의 전표면에 제1평탄화막(도시 않됨)을 형성한다.First, predetermined lower structures such as a device isolation oxide film, a MOS field effect transistor, a bit line, and a capacitor are formed on the
다음, 상기 제1평탄화막 상부에 제1금속배선(12)을 형성하고, 층간절연막으로 제1산화막(14)을 형성한 다음, 제2평탄막으로 SOG막(16)을 형성하고, 층간절연막으로 제2산화막(18)을 형성한다.Next, a
그 다음, 상기 제2산화막(18) 상부에 비아콘택 식각마스크용 감광막패턴(도시 않됨)을 형성하고, 상기 제1금속배선(12)과의 콘택으로 예정되어 있는 부분을 순차적으로 식각하여 제1금속배선(12)의 상측을 노출시키는 비아콘택홀(20)을 형성한다.Subsequently, a photoresist pattern (not shown) for a via contact etch mask is formed on the
이때, 상기 SOG막(16)은 수분 및 탄소 성분의 확산에 의해 측면에는 움푹 들어간 리세스부분이 형성된다.At this time, the
다음, 상기 구조의 전표면에 단차피복성(step covetage)이 좋으며, 접착성이 우수한 PECVD법에 의한 W층(22)을 500~1000Å 두께로 증착하여 상기 SOG막(16)의 리세스된 부분을 매립하여 평탄화한다.Next, the recessed portion of the
이 때, 상기 PECVD-W층(22)은 300 ~ 450℃ 온도범위에서 증착한다.At this time, the PECVD-
그 다음, 상기 구조의 전표면에 PECVD법에 의한 WNx막(24)을 형성한 다음, 비정질 구조를 갖도록 질소/수소의 유량비를 0.1 ~ 0.2 갖는 범위에서 실시하여 10 ~ 100Å 두께로 형성한다.Then, the WNx
여기서, 상기 W층(22,24)은 인-시튜(in - situ)로 형성한다.Herein, the
여기서, 상기 PECVD - WNx막(24)은 대기 노출에 의한 텅스텐의 산화를 방지하게 된다.(제2a도 참조)Here, the PECVD-WNx
다음, 상기 구조의 전표면에 Al막을 형성하여 상기 비아콘택홀(20)을 매립하는 제2금속배선(26)을 형성하게 된다.(제2b도 참조)Next, an Al film is formed on the entire surface of the structure to form a second metal wiring 26 to fill the via contact hole 20 (see also FIG. 2b).
제3a도 내지 제3b도 는 본 발명의 다른 실시예에 따른 반도체 소자의 제조 공정 단면도이다.3A to 3B are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
먼저, 제1금속배선(12) 상측에 형성되는 비아콘택홀(20)의 형성공정 까지는 제2도에 도시된 제조공정과 동일하므로 생략하기로 한다.First, the process of forming the
다음, SOG막(16) 측면의 리세스 부분을 PECVD법에 의한 W층(30)을 100 ~ 500Å 두께로 형성하여 메운다.Next, the recessed portion of the side surface of the
이 때. 상기 PECVD ~ W층(30)은 300 ~ 400℃ 온도범위에서 증착한다.At this time. The PECVD ~
그 다음, 상기 구조의 전표면에 CVD법에 의한 W층(32)을 1000 ~ 2500Å 두께로 증착하여 상기 비아콘택홀(20)을 매립한다.Next, the
이 때. 상기 CVD ~ W층(32)은 WF6를 원료로 수소 환원법을 사용하여 증착하여도 무방하다.At this time. The CVD to W layers 32 may be deposited using WF 6 as a raw material using a hydrogen reduction method.
다음, 상기 구조의 전표면에 PECVD법에 의한 WNx막(34)을 형성한 다음, 비정질 구조를 갖도록 질소/수소의 유량비를 0.1 ~ 1.2 갖는 범위에서 실시하여 10 ~ 100Å 두께로 형성한다.Next, after forming the
여기서, 상기 W층(30,32,34)은 인-시튜(in-situ)로 형성한다.In this case, the W layers 30, 32, and 34 are formed in-situ.
이 때, 상기 PECVD - WNx막(34)은 대기 노출에 의한 텅스텐의 산화를 방지하게 된다.(제3a도 참조)At this time, the PECVD-
그 다음, 상기 구조의 전면에 Al층을 스퍼터(sputter)법으로 형성하여 제2금속배선(36)을 형성하여 본 발명의 제조공정을 완료한다.(제3b도 참조)Then, an Al layer is formed on the entire surface of the structure by a sputtering method to form a
상기한 바와 같이 본 발명에 따르면, 비아콘택홀을 형성 후 감광막 제거 과정에서 생기는 SOG막의 리세스된 부분을 PECVD법으로 W층을 형성하여 리세스된 부분을 매립하고, 그 상부에 WNx층을 형성한 다음 Al층을 증착하여 비아콘택홀을 매립하거나, 비아콘택홀을 형성 후 PECVD법으로 W층을 형성하고 CVD법으로 W층을 형성하여 비아콘택홀을 매립한 다음 AI층을 형성하여 제2금속층을 형성함으로써 비아콘택홀의 매립실패에 의한 불량률을 감소시켜 반도체 소자의 신뢰성을 향상시키는 효과가 있다.As described above, according to the present invention, a W layer is formed by PECVD to form a recessed portion of the SOG film generated during the photoresist film removal process after the via contact hole is formed, and the recessed portion is buried, and a WNx layer is formed thereon. After depositing an Al layer to fill a via contact hole, or after forming a via contact hole, a W layer is formed by PECVD and a W layer is formed by CVD to fill a via contact hole, and then an AI layer is formed. The formation of the metal layer reduces the defect rate caused by the buried failure of the via contact hole, thereby improving the reliability of the semiconductor device.
Claims (15)
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