JP2000323479A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent migration of copper in a copper wiring from an interface between a barrier metal layer and a nitride layer to an interlayer insulating film and thus to prevent the occurrence of a leak current and a short circuit between neighboring wirings, by simply covering the upper surface of the copper wiring formed in a wiring trench via a barrier metal layer with a nitride film. SOLUTION: A semiconductor device having a wiring 24 formed in a recessed portion (wiring trench) 22 formed in an interlayer insulating film 21 has a first barrier layer 23 covering the wiring 24 from under the wiring 24, and a second barrier layer 25 covering the wiring 24 from over the wiring 24, wherein the first barrier layer 23 overlaps the second barrier layer 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device using copper or a copper alloy as a conductor and a method for manufacturing the same.

[0002]

2. Description of the Related Art With miniaturization of semiconductor devices, it is necessary to miniaturize wirings and to reduce wiring pitches. At the same time, with the demand for lower power consumption and higher speed, it has become necessary to lower the dielectric constant of the interlayer insulating film and lower the resistance of the wiring. In particular, in a logic device, a rise in resistance and an increase in wiring capacitance due to fine wiring lead to a decrease in operation speed of the device. Therefore, a fine multilayer wiring using a low dielectric constant film and an interlayer insulating film is required.

The miniaturization of the wiring width and the reduction of the pitch not only increase the aspect ratio of the wiring itself, but also increase the aspect ratio of the interval between wirings (space portion of line and space). In addition, a burden is imposed on a technique for forming vertically elongated fine wiring, a technique for embedding fine wiring between layers with an interlayer insulating film, and the like, which complicates the process and increases the number of processes.

In a damascene process in which a connection hole (for example, a via hole) and a wiring groove are simultaneously filled by reflow sputtering or plating of a metal (aluminum, copper, or the like) and the surface metal is polished by chemical mechanical polishing (hereinafter referred to as CMP), It is not necessary to form a metal wiring having a high aspect ratio by etching or to bury a gap between the wirings with an interlayer insulating film, so that the number of processes can be greatly reduced. This process greatly contributes to a reduction in the total manufacturing cost as the aspect ratio of the wiring increases and the total number of wirings increases.

Conventionally, aluminum and aluminum alloy have been used as conductive materials in LSI wiring.
In recent years, copper alloys have been used as conductive materials in order to achieve higher speed and lower power consumption with the improvement in the degree of integration of semiconductor integrated circuits. Further, a manufacturing method using copper as a wiring material is not to cover the insulating film after processing the wiring material by conventional etching, but to form an insulating film first and then embed a conductor in a part thereof. A damascene method has been developed in which grooves and holes are formed and a wiring material made of a conductor is embedded therein.

Next, a method of forming a wiring by the damascene method will be described with reference to the manufacturing process of FIG.

[0007] As shown in FIG. 10A, a second insulating layer 112 is formed on the first insulating layer 111. The first insulating layer 111 and the second insulating layer 112 may be formed using different insulating materials or may be formed using the same insulating material.

Next, as shown in FIG. 10B, a groove 113 for forming a wiring or an electrode is formed in the second insulating layer 112 by a usual lithography technique and an etching technique.

[0009] Subsequently, as shown in FIG. 10 C, a barrier metal layer 114 is formed on the inner surface of the groove 113, and copper is buried as a conductor. Then, the groove 11
3 is removed by chemical mechanical polishing (hereinafter referred to as CMP).
hanical polishing (abbreviation), and the surface is flattened. Thus, the wiring 115 made of copper is formed inside the groove 113 via the barrier metal layer 114. In this figure, the barrier metal layer 114 is diffused (moved) into the first insulating layer 111 and the second insulating layer 112.
At present, tantalum, a tantalum compound, or a tantalum alloy is often used. As other materials, titanium, a titanium alloy, tungsten, or the like is used.

[0010] Thereafter, as shown in FIG. 10 (4), a second insulating layer 112 is formed so as to cover the upper portion of the wiring 115.
A nitride film (for example, a silicon nitride film) 116 is formed thereon. This nitride film 116 is for preventing copper in the wiring 115 from diffusing to the upper part.

Although FIG. 10 shows a case where the wiring 115 made of copper is formed in the groove 113, a connection hole for the lower wiring is formed simultaneously with the groove for embedding the upper wiring, and the groove and the connection hole are formed. At the same time, even in the dual damascene method of embedding a conductor, the barrier metal layer formed in the trench and the nitride film formed on the wiring have the same configuration.

On the other hand, problems have been pointed out for using copper as a conductive material. That is, since copper is not a material that easily forms an oxide with various materials like aluminum, copper easily moves (diffuses) in the interlayer insulating film and the wiring insulating film. Therefore, in a semiconductor device, formation of a so-called barrier layer for preventing movement of copper is an essential technology in order to realize copper wiring. Therefore, it is necessary to surely prevent the movement of copper by the barrier layer.

[0013]

However, in the wiring structure described in the prior art, the contact area between the barrier metal layer formed on the inner surface of the wiring groove and the nitride film formed on the upper surface of the copper wiring is small, Since the upper surface of the wiring and the contact surface between the barrier metal layer and the nitride film are substantially on the same plane, for example, when the barrier metal layer and the nitride film are peeled off due to the stress of the copper wiring, Copper of the copper wiring moves from the interface between the barrier metal layer and the nitride film toward the silicon oxide film. This is because copper is a very mobile substance. This causes a leak current, and in the worst case, causes a short circuit with an adjacent copper wiring.

It is also reported that copper has an extremely large interface at which two kinds of materials are laminated and a very large surface diffusion of various materials. For example, 1998 International Conference on S
olidState Devices and Materials U.
Kim et al. Report anomalous diffusion induced by defects during processing at the interface between the BCB and the silicon nitride film. As a result, it has been found that it is not sufficient to pay attention only to thermal diffusion in copper wiring.

[0015]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

In a semiconductor device having a wiring in a recess formed in an interlayer insulating film, a first barrier layer covering the wiring from a lower side of the wiring and a wiring from an upper side of the wiring are formed by the first barrier layer. A second barrier layer for coating,
The first barrier layer and the second barrier layer overlap each other to cover the wiring.

In the above-described semiconductor device, the semiconductor device includes a first barrier layer covering the wiring from the lower side of the wiring, and a second barrier layer covering the wiring from the upper side of the wiring. Since the wiring is covered by overlapping with the second barrier layer, even if stress of the wiring is applied to the first barrier layer and the second barrier layer, the first barrier layer and the second barrier layer are applied. Due to the overlapping of the layers, even if one of the barrier layers is displaced, the first barrier layer and the second barrier layer maintain contact at the overlapping portion. That is, since the first barrier layer and the second barrier layer overlap, the adhesion between the barrier layers is enhanced. Therefore, the first barrier layer and the second barrier layer
And the metal constituting the wiring does not move (or diffuse) to the outside from the barrier layer. Therefore, even if the wiring is formed of copper or a copper alloy and the silicon oxide interlayer insulating film is formed around the wiring, copper in the wiring, for example, ionized copper does not move into the interlayer insulating film.

According to the first method of manufacturing a semiconductor device, after forming a concave portion in an insulating film, a first barrier layer is formed on the inner surface of the concave portion, and a conductor is formed by embedding a conductor inside the concave portion. Removing the insulating film around the wiring to project the wiring and the first barrier layer from the surface of the insulating film; and covering the upper side of the wiring and forming the first barrier layer on the side of the wiring. Forming a second barrier layer that overlaps and covers the wiring together with the first barrier layer.

In the first method of manufacturing a semiconductor device, a step of forming a wiring by forming a first barrier layer on an inner surface of a concave portion formed in an insulating film and embedding a conductor in the concave portion; Removing the insulating film around the substrate and projecting the wiring and the first barrier layer from the surface of the insulating film;
A second cover that covers an upper side of the wiring and overlaps the first barrier layer on the side of the wiring to cover the wiring together with the first barrier layer;
The wiring is covered with the first barrier layer and the second barrier layer.

Therefore, even if stress of the wiring is applied to the first barrier layer and the second barrier layer, the first barrier layer and the second barrier layer are overlapped with each other.
Even if one of the barrier layers is displaced, the contact between the first barrier layer and the second barrier layer is maintained at the overlapping portion. That is, by forming the first barrier layer and the second barrier layer so as to overlap with each other, the adhesion between the barrier layers is enhanced. Therefore, the first
Since the barrier layer and the second barrier layer do not separate from each other, there is no gap between them and the metal constituting the wiring does not move (or diffuse) to the outside. Therefore, even if the wiring is formed of copper or a copper alloy, copper in the wiring does not move into the insulating film.

According to the second method of manufacturing a semiconductor device, after forming a recess in an insulating film, a first barrier layer is formed on the inner surface of the recess and a conductor is formed by embedding a conductor inside the recess. Forming a groove by removing an insulating film near an upper portion of the first barrier layer; and forming a second barrier layer so as to cover an upper side of the wiring and fill the groove. Manufacturing method.

In the second method for manufacturing a semiconductor device, a step of forming a first barrier layer on the inner surface of the concave portion formed in the insulating film and forming a wiring by embedding a conductor inside the concave portion; The method includes the steps of forming a groove by removing the insulating film near the upper part of the first barrier layer, and forming the second barrier layer so as to cover the upper side of the wiring and fill the groove. , The wiring is connected to the first barrier layer and the second barrier layer.
With a barrier layer.

Therefore, even if stress of the wiring is applied to the first barrier layer and the second barrier layer, the first barrier layer and the second barrier layer are overlapped with each other.
Even if one of the barrier layers is displaced, the contact between the first barrier layer and the second barrier layer is maintained at the overlapping portion. That is, by forming the first barrier layer and the second barrier layer so as to overlap each other, the adhesion between the barrier layers is strengthened. Therefore, since the first barrier layer and the second barrier layer do not separate from each other, a gap does not open between the first barrier layer and the second barrier layer, and the metal forming the wiring does not move (or diffuse) to the outside. Therefore, even if the wiring is formed of copper or a copper alloy, copper in the wiring does not move into the insulating film.

According to the third method of manufacturing a semiconductor device, after forming a concave portion in an insulating film, a first barrier layer is formed on the inner surface of the concave portion, and a conductor is formed by embedding a conductor inside the concave portion. Removing the upper part of the wiring so as to be lower than the surface of the insulating film; and covering the upper side of the wiring and overlapping the first barrier layer at the upper part of the wiring to cover the wiring together with the first barrier layer. Forming a second barrier layer.

In the third method of manufacturing a semiconductor device, a step of forming a wiring by forming a first barrier layer on the inner surface of the concave portion formed in the insulating film and embedding a conductor in the concave portion; Removing the upper part of the wiring so as to be lower than the film surface; and covering the upper side of the wiring and overlapping the first barrier layer with the upper part of the wiring to form the first wiring.
Forming a second barrier layer covering the barrier layer together with the barrier layer, so that the wiring is covered with the first barrier layer and the second barrier layer.

Therefore, even if the stress of the wiring is applied to the first barrier layer and the second barrier layer, the first barrier layer and the second barrier layer are overlapped with each other.
Even if one of the barrier layers is displaced, the contact between the first barrier layer and the second barrier layer is maintained at the overlapping portion. That is, by forming the first barrier layer and the second barrier layer so as to overlap each other, the adhesion between the barrier layers is strengthened. Therefore, since the first barrier layer and the second barrier layer do not separate from each other, a gap does not open between the first barrier layer and the second barrier layer, and the metal forming the wiring does not move (or diffuse) to the outside. Therefore, even if the wiring is formed of copper or a copper alloy, copper in the wiring does not move into the insulating film.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment According to a Semiconductor Device of the Present Invention
Will be described with reference to the schematic cross-sectional view of FIG.

As shown in FIG. 1, a concave portion (hereinafter referred to as a wiring groove) 22 is formed in an interlayer insulating film 21 constituting a part of a semiconductor device. The interlayer insulating film 21
Is formed of, for example, silicon oxide. In the wiring groove 22, a wiring 24 is formed so as to protrude from the upper surface of the interlayer insulating film 21 via a first barrier layer 23. Thus, the first barrier layer 23 covers the wiring 24 from below. The first barrier layer 23 is formed of, for example, tantalum nitride or tantalum as a material having a barrier property against copper atoms and copper ions. The wiring 24 is formed of, for example, copper or a copper alloy.

Further, a second barrier layer 25 for covering the wiring 24 from above is formed so as to overlap the first barrier layer 23 on the side (side surface) of the wiring 24. The second barrier layer 25 is formed of, for example, silicon nitride as a material having a barrier property against copper atoms and copper ions. Thus, the wiring 2
4 is covered with a first barrier layer 23 and a second barrier layer 25.

Although not shown, the interlayer insulating film 21 is, for example, a transistor formed on a semiconductor substrate,
Capacitance, may cover the semiconductor elements and wiring such as resistance, or may be for planarization,
Alternatively, it may cover the wiring layer. That is, it is an interlayer insulating film used in a normal semiconductor device.

In the first embodiment, the first barrier layer 23 covering the wiring 24 from the lower side of the wiring 24
And a second barrier layer 25 that covers the wiring 24 from above the wiring 24. The first barrier layer 23 and the second barrier layer 25 overlap each other on the side of the wiring 24 and Since the first barrier layer 23 and the second barrier layer 25 are covered with each other, the first barrier layer 23 and the second barrier layer 25 overlap even when the stress of the wiring 24 is applied to the first barrier layer 23 and the second barrier layer 25. Therefore, even if one of the barrier layers (for example, the second barrier layer 25) is displaced, the first barrier layer 23 and the second barrier layer 23 are overlapped with each other.
The contact with the barrier layer 25 is maintained.

That is, since the first barrier layer 23 and the second barrier layer 25 overlap, the adhesion between the barrier layers is enhanced. Therefore, the first barrier layer 2
3 and the second barrier layer 25 are separated from each other,
4 does not move (or diffuse) toward the outside, that is, in the direction of the interlayer insulating film 21. That is,
Even if the stress of the wiring 24 acts, the state where the wiring 24 is covered with the first barrier layer 23 and the second barrier layer 25 does not change. Therefore, the copper constituting the wiring 24 does not ionize and move into the interlayer insulating film 21 around the wiring 24, for example.

Next, a second embodiment according to the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2, a concave portion (hereinafter referred to as a wiring groove) 22 is formed in an interlayer insulating film 21 constituting a part of the semiconductor device. The interlayer insulating film 21
Is formed of, for example, silicon oxide. In this wiring groove 22, a wiring 24 is formed with a first barrier layer 23 interposed therebetween. Thus, the first barrier layer 23 covers the wiring 24 from below. First barrier layer 23
Is formed of a material having a barrier property against copper atoms and copper ions, for example, tantalum nitride or tantalum. The wiring 24 is formed of, for example, copper or a copper alloy.

Further, a groove 26 is formed in the interlayer insulating film 21 above the first barrier layer 23, and a second barrier is formed so as to fill the groove 26 and cover the wiring 24 from above. Layer 25 is formed. Since the second barrier layer 25 is formed as described above, the second barrier layer 25 is formed by the first barrier layer 23 and the wiring 24.
Are in a state of being overlapped on the side portions (side surfaces). The second barrier layer 25 is formed of, for example, silicon nitride as a material having a barrier property against copper atoms and copper ions. Or silicon carbide, tantalum,
It is also possible to use a tantalum alloy, tantalum nitride, or the like. In this manner, the wiring 24 is connected to the first barrier layer 23
And the second barrier layer 25.

In the second embodiment, the first barrier layer 23 and the second barrier layer 2 are placed such that the first barrier layer 23 and the second barrier layer 25 overlap on the side of the wiring 24.
5 covers the wiring 24, similarly to the first embodiment, it is assumed that the copper constituting the wiring 24 is ionized and moves into the interlayer insulating film 21 around the wiring 24, for example. , The first barrier layer 23 and the second barrier layer 25 can be used.

Next, a third embodiment of the semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG. In FIG. 3, the same reference numerals are given to the same components as those in FIG.

As shown in FIG. 3, a concave portion (hereinafter, referred to as a wiring groove) 22 is formed in an interlayer insulating film 21 constituting a part of the semiconductor device. The interlayer insulating film 21
Is formed of, for example, silicon oxide. In this wiring groove 22, a wiring 24 is formed with a first barrier layer 23 interposed therebetween. Thus, the first barrier layer 23 covers the wiring 24 from below. First barrier layer 23
Is formed of a material having a barrier property against copper atoms and copper ions, for example, tantalum nitride or tantalum. The wiring 24 is formed of, for example, copper or a copper alloy.

Further, a groove 26 is formed in the interlayer insulating film 21 near the upper portion of the first barrier layer 23.
And a second barrier layer 27 is formed so as to cover the wiring 24 from above. Since the second barrier layer 27 is thus formed, the second barrier layer 27 overlaps the first barrier layer 23 on the side (side surface) of the wiring 24. The second barrier layer 27 is formed of a low dielectric constant organic film such as an aryl ether, for example, as a material having a barrier property against copper atoms and copper ions. Thus, the wiring 24 is covered with the first barrier layer 23 and the second barrier layer 27.

The low dielectric constant organic film can be used for the second barrier layer because the diffusion coefficient of copper with respect to the low dielectric constant organic film is small.

In the third embodiment, the first barrier layer 23 and the second barrier layer 2 are placed such that the first barrier layer 23 and the second barrier layer 27
7, the copper forming the wiring 24 is, for example, ionized and moved into the interlayer insulating film 21 around the wiring 24 in the same manner as in the first embodiment. , The first barrier layer 23 and the second barrier layer 27. Further, the second barrier layer 27 can be used as an interlayer insulating film between the wiring 24 and a wiring (not shown) formed thereon.

Next, a fourth embodiment according to the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG. In FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 4, a concave portion (hereinafter referred to as a wiring groove) 22 is formed in an interlayer insulating film 21 constituting a part of the semiconductor device. The interlayer insulating film 21
Is formed of, for example, silicon oxide. A first barrier layer 23 is formed on the inner wall (including the bottom) of the wiring groove 22. The first barrier layer 23 is formed of, for example, tantalum nitride or tantalum as a material having a barrier property against copper atoms and copper ions. Further, in the wiring groove 22, a wiring 24 is formed so as to be recessed from the upper surface of the interlayer insulating film 21 via the first barrier layer 23. The wiring 24 is formed of, for example, copper or a copper alloy.

Accordingly, the first barrier layer 23 is also formed on the side of the wiring 24 in the wiring groove 22, and the lower side of the wiring 24 is covered with the first barrier layer 23.

Further, a second barrier layer 25 for covering the wiring 24 from above is formed so as to overlap the first barrier layer 23 on the side wall of the wiring groove 22.
The second barrier layer 25 is formed of, for example, silicon nitride as a material having a barrier property against copper atoms and copper ions. In this manner, the wiring 24 is covered with the first barrier layer 23 and the second barrier layer 25.

Although not shown, the interlayer insulating film 21 is, for example, a transistor formed on a semiconductor substrate,
Capacitance, may cover the semiconductor elements and wiring such as resistance, or may be for planarization,
Alternatively, it may cover the wiring layer. That is, it is an interlayer insulating film used in a normal semiconductor device.

In the fourth embodiment, the first barrier layer 23 covering the wiring 24 from the lower side of the wiring 24
And a second barrier layer 25 covering the wiring 24 from the upper side of the wiring 24, wherein the first barrier layer 23 and the second barrier layer 25 overlap on the side of the wiring groove 22. Since the wiring 24 is covered, even if stress of the wiring 24 is applied to the first barrier layer 23 and the second barrier layer 25, the first barrier layer 23 and the second barrier layer 25
Are overlapped with each other, so that even if one of the barrier layers (for example, the second barrier layer 25) is displaced, the first barrier layer 23 and the second barrier layer 23
Is kept in contact with the barrier layer 25.

That is, since the first barrier layer 23 and the second barrier layer 25 overlap, the adhesion between the barrier layers is strengthened. Therefore, the first barrier layer 2
3 and the second barrier layer 25 are separated from each other,
4 does not move (or diffuse) toward the outside, that is, in the direction of the interlayer insulating film 21. That is,
Even if the stress of the wiring 24 acts, the state where the wiring 24 is covered with the first barrier layer 23 and the second barrier layer 25 does not change. Therefore, the copper constituting the wiring 24 does not ionize and move into the interlayer insulating film 21 around the wiring 24, for example.

Next, an embodiment according to the first manufacturing method of the present invention will be described with reference to a manufacturing process diagram of FIG. FIG.
Here, as an example, a method of manufacturing the semiconductor device described with reference to FIG. 1 will be described, and parts that are the same as the constituent parts illustrated in FIG.

As shown in FIG. 5A, a semiconductor element (for example, a transistor, a capacitor, a resistor, etc.) is formed on a semiconductor substrate (not shown), and a lower layer wiring, a wiring pattern and the like are formed thereon. I have. On such a semiconductor substrate, an insulating film 11 covering these elements, wirings and the like is formed. On the insulating film 11, an interlayer insulating film 21 is formed. The interlayer insulating film 21 is formed of a laminated film of a low dielectric constant organic film such as an aryl ether and a silicon oxide film. Alternatively, a laminated film of a fluororesin film and a silicon oxide film, a fluorinated silicon oxide film, an organic SOG film, an inorganic S film
It is formed of a so-called low dielectric constant film such as an OG film. In particular, for devices with design rules of 0.13 μm generation or later,
It is necessary to include a low dielectric constant film.

After that, a concave portion (hereinafter, referred to as a wiring groove) 22 is formed in the interlayer insulating film 21 by a generally known damascene method.
Is formed of, for example, tantalum nitride or tantalum as a material having a barrier property against copper atoms and copper ions. Further, after a copper seed layer is formed on the inner surface of the wiring groove 22 via the first barrier layer 23, the inside of the wiring groove 22 is filled with a conductor (for example, copper) by an electrolytic plating method or the like. Thereafter, the excess copper and the first barrier layer 23 on the interlayer insulating film 21 are removed by, for example, CMP, and the first barrier layer 2 is formed inside the wiring groove 22.
Then, a wiring 24 made of copper is formed through the wiring 3.

Next, as shown in FIG.
The wiring 24 and the first barrier layer 23 protrude from the surface of the interlayer insulating film 21 by removing the interlayer insulating film 21 around 4 by etching. Therefore, the first barrier layer 2
Reference numeral 3 denotes a state in which the wiring 24 is covered from below.

In the above etching, when the interlayer insulating film 21 is a silicon oxide film, for example, the concentration is 0.1% to 1.0%.
Using a hydrofluoric acid aqueous solution of, for example, a 0.5% hydrofluoric acid aqueous solution as an example, is removed by wet etching.
It is not practical to perform wet etching using a hydrofluoric acid aqueous solution having a concentration of less than 0.1% because the etching rate becomes slow. In wet etching using a hydrofluoric acid aqueous solution exceeding 1.0%, a metal portion is also etched. It is not preferable because it is done. When the interlayer insulating film 21 is a low dielectric constant organic film such as an aryl ether, it is removed by hydrogen plasma etching or nitrogen plasma etching. Note that using oxygen plasma etching is not preferable because copper in the wiring 24 is oxidized and causes a defect. From the viewpoint of preventing the wiring 24 from being oxidized, it is desirable to perform this etching and the subsequent formation of the second barrier layer in a non-oxidizing atmosphere. That is, it is desirable to perform a so-called in situ treatment.

The etching of the interlayer insulating film 21 can be performed by dry etching using a fluorocarbon-based gas. In this case, the upper part of the first barrier layer 23 may be etched. Note that even if the upper portion of the first barrier layer 23 is etched, the amount of overlap of the subsequently formed second barrier layer with the first barrier layer 23 can be sufficiently ensured, that is, after the etching, The first barrier layer 2 from the surface of the interlayer insulating film 21
It is necessary to perform the above-mentioned etching so that 3 remains at a height of 30 nm or more.

It is preferable that the height of the step between the interlayer insulating film 21 and the first barrier layer 23 be at least 30 nm or more by etching the interlayer insulating film 21. If the step is 30 nm or less, the overlapping portion with the second barrier layer to be formed later is reduced, and it is difficult to secure sufficient barrier properties. It is because it becomes.

Next, as shown in FIG. 5C, a second barrier layer 25 is formed on the interlayer insulating film 21 so as to cover the wiring 24. The second barrier layer 25 is formed of a material having a barrier property against copper atoms and copper ions, for example, an insulating film such as silicon nitride or silicon hydride carbon. The manufacturing method is CVD
The method is preferred. As another film formation method, a film formation method such as sputtering or a sol-gel method can be used.
When the film is formed by the CVD method, it is preferable that the interlayer insulating film 21 is subjected to etching and in situ processing. For example, after etching a silicon oxide film with a diluted hydrofluoric acid aqueous solution, etching using hydrogen
Etching is performed on the order of 20 nm, and thereafter, chemical vapor deposition (hereinafter referred to as CVD) is performed continuously.
A second barrier layer 25 made of a silicon nitride film is formed by an apour deposition method.

When the interlayer insulating film 21 is an organic film, it is etched by about 10 nm to 100 nm by etching using hydrogen plasma or nitrogen plasma.
The second barrier layer 25 is formed of a silicon nitride film by a VD method. At this time, the silicon nitride film has a thickness of 20 nm to 100 nm.
It is desirable to form it to a thickness of about nm. If it is less than 20 nm, sufficient barrier properties cannot be obtained. On the other hand, 100 nm
If the thickness exceeds, the capacitance between wirings becomes large, which is not preferable. As described above, the oxide film (copper oxide film) on the surface of the wiring 24 is obtained by etching using the hydrogen plasma.
And at the same time, the surface of the wiring 24 is cleaned, so that the adhesion to the second barrier layer 25 made of a silicon nitride film is improved.

When the second barrier layer 25 made of a silicon nitride film is formed by the CVD method, the thickness of the side wall of the wiring 24 may be smaller than the thickness of the wiring 24. preferable. The reason is that when a silicon nitride film is formed between wirings, the capacitance between the wirings increases, so that the increase in the capacitance between the wirings is suppressed as much as possible. Therefore, CVD
In the method, a high-density plasma CVD apparatus is preferably used for film formation as a directional CVD method. Alternatively, film formation may be performed using a parallel plate type plasma CVD apparatus. As the film forming conditions, the step coverage is 30.
% Or less. Parallel plate type plasma CV
As an example of the film forming conditions when the D apparatus is used,
The pressure of the film formation atmosphere is 1.03 kPa and the film formation temperature is 400
C. and the process gas ratio are set to about monosilane [SiH ₄ ]: ammonia (NH ₃ ) = 3: 1. Furthermore, CV
Immediately before D, a plasma treatment including at least one of hydrogen plasma and nitrogen plasma is preferably performed. As an example of the film forming conditions when a high-density plasma CVD apparatus is used, the pressure of the film forming atmosphere is 1 Pa or less, the film forming temperature is 200 ° C. to 400 ° C., and the process gas ratio is monosilane [SiH ₄ ]: nitrogen ( N ₂₎ = 3: 1.5~
Set to about 5.

When the second barrier layer 25 is formed as described above, the second barrier layer 25 covers the upper side of the wiring 24 and overlaps the first barrier layer 23 on the side of the wiring 24. The wiring 24 is covered together with the first barrier layer 23.

Thereafter, as shown in FIG.
An interlayer insulating film 31 is formed on the barrier layer 25 of FIG. The interlayer insulating film 31 preferably includes a low dielectric constant film. In the present invention, the aryl ether is used.
G, inorganic SOG, fluororesin, xerogel, etc. can also be used.

Although not shown, a connection hole is formed at a predetermined position of the insulating film 11 and a plug is formed therein. When the wiring 24 is formed by the dual damascene method, a connection hole is formed at a predetermined position of the insulating film 11 by the dual damascene method, and when the wiring 24 is formed, the wiring 24 is formed inside the connection hole. A plug is formed by embedding a conductor to be formed, for example, copper.

In the first manufacturing method described with reference to FIG. 5, after forming the wiring 24 made of copper through the first barrier layer 23 inside the wiring groove 22, the interlayer insulating film 21 around the wiring 24 is formed. Is removed, and the wiring 24 and the first barrier layer 23 are made to protrude from the surface of the interlayer insulating film 21. Thereafter, the wiring 24 and the first barrier layer 23 are covered with the side of the wiring 24 while being covered. Wiring 24 to the first barrier layer 2
Since the second barrier layer 25 is formed so as to cover the first barrier layer 23 and the second barrier layer 2,
And 5.

Therefore, even if the stress of the wiring 24 is applied to the first barrier layer 23 and the second barrier layer 25,
Since the first barrier layer 23 and the second barrier layer 25 overlap each other, even if one of the barrier layers is displaced, the first barrier layer 23 and the second barrier layer 25 overlap at the overlapping portion. Contact with layer 25 is maintained. That is, by forming the first barrier layer 23 and the second barrier layer 25 so as to overlap with each other, the adhesion between the barrier layers is strengthened. Therefore, since the first barrier layer 23 and the second barrier layer 25 do not separate from each other, there is no gap between them, and copper constituting the wiring 24 does not move (or diffuse) to the outside. Therefore, even if the wiring 24 is formed of copper (or a copper alloy) as described above and a silicon oxide film is used for the interlayer insulating film 21, the copper in the wiring 24, for example, ionized copper, may be formed in the interlayer insulating film 21. Never move on.

In the first manufacturing method, the interlayer insulating film 21 has a laminated structure of a low dielectric constant organic film and a silicon oxide film, and the upper portion of the interlayer insulating film 21 is formed of a silicon oxide film; The thickness of the silicon oxide film is 30 nm
In the case of about 100 nm, the silicon oxide film portion of the interlayer insulating film 21 may be entirely removed in the step of removing the upper part of the interlayer insulating film 21 in order to project the wiring 24 and the first barrier layer 23. .

Next, a first embodiment according to the second manufacturing method of the present invention will be described with reference to a manufacturing process diagram of FIG. FIG. 6 shows, by way of example, the method of manufacturing the semiconductor device described with reference to FIG. 2, and the same components as those shown in FIG.

As shown in FIG. 6A, a recess (hereinafter referred to as a wiring) is formed in the interlayer insulating film 21 by a method similar to that described with reference to FIG. 5A, that is, a generally known damascene method. After forming a groove 22), a first barrier layer 23 is formed on the inner surface of the wiring groove 22 as a material having a barrier property against copper atoms and copper ions.
For example, it is formed of tantalum nitride or tantalum. Further, after a copper seed layer is formed on the inner surface of the wiring groove 22 via the first barrier layer 23, the inside of the wiring groove 22 is filled with a conductor (for example, copper) by an electrolytic plating method or the like. Thereafter, excess copper and the first barrier layer 23 on the interlayer insulating film 21 are removed by, for example, CMP, and a wiring 24 made of copper is formed inside the wiring groove 22 via the first barrier layer 23. .

Next, as shown in FIG. 6B, the interlayer insulating film 21 is etched. The etching conditions at that time are set so that the interlayer insulating film 21 on the side circumference of the first barrier layer 23 is
Are selected so that the is etched. For example, when the interlayer insulating film 21 is a silicon oxide film containing 10% to 20% carbon, trifluoromethane (CHF ₃ ) [supply flow rate is set to, for example, 5 sccm] and argon ( Ar)
Using, for example, a supply flow rate of 20 sccm and oxygen (O ₂ ) [a supply flow rate of 5 sccm], for example, the pressure of the etching atmosphere is set to 5 Pa, the applied power is set to 600 W, and the interlayer insulating film is formed. 21 may be etched back entirely. Etching back under such conditions forms a groove 26 in the interlayer insulating film 21 near the upper portion of the first barrier layer 23.

Thereafter, as shown in FIG. 6C, a second barrier layer 25 is formed so as to fill the groove 26 and cover the wiring 24 from above. Since the second barrier layer 25 is formed in this manner, the second barrier layer 25 overlaps the first barrier layer 23 on the side (side surface) of the wiring 24. The second barrier layer 25 is formed of a material having a barrier property against copper atoms and copper ions, for example, silicon nitride. In this manner, the wiring 24 is covered with the first barrier layer 23 and the second barrier layer 25.

In the first embodiment according to the second manufacturing method described with reference to FIG. 6, a wiring 24 is formed inside a wiring groove 22 formed in an interlayer insulating film 21 via a first barrier layer 23. Then, after removing the interlayer insulating film 21 near the upper portion of the first barrier layer 23 to form a groove 26, the second barrier layer 25 is formed so as to cover the upper side of the wiring 24 and fill the groove 26. As a result, the wiring 24 is covered with the first barrier layer 23 and the second barrier layer 25.

Therefore, even if the stress of the wiring 24 is applied to the first barrier layer 23 and the second barrier layer 25,
Since the first barrier layer 23 and the second barrier layer 25 overlap each other, even if one of the barrier layers is displaced, the first barrier layer 23 and the second barrier layer 25 overlap at the overlapping portion. Contact with layer 25 is maintained. That is, by forming the first barrier layer 23 and the second barrier layer 25 so as to overlap with each other, the adhesion between the barrier layers is strengthened. Therefore, since the first barrier layer 23 and the second barrier layer 25 do not separate from each other, there is no gap between them, and copper constituting the wiring 24 does not move (or diffuse) to the outside. Therefore, even if the wiring 24 is formed of copper (or a copper alloy) as described above and a silicon oxide film is used for the interlayer insulating film 21, the copper in the wiring 24, for example, ionized copper, may be formed in the interlayer insulating film 21. Never move on.

Next, a second embodiment according to the second manufacturing method of the present invention will be described with reference to the manufacturing process diagram of FIG. In FIG. 7, as an example, the method of manufacturing the semiconductor device described with reference to FIG. 3 is shown, and parts that are the same as the constituent parts shown in FIG.

A recess (hereinafter referred to as a wiring groove) 22 is formed in the interlayer insulating film 21 by the same method as described with reference to FIGS. 6A and 6B, and the inside of the wiring groove 22 is formed. Then, a wiring 24 made of copper is formed via a first barrier layer 23. Next, the interlayer insulating film 21 is etched back to form a groove 26 in the interlayer insulating film 21 above the first barrier layer 23.

Thereafter, as shown in FIG. 7, a second barrier layer 27 is formed on the interlayer insulating film 21 so as to fill the trench 26 and cover the wiring 24 from above. The second barrier layer 27 is formed of a material having a barrier property against copper atoms and copper ions, for example, a low dielectric constant organic film such as an aryl ether. In this way, the second barrier layer 27 is formed so as to overlap the first barrier layer 23 on the side (side surface) of the wiring 24.

Therefore, the same function and effect as those of the first embodiment can be obtained. That is, even if the wiring 24 is formed of copper (or copper alloy) as described above and the silicon oxide film is used for the interlayer insulating film 21, the first barrier layer 23 and the second barrier layer 17 , The copper in the wiring 24, for example, ionized copper does not move into the interlayer insulating film 21.

Next, an embodiment according to the third manufacturing method of the present invention will be described with reference to a manufacturing process diagram of FIG. FIG.
Here, as an example, a method of manufacturing the semiconductor device described with reference to FIG. 4 will be described, and parts that are the same as the constituent parts illustrated in FIG.

As shown in FIG. 8A, a semiconductor element (for example, a transistor, a capacitor, a resistor, etc.) is formed on a semiconductor substrate (not shown), and further, a lower wiring, a wiring pattern, etc. are formed. I have. On such a semiconductor substrate, an insulating film 11 covering these elements, wirings and the like is formed. On the insulating film 11, an interlayer insulating film 21 is formed. The interlayer insulating film 21 is formed of a laminated film of an organic film such as an aryl ether and a silicon oxide film. Alternatively, a low dielectric constant film such as a stacked film of a fluororesin film and a silicon oxide film, a silicon oxyfluoride film, an organic SOG film, and an inorganic SOG film is used. In particular, devices having a design rule of 0.13 μm or later need to include a low dielectric constant film.

Then, after a recess (hereinafter referred to as a groove) is formed in the interlayer insulating film 21 by a generally known damascene method, a first barrier layer 23 is formed on the inner surface of the wiring groove 22 by a copper atom. For example, tantalum nitride or tantalum is used as a material having a barrier property against copper ions. Further, after a copper seed layer is formed on the inner surface of the wiring groove 22 via the first barrier layer 23, the inside of the wiring groove 22 is filled with a conductor (for example, copper) by an electrolytic plating method or the like. Thereafter, excess copper and the first barrier layer 23 on the interlayer insulating film 21 are removed by, for example, CMP, and a wiring 24 made of copper is formed inside the wiring groove 22 via the first barrier layer 23. .

Next, as shown in FIG. 8B, only the upper part of the wiring 24 is selectively etched so that the upper surface of the wiring 24 is lower than the surface of the interlayer insulating film 21. It is preferable that the height of the step between the wiring 24 and the first barrier layer 23 be at least 30 nm or more by the above etching. If the step is 30 nm or less, the overlapping portion with the second barrier layer formed later is reduced, and it becomes difficult to secure sufficient barrier properties.
This is because the structure becomes the same as the structure of the conventional barrier layer.

Next, as shown in FIG. 8C, the surface of the wiring 24 is subjected to, for example, sputter etching or hydrogen plasma etching to remove an oxide film or the like. Subsequently, a second barrier layer 25 is formed on the interlayer insulating film 21 so as to cover the wiring 24 by, for example, sputtering. The second barrier layer 25 is formed of a material having a barrier property against copper atoms and copper ions, for example, tantalum, tantalum nitride, or the like. As another film formation method, a film formation method such as a vapor method or a CVD method can be used.

In order to prevent an oxide film from being formed on the surface of the wiring 24, it is preferable to perform the steps from the above-described sputter etching or hydrogen plasma etching to the formation of the second barrier layer 25 in a non-oxidizing atmosphere. For example, it is desirable to perform so-called in situ processing. For example, etching is performed by about 5 nm to 20 nm by sputter etching, and then the second barrier layer 25 made of a tantalum film is continuously formed by sputtering. This tantalum film is desirably formed to a thickness of about 20 nm to 75 nm. If it is less than 20 nm, sufficient barrier properties cannot be obtained. On the other hand, if the thickness exceeds 75 nm, processing takes time and the wiring resistance becomes too large.

Then, as shown in FIG. 8D, the second barrier layer 25 on the interlayer insulating film 21 is removed by, for example, CMP. As a result, the first barrier layer 23 and the second barrier layer 25 overlap in the wiring groove 22 on the upper side of the wiring 24, and the wiring 24 is formed by the first barrier layer 23 and the second barrier layer 25. The covering configuration is completed. Since the second barrier layer 25 on the interlayer insulating film 21 is removed as described above, the second barrier layer 25 can be formed of tantalum nitride or tantalum as a conductor.

Thereafter, although not shown, the second barrier layer 25 and the interlayer insulating film 2 are formed in the same manner as in the first manufacturing method.
1, an interlayer insulating film 31 is formed. The interlayer insulating film 31
It is desirable to include a low dielectric constant film. In the present invention, an aryl ether is used.
It is also possible to use G, fluororesin, xerogel, or the like.

Note that the second barrier layer 25 can be formed of the insulating film such as the silicon nitride film or silicon hydride carbon described in the first manufacturing method. The film forming method, film forming conditions, and the like in that case are the same as those described in the first manufacturing method.

In the third manufacturing method, though not shown, a connection hole is formed at a predetermined position of the insulating film 11 and a plug is formed therein. When the wiring 24 is formed by the dual damascene method, a connection hole is formed at a predetermined position of the insulating film 11 by the dual damascene method, and when the wiring 24 is formed, the wiring 24 is formed inside the connection hole. A plug is formed by embedding a conductor to be formed, for example, copper.

In the second manufacturing method described with reference to FIG. 8, after the wiring 24 made of copper is formed inside the wiring groove 22 via the first barrier layer 23, the upper part of the wiring 24 is removed. The upper surface of the wiring 24 is made lower than the surface of the interlayer insulating film 21.
4 overlaps the first barrier layer 23 on the side of
Is formed together with the first barrier layer 23, the wiring 24 is covered with the first barrier layer 23 and the second barrier layer 25.

Therefore, even if the stress of the wiring 24 is applied to the first barrier layer 23 and the second barrier layer 25,
Since the first barrier layer 23 and the second barrier layer 25 overlap each other, even if one of the barrier layers is displaced, the first barrier layer 23 and the second barrier layer 25 overlap at the overlapping portion. Contact with layer 25 is maintained. That is, by forming the first barrier layer 23 and the second barrier layer 25 so as to overlap with each other, the adhesion between the barrier layers is strengthened. Therefore, since the first barrier layer 23 and the second barrier layer 25 do not separate from each other, there is no gap between them, and copper constituting the wiring 24 does not move (or diffuse) to the outside. Therefore, even if the wiring 24 is formed of copper (or a copper alloy) as described above and a silicon oxide film is used for the interlayer insulating film 21, the copper in the wiring 24, for example, ionized copper, may be formed in the interlayer insulating film 21. Never move on.

As a fifth embodiment relating to the semiconductor device of the present invention, a structure as shown in FIG. 9 is also possible. It is described below.

As shown in FIG. 9, a concave portion (hereinafter, referred to as a wiring groove) 22 is formed in an interlayer insulating film 21 constituting a part of a semiconductor device. In this wiring groove 22,
The wiring 24 is formed so as to protrude from the upper surface of the interlayer insulating film 21 via the first barrier layer 23. Moreover, the first barrier layer 23 is also formed on the interlayer insulating film 21 around the wiring groove 22. To form in this way,
After removing a conductor (eg, copper) for forming a wiring deposited on the first barrier layer 23 by CMP, the first barrier layer 23 is patterned by a so-called masking process (lithography and etching). There is a need to. The first barrier layer 23 is made of, for example, tantalum nitride or tantalum as a material having a barrier property against copper atoms and copper ions.
The wiring 24 is formed of, for example, copper or a copper alloy.

Further, a second barrier layer 25 covering the wiring 24 from above is formed so as to overlap the first barrier layer 23 on the side (side surface) of the wiring 24. The second barrier layer 25 is formed of, for example, silicon nitride as a material having a barrier property against copper atoms and copper ions. Thus, the wiring 2
4 is covered with a first barrier layer 23 and a second barrier layer 25.

In the fifth embodiment, the same effects as those in the first embodiment can be obtained.

The first barrier layer 23 and the second barrier layer 25 or the second barrier layer 2 described in each of the above embodiments have been described.
7 must be equal to or greater than the thickness of the first barrier layer 23 on the side surface of the wiring 24 or on the side surface of the wiring groove 22;
It was confirmed by experiments of the inventor that it was sufficient if the thickness was about nm.

The first barrier layer 23 and the second barrier layer 25 or the second barrier layer 27 described in each of the above embodiments can be applied to a dual damascene structure.

Further, a configuration in which the configuration described in each of the above embodiments is turned upside down also falls within the scope of the present invention.

[0094]

As described above, according to the semiconductor device of the present invention, the lower part of the wiring is covered with the first barrier layer, and the upper part of the wiring is covered with the second barrier layer. Since the layers overlap with the second barrier layer, the stress of the wiring is applied to the first and second barrier layers, and even if one of the barrier layers is displaced, the first barrier layer is displaced. The first barrier layer and the second barrier layer do not separate from each other, and the wiring can always be covered with the first barrier layer and the second barrier layer. Therefore, even if the wiring is formed of copper or a copper alloy, copper in the wiring cannot move out of the wiring. Therefore, the occurrence of a short circuit between wirings and the generation of leakage current can be suppressed, and wiring reliability is improved.

According to the first method of manufacturing a semiconductor device according to the present invention, the insulating film around the wiring formed by embedding a conductor in the recess formed in the insulating film is removed, and the wiring is removed from the surface of the insulating film. After the second barrier layer is formed, the second barrier layer covers the upper side of the wiring and overlaps the first barrier layer at the side of the wiring to cover the wiring together with the first barrier layer. The wiring can be completely covered with the first barrier layer and the second barrier layer. Therefore, even if a stress of the wiring is applied to the first barrier layer and the second barrier layer, and either of the barrier layers is displaced, the first barrier layer and the second barrier layer are not overlapped with each other. Therefore, even if the wiring is formed of copper or a copper alloy, the movement of copper in the wiring can be prevented. Therefore, it is possible to manufacture a wiring having high wiring reliability in which occurrence of short circuit between wirings and generation of leakage current are suppressed.

According to the second method of manufacturing a semiconductor device according to the present invention, the insulating film near the upper portion of the first barrier layer in the recess formed in the insulating film is removed to form a groove, and then the wiring is formed. And a trench is buried, and a second barrier layer is formed on the side of the wiring so as to overlap with the first barrier layer and cover the wiring together with the first barrier layer, so that the first barrier layer and the second barrier layer are formed. The wiring can be completely covered with the barrier layer. Therefore, even if a stress of the wiring is applied to the first barrier layer and the second barrier layer, and either of the barrier layers is displaced, the first barrier layer and the second barrier layer are not overlapped with each other. Therefore, even if the wiring is formed of copper or a copper alloy, the movement of copper in the wiring can be prevented. Therefore, it is possible to manufacture a wiring having high wiring reliability in which occurrence of short circuit between wirings and generation of leakage current are suppressed.

According to the third method of manufacturing a semiconductor device according to the present invention, the upper portion of the wiring formed by embedding the recessed conductor formed in the insulating film is removed and the wiring is formed lower than the surface of the insulating film. The second barrier layer covers the upper side of the wiring and overlaps the first barrier layer on the upper side of the wiring to cover the wiring together with the first barrier layer. Therefore, the first barrier layer and the second barrier layer are formed. Can completely cover the wiring. Therefore, similarly to the first manufacturing method, even if the wiring is formed of copper or a copper alloy, movement of copper in the wiring, for example, ionized copper can be prevented. Therefore, it is possible to manufacture a wiring having high wiring reliability in which occurrence of short circuit between wirings and generation of leakage current are suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment according to a semiconductor device of the present invention.

FIG. 2 is a schematic configuration sectional view showing a second embodiment according to the semiconductor device of the present invention.

FIG. 3 is a schematic configuration sectional view showing a third embodiment according to the semiconductor device of the present invention.

FIG. 4 is a schematic sectional view showing a fourth embodiment according to the semiconductor device of the present invention;

FIG. 5 is a manufacturing process diagram showing an embodiment according to a first manufacturing method of the present invention.

FIG. 6 is a manufacturing process diagram showing a first embodiment according to a second manufacturing method of the present invention.

FIG. 7 is a manufacturing process diagram showing a second embodiment according to the second manufacturing method of the present invention.

FIG. 8 is a manufacturing process diagram showing an embodiment according to a third manufacturing method of the present invention.

FIG. 9 is a schematic sectional view showing a fifth embodiment according to the semiconductor device of the present invention.

FIG. 10 is a manufacturing process diagram for explaining a conventional method of forming a wiring by a damascene method.

[Explanation of symbols]

21 ... interlayer insulating film, 22 ... recess (wiring groove), 23 ... first
Barrier layer, 24 ... wiring, 25 ... second barrier layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Sachiji Miyata 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Koichi Ikeda 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) SS22 TT02 TT04 XX12 XX28

Claims (13)

[Claims] 1. A semiconductor device having a wiring inside a recess formed in an interlayer insulating film, wherein: a first barrier layer covering the wiring from a lower side of the wiring; and a wiring from an upper side of the wiring. A semiconductor device, comprising: a second barrier layer to cover, wherein the first barrier layer and the second barrier layer overlap each other to cover the wiring. 2. The semiconductor device according to claim 1, wherein an overlapping portion between the first barrier layer and the second barrier layer is provided on a side portion of the wiring. 3. The semiconductor device according to claim 1, wherein an overlapping portion between the first barrier layer and the second barrier layer is provided above the wiring. 4. The semiconductor device according to claim 1, wherein said recess comprises a groove, a connection hole, or a groove and a connection hole formed at a bottom of said groove. 5. A step of forming a wiring by forming a first barrier layer on the inner surface of the concave and forming a conductor inside the concave after forming the concave in the insulating film; Removing the insulating film and projecting the wiring and the first barrier layer from the surface of the insulating film; and covering an upper side of the wiring and forming the first barrier layer at a side of the wiring. Forming a second barrier layer that overlaps with the first barrier layer so as to cover the wiring together with the first barrier layer. 6. The manufacturing of a semiconductor device according to claim 5, wherein the steps from the step of removing the insulating film around the wiring to the step of forming the second barrier layer are performed in a non-oxidizing atmosphere. Method. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the recess is formed by a groove, a connection hole, or a groove and a connection hole formed at a bottom of the groove. 8. forming a recess in the insulating film, forming a first barrier layer on an inner surface of the recess, and forming a wiring by embedding a conductor in the recess; Forming a groove by removing the insulating film near the upper portion of the barrier layer; and forming a second barrier layer in a state of covering the upper side of the wiring and filling the groove. A method for manufacturing a semiconductor device. 9. The method according to claim 8, wherein the steps from the step of removing the insulating film around the wiring to the step of forming the second barrier layer are performed in a non-oxidizing atmosphere. Method. 10. The method according to claim 8, wherein the recess is formed by a groove, a connection hole, or a groove and a connection hole formed at the bottom of the groove. 11. A step of forming a recess in the insulating film, forming a first barrier layer on the inner surface of the recess, and burying a conductor in the recess to form a wiring; Removing the upper part of the wiring so as to be lower than the first wiring layer, and covering the upper side of the wiring and overlapping the first barrier layer at the upper part of the wiring so as to cover the wiring together with the first barrier layer. Forming a second barrier layer. 12. The method according to claim 11, wherein the steps from the step of removing the upper part of the wiring to the step of forming the second barrier layer are performed in a non-oxidizing atmosphere. 13. The method according to claim 11, wherein the recess is formed by a groove, a connection hole, or a groove and a connection hole formed at the bottom of the groove.