KR20030000827A - Method for Fabricating of Semiconductor Device - Google Patents

Method for Fabricating of Semiconductor Device Download PDF

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Publication number
KR20030000827A
KR20030000827A KR1020010036977A KR20010036977A KR20030000827A KR 20030000827 A KR20030000827 A KR 20030000827A KR 1020010036977 A KR1020010036977 A KR 1020010036977A KR 20010036977 A KR20010036977 A KR 20010036977A KR 20030000827 A KR20030000827 A KR 20030000827A
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South Korea
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insulating film
semiconductor device
copper
film
interlayer insulating
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KR1020010036977A
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Korean (ko)
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박상종
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주식회사 하이닉스반도체
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Priority to KR1020010036977A priority Critical patent/KR20030000827A/en
Publication of KR20030000827A publication Critical patent/KR20030000827A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent the device from being deteriorated by diffusion of copper atoms by using P, H and F having a gettering characteristic of the copper atoms in an insulation layer, and to improve the characteristic of the semiconductor device by eliminating the necessity of a barrier layer of a high dielectric constant. CONSTITUTION: The second interlayer dielectric(33) composed of a material which includes the composition having a gettering characteristic of the copper atoms and has a high dielectric constant, is formed on the first interlayer dielectric(31) having a lower metal pattern(32). A copper interconnection(34) penetrates the second interlayer dielectric and is connected to the lower metal pattern.

Description

반도체　소자의　제조방법{Method for Fabricating of Semiconductor Device}Method for Fabricating Semiconductor Devices

본 발명은 반도체　소자에 관한 것으로 특히, 구리　배선으로부터의　구리　원자　확산으로　인한　소자　열화를　방지하기　위한　반도체　소자의　제조방법에　관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing device degradation due to diffusion of copper atoms from copper wiring.

최근，　RC　딜레이（Delay)에　의한　소자　속도　특성을　향상시키기　위하여　구리　배선　공정에서　낮은　유전상수를　갖는　층간　절연막을　이용한　듀얼　또는　싱글　다마신　공정을　적용하고　있다．Recently, in order to improve the device speed characteristics due to RC delay, a dual or single damascene process using an interlayer insulating film having a low dielectric constant in copper wiring process has been applied.

이하，　첨부된　도면을　참조하여　종래　기술에　따른　반도체　소자의　제조방법을　설명하면　다음과　같다．Hereinafter, referring to the attached drawings, the manufacturing method of the semiconductor device according to the conventional technology will be described as follows.

도　１은　싱글　다마신（Single Damascene）　구조를　갖는　구리배선의　단면도이고，　도　２는　듀얼　다마신(Dual Damascene)　구조를　갖는　구리배선의　단면도이다．1 is a cross-sectional view of a copper wiring having a single damascene structure, and FIG. 2 is a cross-sectional view of a copper wiring having a dual damascene structure.

현재，　구리배선　공정은　도　１ 및　도　２에　도시된　바와　같이，　하부　금속　패턴（１２）이　형성된　제　１　층간　절연막（１１）상에　제　２　층간　절연막（１３）을　형성하고，　포토　 및　식각　공정으로　싱글　또는　듀얼　콘택홀을　형성한　뒤　상기　콘택홀에　구리를　매립하여　구리배선（１５）을　형성하고　있다．At present, the copper wiring process forms the second interlayer insulating film (13) on the first interlayer insulating film (11) on which the lower metal pattern (12) is formed, as shown in FIGS. 1 and 2, and the photolithography and etching processes are performed. After forming single or dual contact holes, copper copper (15) is formed by embedding copper in the contact holes.

여기서，　상기　제　２　층간　절연막（１３）은　SOG막，PE-CVD막　등과　같이　낮은　유전상수（Low-k）를　갖는　물질로　형성한다．Here, the second interlayer insulating film 13 is formed of a material having a low dielectric constant (Low-k), such as a SOG film and a PE-CVD film.

여기서，　상기　구리배선（１５）을　이루는　구리（Cu）　원자의　확산에　의한　소자　열화를　방지하기　위하여　상기　구리배선（１５）과　하부　금속　패턴（１２），　제　２　층간　절연막（１３）의　계면에　베리어막（１４）을　형성한다．Here, in order to prevent the deterioration of the element due to the diffusion of copper (Cu) atoms that make up the copper wiring (15), the copper wiring (15) and the lower metal metal pattern (12) and the barrier on the interlayer insulating film (13) of the second interlayer insulating film (13). A film (14) is formed.

이때，　상기　베리어막（１４）으로는　Ta, TaO　등의　물질이　사용되고　있으나，　상기　베리어막의　스텝　커버리지（Step Coverage)　특히，　제　２　층간　절연막（１３）과　구리배선（１５）의　계면에　형성되는　베리어막（１４）의　스텝　커버리지가　불량하여　상기　베리어막（１４）이　상기　구리배선（１５）의　베리어　역할을　충분히　하고　있지　못하고　있다．At this time, materials such as Ta and TaO are used as the barrier film 14, but the step barrier of the barrier film is particularly formed on the interfacial surfaces of the interlayer insulating film 13 and the copper wiring 15. The step barrier coverage of the membrane (14) is poor, and the barrier membrane (14) is not sufficient as the barrier of the copper wiring (15).

따라서, 　상기와 같은 종래의 반도체　소자의　제조방법은 베리어막이　구리배선에　대하여　베리어　역할을　충분히　하지　못함에　따라서　구리　원자가　확산되어　트랜지스터　특성　 및　리퀴지（Leakage)　특성이　열화되는　문제점이 있다.Therefore, the conventional method of manufacturing a semiconductor device as described above has a problem in that the barrier film does not sufficiently serve as a barrier against copper wiring, so that the copper atoms are diffused, resulting in deterioration of transistor characteristics and leakage characteristics.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 구리배선으로　부터　확산되는　구리　원자에　의한　소자　특성　열화를　방지하기　위한　반도체　소자의　제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for manufacturing a semiconductor device for preventing deterioration of device characteristics due to copper atoms diffused from a copper wiring.

도　１은　싱글　다마신（Single Damascene)　구조를　갖는　구리배선의　단면도Fig. 1 is a cross-sectional view of a copper wiring having a single single damascene structure.

도　２는　듀얼　다마신(Dual Damascene)　구조를　갖는　구리배선의　단면도Fig. 2 is a cross-sectional view of a copper wiring having a dual dual damascene structure.

도　３은　본　발명의　제　１　실시예에　따른　반도체　소자의　제조공정　단면도Figure 3 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

도　４는　본　발명의　제　２　실시예에　따른　반도체　소자의　제조공정　단면도4 is a cross-sectional view of the manufacturing process of the semiconductor device according to Example 2 of the present invention.

도　５는　본　발명의　제　３　실시예에　따른　반도체　소자의　제조공정　단면도5 is a cross-sectional view of the manufacturing process of the semiconductor device according to Example 3 of the present invention.

도　６은　인（P)의　　더블　본딩（Double Bonding）　구조를　나타낸　도면Fig. 6 is a drawing showing the structure of double bonding of P (P).

도　７은　H　또는　F의　논브릿징　본딩(Non-bridging Bonding)　구조를　나타낸　도면7 is a diagram showing a non-bridging bonding structure of H or F. FIG.

도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings

３1 :　제　１　층간　절연막　 　　　３２　：　하부　금속　패턴313: Interlayer insulating film made of 13: Lower metal pattern

３３　：　제　２　층간　절연막　　　３４　：　구리　배선330: Interlayer insulating film made of copper 303: Copper wiring

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은　하부　금속　패턴이　형성된　제　１　층간　절연막상에　구리　원자의　게더링　특성을　갖는　성분을　포함하며　낮은　유전상수를　갖는　물질로　제　２　층간　절연막을　형성하는　단계와，　상기　제　２　층간　절연막을　관통하여　상기　하부　금속　패턴에　연결되는　구리배선을　형성하는　단계를　포함하여　형성함을　특징으로　한다．A method for manufacturing a semiconductor device according to the present invention for achieving the above object includes a component having a “gathering” characteristic of copper atoms on a first interlayer insulating film having a lower metal pattern formed therebetween and a second interlayer made of a material having a low dielectric constant. And a step of forming an insulating film and a step of forming a copper wiring connected to the lower metal pattern by passing through the second interlayer insulating film.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체　소자의　제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도　３은　본　발명의　제　１　실시예에　따른　반도체　소자의　제조공정　단면도이고，　도　４는　본　발명의　제　２　실시예에　따른　반도체　소자의　제조공정　단면도이고，　도　５는　본　발명의　제　３　실시예에　따른　반도체　소자의　제조공정　단면도이고，　도　６은　인（P)의　　더블　본딩（Double Bonding）　구조를　나타낸　도면이고，　도　７은　H　또는　F의　논브릿징　본딩(Non-bridging Bonding)　구조를　나타낸　도면이다．3 is a cross-sectional view of the manufacturing process of a semiconductor device according to the first embodiment of the present invention, Figure 4 is a cross-sectional view of the manufacturing process of a semiconductor device according to the second embodiment of the present invention, Figure 5 is a third embodiment of the present invention. The semiconductor device is a cross-sectional view of the manufacturing process of the device, FIG. 6 is a diagram showing a double bonding structure of phosphorus (P), and FIG. 7 is a non-bridging bonding structure of H or F. FIG. Drawing.

본　발명의　제　１　실시예에　따른　반도체　소자의　제조방법은　도　３에　도시된　바와　같이，　하부　금속　패턴（３２）이　형성된　제　１　층간　절연막（３１）상에　제　２　층간　절연막（３３）을　형성한다．According to the first embodiment of the present invention, the manufacturing method of the semiconductor device forms a second interlayer insulating film (33) on the first interlayer insulating film (31) on which the lower metal pattern (32) is formed, as shown in FIG. ．

여기서，　상기　제　２　층간　절연막（３３）은　　SOG막, PE-CVD막　등과　같이　유전상수가　낮은　물질을　형성한　후　인（P)을　도핑하거나，　P－도핑된　SOG막을　이용하나，　H　혹은　F가　포함된　저유전막을　이용하여　형성한다．Here, the above-described interlayer insulating film 33 is doped with phosphorus (P) after forming a low dielectric constant material such as SOG film, PE-CVD film, etc., or P-doped SOG film is used. It is formed using the included low dielectric film.

이어，　포토　 및　식각　공정으로　상기　하부　금속　패턴（３２）의　일부분이　노출되도록　싱글　혹은　듀얼　구조의　콘택홀을　형성하고　상기　콘택홀에　구리를　매립하여　구리배선（３４）을　형성한다．Subsequently, a contact hole having a single or dual structure is formed so as to expose a portion of the lower metal pattern (3 2) through a photolithography and etching process, and copper is embedded in the contact hole by forming copper copper wiring (34).

이때，　상기　구리배선（３４）으로부터의　구리　원자는　상기　제　２　층간　절연막（３３）에　포함되어　있는　P　이온에　의한　도　６과　같은　댕글링　본딩（Dangling Bonding)　구조　내지　H 또는　F에　의한　도　７과　같은　논브릿지　본딩　구조와　결합하게　되어　제거되게　된다．At this time, the copper atoms from the copper wirings (34) are similar to those of the Dangling Bonding structure as shown in Fig. 6 according to the P ions contained in the interlayer insulating film (33). In combination with the same non-bridge bonding structure, they are removed.

그리고，　본　발명의　제　２　실시예에　따른　반도체　소자의　제조방법은　하부　금속　패턴（４２）이　형성된　제　１　층간　절연막（４１）의　표면상에　라이너（Liner)막（４３）을　　형성하고　상기　라이너막(43)상에　낮은　유전　상수를　갖는　제　２　층간　절연막（４４）을　형성한다．In the semiconductor device according to the second embodiment of the present invention, a liner film 433 is formed on the surface of the first interlayer insulating film 41 in which the lower metal pattern 42 is formed, and the liner film is formed. On (43), a second interlayer insulating film (44) having a low dielectric constant is formed.

여기서，　상기　라이너막（４３）은　상기　H 혹은　F가　포함된　유전상수가　낮은　물질로　형성한다．Here, the thinner film 433 is formed of a material having a low dielectric constant containing H or F.

이어，　포토　 및　식각　공정으로　상기　하부　금속　패턴（４２）의　표면이　노출되도록　상기　제　２　층간　절연막（４４）과　라이너막（４５）을　선택적으로　제거하여　콘택홀을　형성한다．Next, the contact hole is formed by selectively removing the interlayer insulating film 4 and liner film 45 so that the surface of the lower metal pattern 4 2 is exposed by photolithography and etching processes.

이어，　상기　콘택홀에　구리를　매립하여　구리배선（４５）을　형성한다．Subsequently, copper is buried in the contact hole to form copper wiring (45).

본　발명의　제　２　실시예에서는　상기　구리배선（４５）으로부터　확산되는　구리원자가　상기　라이너막（４３）의　H 혹은　F의　논브릿지　본딩　구조와　결합되어　제거된다．In the second embodiment of the present invention, copper atoms diffused from the copper wiring (45) are combined with the non-bridge bridge structure of the H or F of the liner film (43) to be removed.

그리고，　본　발명의　제　３　실시예에　따른　반도체　소자의　제조방법은　상기　제　２　실시예에서　상기　제　２　층간　절연막（４４）의　하부에　형성되는　라이너막（４３）을，　제　２　층간　절연막（５３）의　상부에　캡핑막（５４）으로　형성한　것으로，　상기　제　２　실시예와　그　형성　방법　 및　원리가　유사하다．In addition, according to the third embodiment of the present invention, a method for manufacturing a semiconductor device is described in the second embodiment, in which the liner film 433 formed under the second interlayer insulating film 444 is formed, and the second interlayer insulating film 53 is formed. The capping film (54) was formed on the upper portion of the upper portion of the upper portion of the upper surface of the upper surface of the upper surface, and thus, the method and the principle of formation thereof were similar to those of the second embodiment.

다만，　라이너막（４３）　대신에　형성하는　캡핑막（５４）을　상기　제　２　층간　절연막（５３）후에　형성하는　점만　상이하므로　이하　생략하기로　한다．However, since the capping film (5) formed instead of the liner film (43) is different from the point formed after the second interlayer insulating film (53) described above, the following description will be omitted.

상기와 같은 본 발명의 반도체　소자의　제조방법은 다음과 같은 효과가 있다.The method for manufacturing a semiconductor device of the present invention as described above has the following effects.

첫째，　Cu　원자의　게더링（Gettering)　특성이　있는　P, H, F　등을　층간　절연막에　적용하여　구리　원자　확산으로　인한　소자　열화를　방지할　수　있다．First, P, H, and F, which have the gettering characteristic of Cu atoms, can be applied to an interlayer insulating film to prevent element degradation caused by copper atom diffusion.

둘째，　유전상수가　높은　베리어막을　사용하지　않아도　되므로　반도체　소자의　특성을　향상시킬　수　있다．Second, the barrier film with high dielectric constant can be avoided, which can improve the semiconductor device's characteristics.

Claims (4)

하부　금속　패턴이　형성된　제　１　층간　절연막상에　구리　원자의　게더링　특성을　갖는　성분을　포함하며　낮은　유전상수를　갖는　물질로　제　２　층간　절연막을　형성하는　단계；A step of forming a second interlayer insulating film made of a material having a low dielectric constant, including a component having copper metal gathering characteristics on a first interlayer insulating film having a lower metal pattern formed thereon; 상기　제　２　층간　절연막을　관통하여　상기　하부　금속　패턴에　연결되는　구리배선을　형성하는　단계를　포함하여　형성함을　특징으로　하는　반도체　소자의　제조방법．A method of manufacturing a semiconductor device, characterized in that it comprises forming a copper wiring connected to the lower metal pattern by passing through the interlayer insulating film of the second layer. 제　１　항에　있어서，　상기　제　２　층간　절연막은　P　이온이　도핑된　절연막　，　혹은　H 또는　F　가　포함된　절연막으로　형성함을　특징으로　하는　반도체　소자의　제조방법．The method of manufacturing a semiconductor device according to claim 11, characterized in that the above-described interlayer interlayer insulating film is formed of an insulating film doped with P ions or an insulating film containing H or F. 제　１　항에　있어서，　상기　제　２　층간　절연막은　In Clause 11, the interlayer dielectric film 구리　원자　게더링　특성　 및　낮은　유전상수를　갖는　라이너막을　형성하는　단계；Forming a liner film having copper atomic gathering characteristics and low dielectric constant; 상기　박막상에　낮은　유전상수를　갖는　소정　두께의　절연막을　형성하는　단계를　포함하여　형성함을　특징으로　하는　반도체　소자의　제조방법．A method of manufacturing a semiconductor device, characterized in that it comprises a step of forming an insulating film of a predetermined thickness having a low dielectric constant on the thin film. 제　１　항에　있어서，　상기　제　２　층간　절연막은In Clause 11, the interlayer dielectric film 상기　제　１　층간　절연막상에　낮은　유전상수를　갖는　소정　두께의　절연막을　형성하는　단계；Forming an insulating film having a predetermined thickness having a low dielectric constant on the first interlayer insulating film; 구리　원자　게더링　특성　 및　낮은　유전상수를　갖는　캡핑막을　형성하는　단계를　포함하여　형성함을　특징으로　하는　반도체　소자의　제조방법．A method for manufacturing a semiconductor device characterized by the formation of a copper element, including a step of forming a capping film having a copper atomic gathering characteristic and a low dielectric constant.
KR1020010036977A 2001-06-27 2001-06-27 Method for Fabricating of Semiconductor Device KR20030000827A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100731075B1 (en) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 Semiconductor device and method for fabricating the same
KR100763694B1 (en) * 2006-08-31 2007-10-04 동부일렉트로닉스 주식회사 Method for forming inter metal dielectric layer in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100731075B1 (en) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 Semiconductor device and method for fabricating the same
KR100763694B1 (en) * 2006-08-31 2007-10-04 동부일렉트로닉스 주식회사 Method for forming inter metal dielectric layer in semiconductor device

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