KR20000003264A - Semiconductor device contact hole filling method - Google Patents

Semiconductor device contact hole filling method Download PDF

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Publication number
KR20000003264A
KR20000003264A KR1019980024468A KR19980024468A KR20000003264A KR 20000003264 A KR20000003264 A KR 20000003264A KR 1019980024468 A KR1019980024468 A KR 1019980024468A KR 19980024468 A KR19980024468 A KR 19980024468A KR 20000003264 A KR20000003264 A KR 20000003264A
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contact hole
film
metal film
forming
semiconductor device
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KR1019980024468A
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Korean (ko)
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이재욱
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윤종용
삼성전자 주식회사
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Priority to KR1019980024468A priority Critical patent/KR20000003264A/en
Publication of KR20000003264A publication Critical patent/KR20000003264A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A contact hole filling method is provided to improve the fluidity of metal film and the fill margin of the contact hole by interposing a silicon between the contact hole and the metal film. CONSTITUTION: The contact hole filling method comprises steps of; forming a contact hole(24) on the semiconductor substrate(20) which has an insulation film(22); forming a diffuser barrier layer(26) on the contact hole(24), forming a non-crystalline silicon film(28) on the diffusion barrier layer; forming a metal film on the non-crystalline silicon film; thermo-treating the semiconductor substrate on which the metal film is formed and filling up the contact hole.

Description

반도체 장치의 콘택홀 필링 방법Contact hole filling method of semiconductor device

본 발명은 반도체 장치의 콘택홀 필링 방법에 관한 것으로서, 보다 상세하게는 비정질 실리콘막을 금속막 하지막으로 사용하여 형성된 콘택홀을 필링하는 반도체 장치의 콘택홀 필링 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact hole filling method of a semiconductor device, and more particularly, to a contact hole filling method of a semiconductor device for filling a contact hole formed by using an amorphous silicon film as a metal film underlying film.

통상, 반도체 장치의 제조공정에서는 소자와 소자간을 연결시키거나 패드(Pad)의 연결 등을 위해서 게이트전극 상부, 소스영역 상부 및 드레인영역 상부 등에 콘택홀(Contact hole)을 형성하고 있다.In the semiconductor device manufacturing process, contact holes are formed in the upper portion of the gate electrode, the upper portion of the source region, and the upper portion of the drain region in order to connect the elements with the elements or to connect the pads.

또한, 최근에 반도체 장치의 고집적화됨에 따라 반도체 장치의 디자인룰(Design rule)이 점점 작아짐에 따라 콘택홀의 종횡비(Aspect ratio)가 증가하고 있다. 즉, 콘택홀의 직경은 작아지고 깊이는 깊어지고 있다.In addition, as the integration of semiconductor devices has increased recently, the aspect ratio of contact holes has increased as the design rules of the semiconductor devices have become smaller. That is, the diameter of the contact hole is small and the depth is deepening.

도1 내지 도5는 종래의 콘택홀 필링 방법을 나타내는 일 실시예의 단면도들이다.1 to 5 are cross-sectional views of one embodiment showing a conventional contact hole filling method.

종래의 콘택홀 필링 방법에서는 먼저 도1에 도시된 바와 같이 반도체 기판(10)상에 절연막(12)을 형성한 후, 도2에서 도시된 바와 같이 상기 절연막(12)이 형성된 반도체 기판 상에 콘택홀(14)을 형성한다.In the conventional contact hole filling method, first, an insulating film 12 is formed on a semiconductor substrate 10 as shown in FIG. 1, and then a contact is formed on a semiconductor substrate on which the insulating film 12 is formed as shown in FIG. 2. The hole 14 is formed.

도3을 참조하면, 상기 콘택홀(14)이 형성된 절연막(12)상에 확산 장벽층(16)을 1000Å 내지 1500Å 두께로 형성한다. 상기 확산 장벽층은 순차적으로 티타늄막 및 티타늄나이트라이드막을 형성한다.Referring to FIG. 3, a diffusion barrier layer 16 is formed on the insulating film 12 having the contact hole 14 to have a thickness of 1000 Å to 1500 Å. The diffusion barrier layer sequentially forms a titanium film and a titanium nitride film.

이어서, 도4를 참조하면, 상기 확산 장벽층(16) 상에 금속막을 소정의 두께로 형성한 후, 도5를 참조하면, 상기 금속막이 형성된 반도체 기판을 고온에서 열처리하여 상기 콘택홀(14)을 매몰시킨다.Next, referring to FIG. 4, a metal film is formed on the diffusion barrier layer 16 to a predetermined thickness. Referring to FIG. 5, the semiconductor substrate on which the metal film is formed is heat-treated at a high temperature to contact the contact hole 14. Bury them.

상기 금속막(18)은 구리와 실리콘 그리고 알루미늄의 합금을 사용하며, 두께는 5000Å이다. 상기 구리함량은 0.5%고 실리콘은 0.2%이다.The metal film 18 is made of an alloy of copper, silicon, and aluminum, and has a thickness of 5000 kPa. The copper content is 0.5% and the silicon is 0.2%.

그러나, 상기 종래의 반도체 장치의 콘택홀 필링 방법으로는 소자의 집적도가 증가함에 따라 상기 소자에 사용되는 금속 배선의 선폭의 감소와 더불어 전극을 형성하는 콘택홀 부위의 면적 감소와 콘택홀의 깊이가 깊어진 콘택홀을 필링하는 데 기존의 스퍼터링 방식으로는 더 이상의 필링을 기대할 수 없는 공정들이 생겨나는 문제점이 있었다.However, in the contact hole filling method of the conventional semiconductor device, as the degree of integration of the device increases, the line width of the metal wiring used in the device decreases, the area of the contact hole forming the electrode, and the depth of the contact hole become deep. There was a problem in that processes for filling a contact hole, which can not expect any more peeling by the conventional sputtering method.

본 발명의 목적은, 콘택홀과 금속막사이에 실리콘막을 게재함으로써, 인위적 확산을 이용하여 금속막의 유동성을 증가시켜 콘택홀의 필 마진을 향상시키는 반도체 장치의 콘택홀 필링 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for filling a contact hole in a semiconductor device in which a silicon film is disposed between the contact hole and the metal film, thereby increasing the fluidity of the metal film using artificial diffusion to improve the fill margin of the contact hole.

도1 내지 도5는 종래의 콘택홀 필링 방법을 나타내는 단면도들이다.1 to 5 are cross-sectional views illustrating a conventional contact hole filling method.

도6 내지 도11은 본 발명의 일 실시예에 따른 반도체 장치의 콘택홀 필링 방법을 나타내는 공정 단면도들이다.6 through 11 are cross-sectional views illustrating a method for contact hole filling of a semiconductor device according to example embodiments.

※ 도면의 주요 부분에 대한 부호의 설명※ Explanation of codes for main parts of drawing

10,20 : 반도체 기판 12,22 : 절연막10,20 semiconductor substrate 12,22 insulating film

14,24 : 콘택홀 16,26 : 확산 장벽층14,24: contact hole 16,26: diffusion barrier layer

18,30 : 금속막 28 : 비정질 실리콘막18,30 metal film 28 amorphous silicon film

상기 목적을 달성하기 위한 본 발명에 따른 반도체 장치의 콘택홀 필링 방법은, 절연막이 형성된 반도체 기판 상에 콘택홀을 형성하는 단계, 상기 콘택홀 상에 확산 장벽층을 형성하는 단계, 상기 확산 장벽층 상에 비정질 실리콘막을 형성하는 단계, 상기 비정질 실리콘막 상에 금속막을 형성하는 단계 및 상기 금속막이 형성된 반도체 기판을 열처리함으로써 상기 콘택홀을 매몰시키는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a contact hole filling method of a semiconductor device, the method comprising: forming a contact hole on a semiconductor substrate on which an insulating layer is formed, forming a diffusion barrier layer on the contact hole, and forming the diffusion barrier layer. Forming an amorphous silicon film on the substrate; forming a metal film on the amorphous silicon film; and embedding the contact hole by heat-treating the semiconductor substrate on which the metal film is formed.

상기 확산 장벽층은 순차적으로 적층된 티타늄막 및 티타늄나이트라이드막이며, 두께는 1000Å 내지 1500Å일 수 있다.The diffusion barrier layer may be a titanium film and a titanium nitride film that are sequentially stacked, and may have a thickness of 1000 mW to 1500 mW.

상기 비정질 실리콘막의 두께는 100Å 이하일 수 있다.The amorphous silicon film may have a thickness of 100 μm or less.

상기 금속막은 알루미늄 재질로 형성된 것이나, 구리와 알루미늄 재질로 형성된 것일 수 있으며, 상기 구리함량은 0.4 내지 0.6%인 것을 사용할 수 있다.The metal film may be formed of an aluminum material, or may be formed of copper and an aluminum material, and the copper content may be 0.4 to 0.6%.

상기 열처리 온도는 490℃ 내지 550℃인 것을 특징으로 한다.The heat treatment temperature is characterized in that 490 ℃ to 550 ℃.

이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도6 내지 도11은 본 발명의 일 실시예에 따른 반도체 장치의 콘택홀 필링 방법을 나타내는 공정의 단면도들이다.6 through 11 are cross-sectional views illustrating a process of contact hole filling method of a semiconductor device according to example embodiments.

본 발명의 반도체 장치의 콘택홀 필링 방법을 설명하면, 먼저 도6에서 보는 바와 같이 반도체 기판(20) 상에 절연막(22)을 형성한 후, 도7과 같이 상기 절연막(22)이 형성된 반도체 기판(20) 상에 콘택홀(24)을 형성한다.Referring to the contact hole filling method of the semiconductor device of the present invention, as shown in FIG. 6, an insulating film 22 is formed on the semiconductor substrate 20, and then the semiconductor substrate on which the insulating film 22 is formed as shown in FIG. 7. A contact hole 24 is formed on the 20.

그리고 도8에 도시된 것과 같이, 상기 콘택홀(24) 상에 순차적으로 티타늄막 및 티타늄나이트라이드막인 확산 장벽층(26)을 1000Å 내지 1500Å 두께로 형성한다.As shown in FIG. 8, the diffusion barrier layer 26, which is a titanium film and a titanium nitride film, is sequentially formed on the contact hole 24 to have a thickness of 1000 Å to 1500 Å.

이어서, 도9에 도시된 바대로 상기 확산 장벽층(26) 상에 비정질 실리콘막(28)을 100Å이하로 형성한다.Subsequently, as shown in FIG. 9, an amorphous silicon film 28 is formed on the diffusion barrier layer 26 to 100 mW or less.

상기 비정질 실리콘막(28) 상에 도10과 같이 금속막(30)을 5000Å 두께로 형성한다. 상기 금속막(30)은 알루미늄 재질로 형성된 것이나, 구리와 알루미늄 재질로 형성된 것을 사용할 수 있다. 상기 구리함량은 0.4 내지 0.6%인 것이며, 바람직하기로는 0.5%인 것이다.A metal film 30 is formed on the amorphous silicon film 28 as shown in FIG. The metal film 30 may be formed of aluminum or may be formed of copper and aluminum. The copper content is 0.4 to 0.6%, preferably 0.5%.

이어서, 도11을 참조하면, 상기 금속막(30)이 형성된 반도체 기판(20)을 490℃ 내지 550℃로 열처리함으로써 상기 콘택홀(24)을 매몰시킨다.Subsequently, referring to FIG. 11, the contact hole 24 is buried by heat-treating the semiconductor substrate 20 on which the metal film 30 is formed at 490 ° C to 550 ° C.

인위적으로 확산을 유발시키기 위한 비정질 실리콘의 하지막을 추가로 형성하여 후속 열처리 혹은 고온 증착 공정에서 이미 형성된 알루미늄의 내부로 확산시킴으로 인하여 금속막의 유동도를 증가시키는 역할을 한다.It additionally forms an underlayer of amorphous silicon to artificially induce diffusion to diffuse into the aluminum already formed in a subsequent heat treatment or high temperature deposition process, thereby increasing the flow of the metal film.

따라서, 본 발명에 의하면 콘택홀과 금속막사이에 실리콘막을 게재함으로써, 인위적 확산을 이용하여 금속막의 유동성을 증가시켜 콘택홀의 필 마진을 향상시키는 효과가 있다.Therefore, according to the present invention, by placing a silicon film between the contact hole and the metal film, there is an effect of increasing the fluidity of the metal film by using artificial diffusion to improve the fill margin of the contact hole.

이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.

Claims (8)

절연막이 형성된 반도체 기판 상에 콘택홀을 형성하는 단계;Forming a contact hole on the semiconductor substrate on which the insulating film is formed; 상기 콘택홀 상에 확산 장벽층을 형성하는 단계;Forming a diffusion barrier layer on the contact hole; 상기 확산 장벽층 상에 비정질 실리콘막을 형성하는 단계;Forming an amorphous silicon film on the diffusion barrier layer; 상기 비정질 실리콘막 상에 금속막을 형성하는 단계; 및Forming a metal film on the amorphous silicon film; And 상기 금속막이 형성된 반도체 기판을 열처리함으로써 상기 콘택홀을 매몰시키는 단계;Burying the contact hole by heat-treating the semiconductor substrate on which the metal film is formed; 를 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 콘택홀 필링 방법.Contact hole filling method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 확산 장벽층은 순차적으로 적층된 티타늄막 및 티타늄나이트라이드막인 것을 특징으로 하는 상기 반도체 장치의 콘택홀 필링 방법.And the diffusion barrier layer is a titanium film and a titanium nitride film sequentially stacked. 제 2 항에 있어서,The method of claim 2, 상기 확산 장벽층의 두께는 1000Å 내지 1500Å인 것을 특징으로 하는 상기 반도체 장치의 콘택홀 필링 방법.And the diffusion barrier layer has a thickness of 1000 ns to 1500 ns. 제 1 항에 있어서,The method of claim 1, 상기 비정질 실리콘막의 두께는 100Å 이하인 것을 특징으로 하는 상기 반도체 장치의 콘택홀 필링 방법.And a thickness of the amorphous silicon film is 100 kW or less. 제 1 항에 있어서,The method of claim 1, 상기 금속막은 알루미늄 재질로 형성된 것을 특징으로 하는 상기 반도체 장치의 콘택홀 필링 방법.And the metal film is formed of aluminum. 제 1 항에 있어서,The method of claim 1, 상기 금속막은 구리와 알루미늄 재질로 형성된 것을 특징으로 하는 상기 반도체 장치의 콘택홀 필링 방법.And the metal film is formed of copper and aluminum. 제 6항에 있어서,The method of claim 6, 상기 구리함량은 0.4 내지 0.6%인 것을 특징으로 하는 상기 반도체 장치의 콘택홀 필링 방법.The copper content is a contact hole filling method of the semiconductor device, characterized in that 0.4 to 0.6%. 제 1 항에 있어서,The method of claim 1, 상기 열처리 온도는 490℃ 내지 550℃인 것을 특징으로 하는 상기 반도체 장치의 콘택홀 필링 방법.The heat treatment temperature is a contact hole filling method of the semiconductor device, characterized in that 490 ℃ to 550 ℃.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100667253B1 (en) * 2006-03-28 2007-01-11 김재칠 A tangled powdered red pepper's separator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100667253B1 (en) * 2006-03-28 2007-01-11 김재칠 A tangled powdered red pepper's separator

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