KR100312030B1 - Method for forming metal line in semiconductor device - Google Patents

Method for forming metal line in semiconductor device Download PDF

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KR100312030B1
KR100312030B1 KR1019940035727A KR19940035727A KR100312030B1 KR 100312030 B1 KR100312030 B1 KR 100312030B1 KR 1019940035727 A KR1019940035727 A KR 1019940035727A KR 19940035727 A KR19940035727 A KR 19940035727A KR 100312030 B1 KR100312030 B1 KR 100312030B1
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South Korea
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film
metal
forming
semiconductor device
metal line
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KR1019940035727A
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Korean (ko)
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KR960026629A (en
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신찬수
진성곤
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metal line in a semiconductor device is provided to reduce leakage current and to prevent junction breakage by using a Ti/TiNOx layer having excellent diffusion barrier property as a barrier metal. CONSTITUTION: An insulating pattern(2) having a contact hole is formed on a silicon substrate(1). A Ti and TiN layer are sequentially stacked on the resultant structure by reactive sputtering. By implanting oxygen ions into the TiN layer and annealing at H2 and N2 atmosphere, in the temperature of 450-500°C and for 25-40 minute, a barrier metal(6) made of Ti/TiNOx is formed on the resultant structure. A metal line(7) composed of aluminum is then formed on the barrier metal(6).

Description

반도체 소자의 금속배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 특히 장벽금속(barrier metal)의 장벽효과를 증대시키는 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings for increasing barrier effects of barrier metals.

일반적으로, 반도체 소자 제조 공정 중, 예를 들어 디램(DRAM)에서 워드라인으로 사용되는 폴리실리콘은 저항이 높아 스피드 문제점이 있기 때문에 이를 보완하기 위하여 공정이 용이하고 가격이 경제적인 알루미늄을 이용한 금속배선 공정을행하는데, 알루미늄과 접속되는 실리콘 사이의 접합 스파이킹을 방지하고 금속의 층덮힘, EM 특성향상을 위해 현재 장벽금속으로 스퍼터링을 이용하여 Ti/TiN막을 형성하고 있다.In general, polysilicon used as a word line in a DRAM, for example, in a semiconductor device manufacturing process, has a high resistance and has a problem of speed, so it is easy to process and economical metal wiring using aluminum to compensate for this. In performing the process, Ti / TiN films are currently formed using sputtering as a barrier metal to prevent junction spiking between aluminum and silicon to be connected and to improve metal layer covering and EM characteristics.

그러나, 소자가 고집적화 됨에 따라 누설전류 증가 및 접합 파괴 등이 크게 발생하여 소자에 큰 영향을 줌으로 Ti/TiN막은 장벽금속으로써 소자적용에 한계점을 나타내게 되었다.However, as the device is highly integrated, leakage current increases and junction breakage is greatly generated, which greatly affects the device. Thus, the Ti / TiN film is a barrier metal and shows a limitation in application.

따라서, 본 발명은 알루미늄박과 실리콘 사이의 장벽 역할을 효과적으로 수행하는 장벽금속막을 형성하는 금속배선 형성 방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a metal wiring forming method for forming a barrier metal film that effectively performs a barrier role between aluminum foil and silicon.

상기 목적을 달성하기 위하여 본 발명은 반도체소자의 금속배선 형성방법에 있어서, 실리콘층 상에 금속 콘택홀이 오픈된 절연막패턴을 형성하는 제l단계; 제1단계가 완료된 결과물 상에 Ti 및 TiN막을 적출 형성하는 제2단계; 상기 TiN막 내에 산소 이온을 이온주입하는 제3단계; H2및 N2가스분위기, 450∼500℃의 온도에서 25∼40분 동안 어닐링하여 상기 TiN막을 TiNOx막으로 형성하는 제4단계; 및 상기 제4단계가 완료된 결과물 상에 배선용 알루미늄막을 형성하는 제5단계를 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a metal wiring in a semiconductor device, the method comprising: forming an insulating film pattern with an open metal contact hole on a silicon layer; A second step of extracting and forming Ti and TiN films on the resultant of the first step; A third step of ion implanting oxygen ions into the TiN film; A fourth step of annealing the H 2 and N 2 gas atmosphere at a temperature of 450 to 500 ° C. for 25 to 40 minutes to form the TiN film as a TiNO x film; And a fifth step of forming an aluminum film for wiring on the resultant of the fourth step.

이하, 된 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

첨부된, 도면 제 1A 도 내지 제 1D 도는 본 발명의 일실시예에 따른 금속배선 형성공정을 나타내는 단편도이다.1A to 1D are accompanying drawings illustrating a metallization process according to an exemplary embodiment of the present invention.

먼저, 제 1A 도는 절연막(2)의 소정부위가 식각되어 금속콘택홀(3)이 형성된 반도체기판(1)상에 반응(Reactive) 스퍼터링법에 의해 Ti/TiN막(4)을 형성한 상태이다.First, FIG. 1A shows a Ti / TiN film 4 formed by reactive sputtering on a semiconductor substrate 1 on which a predetermined portion of the insulating film 2 is etched to form a metal contact hole 3. .

이어서, 제 1B 도와 같이, 상기 Ti/TiN막(4)상에 산소이온주입(5)을 실시하고, 제1C 도와 같이 H2및 N2가스분위기, 450∼500℃의 온도에서 25∼40분 동안 어닐링하여 Ti/TiNOx막(6)을 형성한다.Subsequently, oxygen ion implantation 5 is performed on the Ti / TiN film 4 as in the first B diagram, and 25 to 40 minutes at a temperature of H 2 and N 2 gas atmosphere at 450 to 500 ° C. as in the first C diagram. Annealing during the formation of the Ti / TiNOx film 6.

계속해서, 제 1D 도는 상기 Ti/TiNOx막(6)을 장벽금속으로 하여 주 금속배선막인 알루미늄막(7)을 형성한 상태이다.Subsequently, in Fig. 1D, the aluminum film 7 serving as the main metal wiring film is formed using the Ti / TiNOx film 6 as the barrier metal.

이상, 상기 설명과 같이 본 발명은 장벽금속을 Ti/TiNOx막으로 사용함으로써 실리콘과 알루미늄간의 우수한 확산장벽 특성으로 인하여 고온에서도 안정한 금속콘택을 형성할 수 있어 누설전류를 감소시키고 접합이 파괴되는 것을 줄일 수 있어 소자의 특성 향상 및 수율 증대를 가져오는 효과가 있다.As described above, according to the present invention, the barrier metal is used as the Ti / TiNOx film to form a stable metal contact even at a high temperature due to the excellent diffusion barrier property between silicon and aluminum, thereby reducing leakage current and reducing junction breakage. It is possible to improve the characteristics of the device and increase the yield.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

재 1A 도 내지 제 1D 도는 본 발명의 일실시예에 따른 금속배선 형성 공정도.1A to 1D are metal wire forming process diagrams according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1: 실리콘 기판 2 : 절연막1: silicon substrate 2: insulating film

3: 금속 콘택홀 4: Ti/TiN막3: metal contact hole 4: Ti / TiN film

5: 산소이온주입 6: Ti/TINOx막5: oxygen ion injection 6: Ti / TINOx film

7. 알루미늄막7. Aluminum film

Claims (1)

반도체소자의 금속배선 형성방법에 있어서,In the metal wiring forming method of a semiconductor device, 실리콘층 상에 금속 콘택홀이 오픈된 절연막패턴을 형성하는 제1단계;A first step of forming an insulating film pattern with a metal contact hole open on the silicon layer; 제1단계가 완료된 결과물 상에 반응성 스퍼터링법에 의해 Ti 및 TiN막을 적층 형성하는 제2단계 ;A second step of stacking Ti and TiN films by a reactive sputtering method on the resultant of the first step; 상기 TiN막 내에 산소 이온을 이온주입하는 제1단계;A first step of ion implanting oxygen ions into the TiN film; H2및 N2가스분위기, 450∼500℃의 온도에서 25∼40분 동안 어닐링하여 상기 산소 이온주입된 TiN막을 TiNOx막으로 형성하는 제4단계; 및A fourth step of annealing the H 2 and N 2 gas atmosphere at a temperature of 450 to 500 ° C. for 25 to 40 minutes to form the oxygen ion-implanted TiN film as a TiNO x film; And 상기 제4단계가 완료된 결과물 상에 배선용 알루미늄막을 형성하는 제5단계를 포함하여 이루어진 반도체소자의 금속배선 형성방법.And a fifth step of forming an aluminum film for wiring on the resultant of the fourth step.
KR1019940035727A 1994-12-21 1994-12-21 Method for forming metal line in semiconductor device KR100312030B1 (en)

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KR1019940035727A KR100312030B1 (en) 1994-12-21 1994-12-21 Method for forming metal line in semiconductor device

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KR100312030B1 true KR100312030B1 (en) 2002-04-24

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* Cited by examiner, † Cited by third party
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KR100436057B1 (en) * 1997-12-30 2004-12-17 주식회사 하이닉스반도체 Method for fabricating high dielectric capacitor of semiconductor device to guarantee process margin

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211826A (en) * 1990-01-17 1991-09-17 Fujitsu Ltd Manufacture of semiconductor device
JPH04151825A (en) * 1990-10-15 1992-05-25 Sony Corp Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211826A (en) * 1990-01-17 1991-09-17 Fujitsu Ltd Manufacture of semiconductor device
JPH04151825A (en) * 1990-10-15 1992-05-25 Sony Corp Semiconductor device and manufacture thereof

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