KR960006430B1 - Manufacturing process of semiconductor device - Google Patents

Manufacturing process of semiconductor device Download PDF

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KR960006430B1
KR960006430B1 KR1019890020735A KR890020735A KR960006430B1 KR 960006430 B1 KR960006430 B1 KR 960006430B1 KR 1019890020735 A KR1019890020735 A KR 1019890020735A KR 890020735 A KR890020735 A KR 890020735A KR 960006430 B1 KR960006430 B1 KR 960006430B1
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forming
barrier layer
semiconductor device
doped region
manufacturing
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KR910013495A (en
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박창수
안용철
박종호
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삼성전자주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The method of fabricating a semiconductor device includes the steps of forming a second conductive doping region(19) in a predetermined portion of a first conductive semiconductor substrate(11), forming an insulating layer(21) on the substrate and selectively etching it to form a contact hole(23) to expose the doping region, forming at least two layers of barrier layers(25,27) on the substrate including the insulating layer, ion-implanting into the barrier layers to make them in amorphous state and carrying out heat treatment, and forming a metal layer(29) on the barrier layers.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

제1(a)~(c)도는 종래의 반도체 장치의 제조방법을 나타내는 수직단면도.1 (a) to (c) are vertical cross-sectional views showing a conventional method for manufacturing a semiconductor device.

제2(a)∼(c)도는 본 발명에 따른 반도체 장치의 제조방법을 나타내는 수직단면도.2 (a) to 2 (c) are vertical cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체기판 13 : 패드산화막11 semiconductor substrate 13 pad oxide film

15 : 질화막 17 : 확산개구15: nitride film 17: diffusion opening

19 : 도핑영역 21 : 절연막19 doping region 21 insulating film

23 : 접촉개구 25 : 제1장벽층23: contact opening 25: the first barrier layer

26 : 실리사이드층 27 : 제2장벽층26: silicide layer 27: second barrier layer

29 : 금속배선막29 metal wiring film

본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 금속 배선막 형성시 접촉면에서 스파이크(Splke)가 발생하는 것을 방지할 수 있는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device which can prevent the occurrence of spikes on contact surfaces when forming a metal wiring film.

최근 반도체 제조기술의 발달과 메모리소자의 응용 분야가 확장되어 감에 따라 대용량의 메모리소자 개발이 빠른 속도로 진행되고 있다. 이러한 메모리소자의 대용량화는 각 세대마다 2배 정도로 진행하는 미세프로세스 기술을 기본으로하여 고집적화를 이루는데 있다. 특히 반도체 장치의 제조에 있어서 배선기술은 반도체소자의 미세화에 있어 중요한 항목중에 하나이다. 이러한 배선기술은 메모리의 워드선으로 이용되는 게이트전극과 같은 다결정실리콘의 배선과 소오스(드레인)확산 영역과의 접촉 및 각 소자를 상호 접속하는 금속배선등으로 분류된다.Recently, as the development of semiconductor manufacturing technology and the application field of memory devices are expanded, the development of large-capacity memory devices is proceeding at a rapid speed. Such a large capacity of the memory device is to achieve a high integration based on the micro-process technology that proceeds about twice each generation. In particular, in the manufacture of semiconductor devices, wiring technology is one of the important items in the miniaturization of semiconductor devices. Such a wiring technique is classified into a contact of a polysilicon such as a gate electrode used as a word line of a memory, a contact between a source (drain) diffusion region, and a metal wiring for interconnecting each element.

제1(a)∼(c)도는 종래의 반도체 장치의 제조공정을 나타내는 수직단면도이다.1 (a) to (c) are vertical cross-sectional views showing a manufacturing process of a conventional semiconductor device.

제1(a)도를 참조하면 P형 반도체기판(1)의 표면에 패드산화막(2)과 질화막(3)을 도포한 후 통상의 사진공정에 의해 확산개구(4)를 형성한다. 그 다음 상기 확산개구(4)를 통하여 N형불순물을 이온 주입한 후 드라이브 인(drive in)시켜 도핑영역(5)을 형성한다·Referring to FIG. 1 (a), after the pad oxide film 2 and the nitride film 3 are applied to the surface of the P-type semiconductor substrate 1, the diffusion opening 4 is formed by a normal photographic process. Then, an N-type impurity is implanted through the diffusion opening 4 and then driven in to form a doped region 5.

제1(b)도를 참조하면 상기 패드산화막(2)과 질화막(30)을 제거한다. 그 다음 상기 반도체기판(1)의 표면상에 SiO2같은 절연막(6)을 침적(Deposition)하고 통상의 사진 공정에 의해 상기 도핑영역(5) 상부에 접촉개구(7)를 형성한다.Referring to FIG. 1B, the pad oxide film 2 and the nitride film 30 are removed. Then, an insulating film 6 such as SiO 2 is deposited on the surface of the semiconductor substrate 1 and a contact opening 7 is formed on the doped region 5 by a normal photographic process.

제1(c)도를 참조하면 물리증착방법인 스퍼터링(Sputtering)에 의해 제1밍 제2장벽층(8)(9)을 형성한다. 또한 상기에서 제1장벽층(8)은 Ti로 형성하고, 제2장벽층(9)은 TiN으로 형상한다. 또한 상기 제1장벽층(8)은 상기 접촉개구(7)를 통해 도핑영역(5)과 접촉하게 된다. 그 다음 상기 제2장벽층(9)의 표면에 Al을 스퍼터링 방법에 의해 증착하여 금속배선막(10)을 형성한다.Referring to FIG. 1 (c), the first barrier second barrier layers 8 and 9 are formed by sputtering, which is a physical vapor deposition method. In the above description, the first barrier layer 8 is formed of Ti, and the second barrier layer 9 is formed of TiN. In addition, the first barrier layer 8 comes into contact with the doped region 5 through the contact opening 7. Then, Al is deposited on the surface of the second barrier layer 9 by a sputtering method to form a metal wiring film 10.

그러나 상술한 바와 갈이 형성된 반도체 장치는 열응력이 지속적으로 가해지면 금속배선막을 형성하고있는 Al이 제2장벽층인 TiN을 통해 확산하므로 제1장벽층을 형성하고 있는 Ti와 반응을 하여 복합금속(Intermetallic Compound)을 형성한다. 상기 복합금속은 Si의 용해도보다 크므로 상기 Al과 Si의 원자가 상호확산하여 도핑영역내에 Al 스파이크 생성되어 누설전류를 크게 증가시키는 문제점이 있었다,However, in the semiconductor device formed with the above-described gallium, when the thermal stress is continuously applied, Al forming the metal wiring film diffuses through TiN, which is the second barrier layer, thereby reacting with Ti forming the first barrier layer. (Intermetallic Compound) is formed. Since the composite metal is larger than the solubility of Si, the Al and Si atoms are interdiffused to form Al spikes in a doped region, thereby greatly increasing leakage current.

따라서 본 발명의 목적은 금속 배선막 형성시 도핑영역에서 발생되는 Al 스파이크현상을 방지할 수 있는 반도체장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing Al spike phenomenon occurring in a doped region when forming a metal wiring film.

상기와 같은 목적을 달성하기 위하여 본 발명은 반도체장치의 제조방법에 있어서, 제1도전형의 반도체기판 표면의 일부분에 상기 제1도전형과 반대 도전형인 제2도전형의 도핑영역을 형성하는 공정과, 상기 반도체기판 표면에 절연막을 형성하고 상기 도핑영역상에 개구를 형상하는 공정과, 상기 노출된 반도체기판과 절연막의 상부에 적어도 2층 이상의 장벽층을 형성하고 이온 주입한 후 열처리하는 공정과, 상기 장벽층의 표면에 금속배선막을 형성하는 공정으로 이루어짐을 특징으로 하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a doped region of a second conductive type opposite to the first conductive type on a portion of a surface of the first conductive type semiconductor substrate; Forming an insulating film on the surface of the semiconductor substrate and forming an opening on the doped region, forming at least two or more barrier layers on the exposed semiconductor substrate and the insulating film, and performing heat treatment after ion implantation; And forming a metal wiring film on the surface of the barrier layer.

이하 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2(a)∼(c)도는 본 발명에 따른 반도체 장치의 제조방법의 일 실시예를 나타내는 수직단면도이다.2 (a) to 2 (c) are vertical cross-sectional views showing one embodiment of a method for manufacturing a semiconductor device according to the present invention.

제2(a)도를 참조하면 P형반도체기판(11)에 패드산화막(13)과 질화막(15)을 순차적으로 형성한후 상기 반도체기판(11)의 소정부분에 통상의 사진공정으로 확산개구(17)를 형성한다. 그 다음 상기 확산개구(17)를 통하여 P형반도체기판(11)의 노출된 영역에 N헝 불순물을 도핑하여 도핑영역(19)을 형성한다. 이때 상기불순물의 도핑은 이온 주입법이나 확산방법등으로 행할 수 있다.Referring to FIG. 2 (a), the pad oxide film 13 and the nitride film 15 are sequentially formed on the P-type semiconductor substrate 11, and then the diffusion opening is opened on a predetermined portion of the semiconductor substrate 11 by a normal photographing process. (17) is formed. Then, the doped region 19 is formed by doping the doped region with the N-hung impurities in the exposed region of the P-type semiconductor substrate 11 through the diffusion opening 17. At this time, the doping of the impurity may be performed by an ion implantation method or a diffusion method.

제2(b)도를 참조하면 상기 패드산화막(14)과 질화막(15)을 제거한다 그 다음 상기 반도체기판(11)의 표면상에 SiO2와 같은 절연막(21)을 형성한 후 통상의 사진 방법에 의해 상기 도핑영역(19) 상부에 접촉개구(23)를 형성한다.Referring to FIG. 2 (b), the pad oxide film 14 and the nitride film 15 are removed. Then, after the insulating film 21 such as SiO 2 is formed on the surface of the semiconductor substrate 11, a general photograph is taken. The contact opening 23 is formed on the doped region 19 by the method.

제2(c)도를 참조하면 상기 도핑영역(19)과 절연막(21) 상부에 제1 및 제2장벽층(25)(27)을 스퍼터링이나 진공증착등의 물리적인 증착방법에 의해 순차적으로 형성한다. 상기 제1장벽층(25)은 Ti를 150Å정도의 두께로, 제2장벽층(27)은 TiN을 300Å정도 두께로 형성한다. 또한 제1및 체2장벽층(25)(27)은 스퍼터링에 의해 형성되므로 다결정구조를 갖는다. 그 다음 상기 전술한 구조의 전면에 N이온을 주입한 후 Ar분위기에서 600℃로 급속열처리(Rapid Thermal Annealing)를 행한다, 이때 상기 다결정구조를 갖는 제2장벽층(27)은 상기 N이온의 주입시 충돌에 의해 비정질(Amorphous)구조로 변하여 장벽특성을 향상시키고 스트레스(Stress)를 완화시킨다. 또한 급속열처리시 상기 제2장벽층(27)내에 불안정하게 존재하는 N이온들을 Ti와반응시킴과 동시에 제1장벽층(25)을 형성하는 Ti는 상기 도핑영역(19)과 Si와 반응하여 Ti 실리사이드층(26)을 형성한다. 상기 Ti실리사이드층(26)은 접촉 저항을 개선하여 전기적 특성을 향상시킨다. 그후 상기 제2장벽층(27)의 표면에 Al을 스퍼터링이나 진공증착방법으로 증착시켜 금속배선막(29)을 형성한다. 상기 제2장벽층(27)은 이후 계속되는 열처리공정에 의해 금속배선막(29)을 형성하는 Al이 확산되는 것을 방지한다.Referring to FIG. 2 (c), the first and second barrier layers 25 and 27 are sequentially deposited on the doped region 19 and the insulating layer 21 by physical deposition such as sputtering or vacuum deposition. Form. The first barrier layer 25 has a thickness of about 150 GPa and the second barrier layer 27 has a thickness of about 300 GPa. In addition, the first and second sieve barrier layers 25 and 27 are formed by sputtering and thus have a polycrystalline structure. Then, after injecting N ions to the entire surface of the structure described above, rapid thermal annealing is performed at 600 ° C. in an Ar atmosphere, where the second barrier layer 27 having the polycrystalline structure is implanted with the N ions. It is transformed into amorphous structure by collision at the time to improve barrier property and to relieve stress. In addition, Ti reacts N ions that are unstable in the second barrier layer 27 with Ti during rapid heat treatment, and simultaneously forms Ti as the first barrier layer 25 and Ti reacts with the doped region 19 and Si. The silicide layer 26 is formed. The Ti silicide layer 26 improves electrical resistance by improving contact resistance. Thereafter, Al is deposited on the surface of the second barrier layer 27 by sputtering or vacuum deposition to form a metal wiring film 29. The second barrier layer 27 prevents Al from forming the metal wiring layer 29 from being diffused by a subsequent heat treatment process.

상술한 바와 같이 본 발명은 제2장벽층을 비정질 구조로 변화시켜 금속배선막을 형성하는 Al의 원자가 확산되는 것을 방지하므로 도핑영역에 스파이크의 발생을 억제하여 누설전류를 방지하고 제1장벽층을 실리사이드화하여 접촉저항을 개선하므로 전기적특성을 향상시키고 반도체 장치의 신뢰성을 향상시키는 잇점이있다..As described above, the present invention prevents the diffusion of Al atoms forming the metal interconnection film by changing the second barrier layer into an amorphous structure, thereby suppressing the occurrence of spikes in the doped region to prevent leakage current and silicide the first barrier layer. The contact resistance is improved to improve the electrical characteristics and the reliability of the semiconductor device.

Claims (7)

제1도전형의 반도체기판 표면의 일부분에 상기 제1도전형과 반대 도전형인 제2도전형의 도핑영역을 형성하는 공정과, 상기 반도체 기판 표면에 절연막을 형성하고 상기 도핑영역상에 개구를 형성하는 공정과, 상기 노출된 반도체 기판과 절연막의 상부에 적어도 2층 이상의 장벽층을 형성하는 공정과, 상기 장벽층의 표면에 금속배선막을 형성하는 공정으로 이루어진 반도체 장치의 제조방법에 있어서, 상기 금속배선막을형성하기 전에 상기 장벽층에 이온주입하여 상기 장벽층을 비정질화한 후 열처리하는 공정을 포함함을 특징으로 하는 반도체 장치의 제조방법.Forming a doped region of the second conductive type opposite to the first conductive type on a portion of the surface of the first conductive type semiconductor substrate, forming an insulating film on the surface of the semiconductor substrate and forming an opening in the doped region And a step of forming at least two or more barrier layers on the exposed semiconductor substrate and the insulating film, and forming a metal wiring film on the surface of the barrier layer. And ion-implanting the barrier layer prior to forming the interconnection film to amorphousize the barrier layer and then heat treatment. 제1항에 있어서. 상기 도핑영역을 이온 주입방법 또는 확산 영역으로 형성하는 것을 특징으로 하는반도체 장치의 제조방법The method of claim 1. The method of manufacturing a semiconductor device, characterized in that the doped region is formed by an ion implantation method or a diffusion region. 제1항에 있어서, 상기 장벽층을 Ti로 이루어진 제l장벽층과 TiN으로 이루어진 제2장벽층으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the barrier layer is formed of a first barrier layer made of Ti and a second barrier layer made of TiN. 제3항에 있어서, 상기 제1및 제2장벽층을 스퍼터링 또는 진공증착방법에 의해 형성함을 특징으로 하는 반도체 장치의 제조방법.4. A method according to claim 3, wherein the first and second barrier layers are formed by sputtering or vacuum deposition. 제1항에 있어서, 상기 열처리 공정을 Ar분위기에서 600℃로 하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment step is performed at 600 캜 in an Ar atmosphere. 제5항에 있어서, 상기 열처리 공정시 도핑영역과 제1장벽층사이에 실리사이드층이 형성되어짐을 특징으로 하는 반도체 장치의 제조방법.6. The method of claim 5, wherein a silicide layer is formed between the doped region and the first barrier layer during the heat treatment process. 제1항에 있어서, 상기 금속배선막을 Al로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the metal wiring film is made of Al.
KR1019890020735A 1989-12-31 1989-12-31 Manufacturing process of semiconductor device KR960006430B1 (en)

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