KR100351895B1 - Method for forming bitline in semiconductor device - Google Patents
Method for forming bitline in semiconductor device Download PDFInfo
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- KR100351895B1 KR100351895B1 KR1019990059455A KR19990059455A KR100351895B1 KR 100351895 B1 KR100351895 B1 KR 100351895B1 KR 1019990059455 A KR1019990059455 A KR 1019990059455A KR 19990059455 A KR19990059455 A KR 19990059455A KR 100351895 B1 KR100351895 B1 KR 100351895B1
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- bit line
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- barrier metal
- metal layer
- heat treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
본 발명은 비트라인 콘택부위에 불순물을 추가 도핑한 후, 고온 열처리를 실시하여 도핑된 불순물을 활성화시켜 콘택저항을 감소시키는데 적당한 반도체 소자의 비트라인 형성방법에 관한 것으로, 본 발명의 반도체 소자의 비트라인 형성방법은 P형 불순물 영역이 형성된 반도체 기판상에 비트라인 콘택을 형성하는 제 1 단계와, 상기 비트라인 콘택에 보론(B)이 포함된 이온을 주입하는 제 2 단계와, 1차 고온열처리를 실시하여 상기 주입된 이온을 활성화하는 제 3 단계와, 상기 비트라인 콘택을 포함한 전면에 제 1 베리어 메탈층을 형성하는 제 4 단계와, 2차 고온열처리를 실시하여 비트라인 콘택부위에 실리사이드층을 형성하는 제 5 단계와, 상기 제 1 베리어 메탈층상에 제 2 베리어 메탈층을 형성하는 제 6 단계와, 비트라인을 형성하는 제 7 단계를 포함하여 이루어진다.The present invention relates to a method of forming a bit line of a semiconductor device suitable for reducing contact resistance by activating doped impurities by performing a high temperature heat treatment after further doping an impurity into the bit line contact portion, and the bit of the semiconductor device of the present invention. The line forming method includes a first step of forming a bit line contact on a semiconductor substrate having a P-type impurity region, a second step of implanting ions containing boron (B) into the bit line contact, and a first high temperature heat treatment. Performing a third step of activating the implanted ions, a fourth step of forming a first barrier metal layer on the entire surface including the bit line contacts, and performing a second high temperature heat treatment to form a silicide layer on the bit line contacts. And a fifth step of forming a second barrier metal layer on the first barrier metal layer, and a seventh step of forming a bit line. By made.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 비트라인 콘택의 저항을 감소시키는데 적당한 반도체 소자의 비트라인 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method for forming a bit line of a semiconductor device suitable for reducing the resistance of a bit line contact.
일반적으로 텅스텐 비트라인은 기존의 폴리사이드(폴리실리콘/텅스텐 실리사이드) 비트라인에 비해 라인 저항이 약1/6 이하이므로 디램 셀(DRAM Cell)의 효율(cell efficiency)을 높여 집적도를 증가시킬 수 있을 뿐만 아니라, 로컬 인터커넥션(local interconnection)으로 사용할 수 있으므로 배선층의 수도 감소시킬 수 있으며, 스피트를 향상시키는 여러가지 장점을 가지고 있다.In general, the tungsten bit line has a line resistance of about 1/6 or less compared to the conventional polyside (polysilicon / tungsten silicide) bit line, so that the density of the DRAM cell can be increased by increasing the cell efficiency of the DRAM cell. In addition, since it can be used as a local interconnection (wire interconnection) can reduce the number of wiring layers, and has various advantages of improving the speed.
하지만, 텅스텐 비트라인을 형성함에 있어서, 가장 어려운 점은 비트라인 형성후, 고온 열공정이 많기 때문에 이때 콘택이 열화(콘택 저항 및 정션 리키지)되는 현상이다.However, the most difficult point in forming a tungsten bit line is a phenomenon in which the contact deteriorates (contact resistance and junction liquidity) since there are many high temperature thermal processes after the bit line is formed.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자의 비트라인 형성방법을 설명하기로 한다.Hereinafter, a method of forming a bit line of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 1f는 종래 기술에 따른 반도체 소자의 비트라인 형성방법을 설명하기 위한 공정단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the related art.
도 1a에 도시한 바와 같이, P웰 영역(11a)과 N웰 영역(11b)이 형성된 반도체 기판(11)에 웰(well) 분리를 위한 웰 분리영역(12a)과, 각 웰내의 소자 분리를 위한 소자 격리영역(12b)을 형성한다. 이때, 웰 분리영역(12a) 및 소자 격리영역(12b)은 각각 트렌치 아이솔레이션(trench isolation) 공정을 이용하여 형성한다.As shown in FIG. 1A, a well isolation region 12a for well separation and a device isolation in each well are formed in a semiconductor substrate 11 on which a P well region 11a and an N well region 11b are formed. The device isolation region 12b is formed. In this case, the well isolation region 12a and the device isolation region 12b are formed using a trench isolation process, respectively.
이후, 도 1b에 도시한 바와 같이, 상기 기판(11)상에 복수개의워드라인(13)들을 형성한 후, P웰 영역(11a)의 표면내에 N도전형의 불순물을 주입하여 N+영역(14)을 형성하고, N웰 영역(11b)의 표면내에는 P도전형의 불순물을 주입하여 P+영역(14a)을 형성한다.Thereafter, as illustrated in FIG. 1B, after forming a plurality of word lines 13 on the substrate 11, an N conductive type impurity is implanted into the surface of the P well region 11a to form an N + region ( 14) and a P conductive region is implanted into the surface of the N well region 11b to form the P + region 14a.
도 1c에 도시한 바와 같이, 기판 전면에 층간절연막(15)을 형성한 후, 사진 식각 공정으로 패터닝하여 상기 N+영역(14)과 P+영역(14a)이 노출되도록 제 1, 제 2 비트라인 콘택(16,16a)을 형성한다.As shown in FIG. 1C, the interlayer insulating layer 15 is formed on the entire surface of the substrate, and then patterned by a photolithography process so that the N + 14 and P + regions 14a are exposed. Line contacts 16 and 16a are formed.
이어, 상기 제 1, 제 2 비트라인 콘택(16,16a)을 포함한 기판 전면에 포토레지스트(17)를 도포한 후, 상기 P+영역(14a)이 노출되는 제 2 비트라인 콘택(16a)을 오픈시킨다.Subsequently, after the photoresist 17 is coated on the entire surface of the substrate including the first and second bit line contacts 16 and 16a, the second bit line contact 16a exposing the P + region 14a is exposed. Open it.
이후, 상기 포토레지스트(17)를 마스크로 이용하여 노출된 제 2 비트라인 콘택(16a)을 통해 상기 N웰 영역(11b)의 표면내에 BF2이온주입을 실시한다.Subsequently, BF 2 ion implantation is performed in the surface of the N well region 11b through the exposed second bit line contact 16a using the photoresist 17 as a mask.
이어서, 도 1d에 도시한 바와 같이, 상기 포토레지스트(17)를 제거한 후, 전세정 공정을 실시한 다음, 상기 제 1, 제 2 비트라인 콘택(16,16a)을 포함한 층간절연막(15)상에 제 1 베리어 메탈층(18)을 형성한다.Subsequently, as shown in FIG. 1D, after the photoresist 17 is removed, a pre-cleaning step is performed, and then on the interlayer insulating film 15 including the first and second bit line contacts 16 and 16a. The first barrier metal layer 18 is formed.
이때, 상기 제 1 베리어 메탈층(18)은 티타늄(Ti)과 티타늄 나이트라이드(TiN)의 적층막으로 형성한다.In this case, the first barrier metal layer 18 is formed of a laminated film of titanium (Ti) and titanium nitride (TiN).
이후, RTP공정을 진행하면, 도 1e에 도시한 바와 같이, 상기 제 1, 제 2 비트라인 콘택(16,16a) 부위에 티타늄 실리사이드층(19)이 형성된다.Subsequently, when the RTP process is performed, a titanium silicide layer 19 is formed on the first and second bit line contacts 16 and 16a, as shown in FIG. 1E.
이어서, RTP(Rapid Thermal Process)공정시 티타늄 나이트라이드(TiN)막이 스트레스를 받아 마이크로 크랙(microcrack)이 발생한 것을 보완하기 위해 다시 상기 제 1 베리어 메탈층(18)상에 제 2 베리어 메탈층(20)으로써, 티타늄 나이트라이드막을 형성한다.Subsequently, in order to compensate for the occurrence of the microcrack due to the stress of the titanium nitride (TiN) layer during the rapid thermal process (RTP) process, the second barrier metal layer 20 on the first barrier metal layer 18 again. ) To form a titanium nitride film.
도 1f에 도시한 바와 같이, 기판 전면에 텅스텐층을 형성한 후, 사진 식각 공정을 이용하여 상기 제 1, 제 2 비트라인 콘택을 통해 각각 N+영역(14)과 P+영역(14a)에 연결되는 비트라인(21)들을 형성하면, 종래 기술에 따른 반도체 소자의 비트라인 형성공정이 완료된다.As shown in FIG. 1F, after forming a tungsten layer on the entire surface of the substrate, the photolithography process is performed to the N + region 14 and the P + region 14a through the first and second bit line contacts, respectively. When the bit lines 21 to be connected are formed, the bit line forming process of the semiconductor device according to the prior art is completed.
그러나 상기와 같은 종래 반도체 소자의 비트라인 형성방법은 다음과 같은 문제점이 있었다.However, the bit line forming method of the conventional semiconductor device as described above has the following problems.
첫째, P+영역에만 추가로 이온주입을 실시하더라도 보론의 원소가 물리적으로 실리콘 기판에 주입된 상태일 뿐, 실리콘 원자로 치환한 상태(활성화 상태)가 아니므로 후속 열처리 고온 공정시 도펀트 로스(dopant loss)가 심하다.First, even if the ion implantation is performed only in the P + region, boron elements are physically injected into the silicon substrate, and are not replaced with silicon atoms (active state). ) Is severe.
둘째, 상기 보론 원소로 인하여 실리콘 기판의 저항을 낮추는 효과가 있으나, 이는 활성화 상태일때 보다 덜 효과적이므로 활성화 상태일때보다 콘택 저항이 증가하고, 콘택 형성을 위한 식각공정과 이후의 세정공정 및 베리어 메탈 증착전 세정공정, 그리고 베리어 메탈 증착공정에 민감하게 작용한다.Second, the boron element has the effect of lowering the resistance of the silicon substrate, but it is less effective than in the activated state, the contact resistance is increased than in the activated state, the etching process for forming the contact and the subsequent cleaning process and barrier metal deposition It is sensitive to pre-cleaning and barrier metal deposition.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 비트라인 콘택부위에 불순물을 추가 도핑한 후, 고온 열처리를 실시하여 도핑된 불순물을 활성화시켜 콘택저항을 감소시키는데 적당한 반도체 소자의 비트라인 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and the semiconductor device is suitable for reducing contact resistance by activating the doped impurities by additionally doping impurities into the bit line contact portions, and then performing high temperature heat treatment. The purpose is to provide a line forming method.
도 1a 내지 1f는 종래 기술에 따른 반도체 소자의 비트라인 형성방법을 설명하기 위한 공정단면도1A to 1F are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the related art.
도 2a 내지 2f는 본 발명에 따른 반도체 소자의 비트라인 형성방법을 설명하기 위한 공정단면도2A through 2F are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
31 : 반도체 기판 31a : P웰 영역31 semiconductor substrate 31a P well region
31b : N웰 영역 32a : 웰 분리영역31b: N well region 32a: well isolation region
32b : 소자 격리영역 33 : 워드라인32b: device isolation region 33: word line
34 : N+영역 34a : P+영역34: N + region 34a: P + region
35 : 층간절연막 36,36a : 제 1, 제 2 비트라인 콘택35: interlayer insulating film 36, 36a: first and second bit line contacts
37 : 포토레지스트 38,40 : 제 1, 제 2 베리어 메탈층37: photoresist 38, 40: first and second barrier metal layer
41 : 비트라인41: bit line
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 비트라인 형성방법은 P형 불순물 영역이 형성된 반도체 기판상에 비트라인 콘택을 형성하는 제 1 단계와, 상기 비트라인 콘택에 보론(B)이 포함된 이온을 주입하는 제 2 단계와, 1차 고온열처리를 실시하여 상기 주입된 이온을 활성화하는 제 3 단계와, 상기 비트라인 콘택을 포함한 전면에 제 1 베리어 메탈층을 형성하는 제 4 단계와, 2차 고온열처리를 실시하여 비트라인 콘택부위에 실리사이드층을 형성하는 제 5 단계와, 상기 제 1 베리어 메탈층상에 제 2 베리어 메탈층을 형성하는 제 6 단계와, 비트라인을 형성하는 제 7 단계를 포함하여 이루어지는 것을 특징으로 한다.A bit line forming method of a semiconductor device of the present invention for achieving the above object is a first step of forming a bit line contact on a semiconductor substrate formed with a P-type impurity region, and boron (B) is included in the bit line contact A second step of injecting the implanted ions, a third step of activating the implanted ions by performing a first high temperature heat treatment, and a fourth step of forming a first barrier metal layer on the entire surface including the bit line contacts; Performing a second high temperature heat treatment to form a silicide layer on the bit line contact portion, a sixth step of forming a second barrier metal layer on the first barrier metal layer, and a seventh step of forming a bit line Characterized in that comprises a.
이하, 본 발명 반도체 소자의 비트라인 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of forming a bit line of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 2f는 본 발명 반도체 소자의 비트라인 형성방법을 설명하기 위한 공정단면도이다.2A through 2F are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, P웰 영역(31a)과 N웰 영역(31b)이 형성된 반도체 기판(31)에 웰(well) 분리를 위한 웰 분리영역(32a)과, 각 웰내의 소자 분리를 위한 소자 격리영역(32b)을 형성한다. 이때, 웰 분리영역(32a) 및 소자 격리영역(32b)은 각각 트렌치 아이솔레이션(trench isolation) 공정을 이용하여 형성한다.As shown in FIG. 2A, a well isolation region 32a for well separation and a device isolation in each well are formed on a semiconductor substrate 31 having a P well region 31a and an N well region 31b formed therein. The device isolation region 32b is formed. In this case, the well isolation region 32a and the device isolation region 32b are formed using a trench isolation process, respectively.
이후, 도 2b에 도시한 바와 같이, 상기 기판(31)상에 복수개의 워드라인(33)들을 형성한 후, P웰 영역(31a)의 표면내에 N도전형의 불순물을 주입하여 N+영역(34)을 형성하고, N웰 영역(31b)의 표면내에는 P도전형의 불순물을 주입하여 P+영역(34a)을 형성한다.Subsequently, as shown in FIG. 2B, after forming a plurality of word lines 33 on the substrate 31, an N conductive type impurity is implanted into the surface of the P well region 31 a to form an N + region ( 34) and a P conductive region is implanted into the surface of the N well region 31b to form the P + region 34a.
도 2c에 도시한 바와 같이, 기판 전면에 층간절연막(35)을 형성한 후, 사진 식각 공정으로 패터닝하여 상기 N+영역(34)과 P+영역(34a)이 노출되도록 제 1, 제 2 비트라인 콘택(36,36a)을 형성한다.As shown in FIG. 2C, the interlayer insulating layer 35 is formed on the entire surface of the substrate, and then patterned by a photolithography process so that the N + region 34 and the P + region 34a are exposed. Line contacts 36 and 36a are formed.
이어, 상기 제 1, 제 2 비트라인 콘택(36,36a)을 포함한 기판 전면에 포토레지스트(37)를 도포한 후, 상기 P+영역(34a)이 노출되는 제 2 비트라인 콘택(36a)을 오픈시킨다.Subsequently, after the photoresist 37 is coated on the entire surface of the substrate including the first and second bit line contacts 36 and 36a, the second bit line contact 36a exposing the P + region 34a is exposed. Open it.
이후, 상기 포토레지스트(37)를 마스크로 이용하여 노출된 제 2 비트라인 콘택(36a)을 통해 상기 P+영역(34a)에 BF2이온주입을 실시한다.Thereafter, BF 2 ion implantation is performed to the P + region 34a through the exposed second bit line contact 36a using the photoresist 37 as a mask.
이어서, 상기 포토레지스트를 제거하고, 800℃ 이상의 고온에서 N2+O2또는 Ar+O2와 같은 불활성 기체와 산소를 포함한 혼합기체로 이루어지는 분위기에서 열처리하여 상기 P+영역에 주입된 불순물을 활성화(activation)시킨다.Subsequently, the photoresist is removed and heat-treated in an atmosphere composed of a mixed gas containing oxygen and an inert gas such as N 2 + O 2 or Ar + O 2 at a high temperature of 800 ° C. or higher to activate impurities injected into the P + region. activate.
이와 같이, 불순물을 주입한 후, 불순물을 활성화시키면 후속 열공정시 측면으로 확산되는 현상을 방지하고, 실리콘 기판의 저항을 감소시켜 콘택저항을 감소시킬 수 있다.As such, after the impurity is implanted, activating the impurity can prevent the side diffusion during the subsequent thermal process and reduce the resistance of the silicon substrate to reduce the contact resistance.
단, N2분위기에서만 열처리를 실시하면, 불순물이 활성화됨과 동시에 많은 양의 보론(Boron)이 확산되어 도펀트 로스(dopant loss)가 발생하므로 미량의 산소(O2)를 질소와 혼합한 상태에서 열처리하여야 한다.However, if the heat treatment is performed only in the N 2 atmosphere, impurities are activated and a large amount of boron is diffused to cause dopant loss. Therefore, heat treatment is performed in a state where a small amount of oxygen (O 2 ) is mixed with nitrogen. shall.
이후, 도 2d에 도시한 바와 같이, 세정 공정을 실시한 후, 상기 제 1, 제 2 비트라인 콘택(36,36a)을 포함한 층간절연층(35)상에 제 1 베리어 메탈층(38)을 형성한다.Thereafter, as shown in FIG. 2D, after performing the cleaning process, the first barrier metal layer 38 is formed on the interlayer insulating layer 35 including the first and second bit line contacts 36 and 36a. do.
이때, 상기 제 1 베리어 메탈층(38)은 티타늄(Ti)과 티타늄 나이트라이드(TiN)의 적층막으로 형성한다.In this case, the first barrier metal layer 38 is formed of a laminated film of titanium (Ti) and titanium nitride (TiN).
이어, RTP공정을 진행하면, 도 2e에 도시한 바와 같이, 상기 제 1, 제 2 비트라인 콘택(36,36a) 부위에 티타늄 실리사이드층(39)이 형성된다.Subsequently, when the RTP process is performed, a titanium silicide layer 39 is formed on the first and second bit line contacts 36 and 36a as shown in FIG. 2E.
이어서, RTP(Rapid Thermal Process)공정시 티타늄 나이트라이드(TiN)막이 스트레스를 받아 마이크로 크랙(microcrack)이 발생한 것을 보완하기 위해 상기 제 1 베리어 메탈층(38)상에 다시 제 2 베리어 메탈층(40)으로서, 티타늄 나이트라이드막을 형성한다.도 2f에 도시한 바와 같이, 기판 전면에 텅스텐층을 형성한 후, 사진 식각 공정을 이용하여 상기 제 1, 제 2 비트라인 콘택(36,36a)을 통해 각각 N+영역(34)과 P+영역(34a)에 연결되는 비트라인(41)들을 형성하면, 본 발명에 따른 반도체 소자의 비트라인 형성공정이 완료된다.Subsequently, the second barrier metal layer 40 is again on the first barrier metal layer 38 to compensate for the occurrence of the microcrack due to the stress of the titanium nitride (TiN) layer during the rapid thermal process (RTP) process. As shown in FIG. 2F, a tungsten layer is formed on the entire surface of the substrate, and then through the first and second bit line contacts 36 and 36a using a photolithography process. If the bit lines 41 connected to the N + region 34 and the P + region 34a are formed, respectively, the bit line forming process of the semiconductor device according to the present invention is completed.
한편, 본 발명의 다른 실시예로써는 불순물 이온주입 후, 불순물을 활성화시키기 위해 RTP공정을 사용하지 않고, 기존 공정 그대로 비트라인을 형성한 다음, NO막을 유전막으로 사용할 경우, 커패시터 상부전극으로 사용하는 도프트 폴리실리콘의 활성화 온도를 고온화하는 방법이 있다.Meanwhile, in another embodiment of the present invention, after implanting impurity ions, without using the RTP process to activate the impurity, forming a bit line as it is, and then using a NO film as a dielectric film, the dope is used as a capacitor upper electrode. There is a method of increasing the activation temperature of polypolysilicon.
이렇게 하면, 비트라인 콘택부위에 실리사이드층을 형성하거나 커패시터 형성을 위한 고온 열공정시 불순물의 확산을 방지할 수는 없지만, 주입된 불순물을 활성화시킴으로써, 콘택저항을 감소시킬 수는 있다. 실제로 P+영역에 주입된 불순물의 농도는 충분히 높으므로 확산이 일어나더라도 콘택저항에 큰 영향을 주지 않기 때문이다.In this case, it is not possible to prevent the diffusion of impurities during the formation of the silicide layer on the bit line contact portion or during the high temperature thermal process for forming the capacitor, but it is possible to reduce the contact resistance by activating the implanted impurities. In fact, the concentration of impurities implanted in the P + region is high enough, so that diffusion does not significantly affect the contact resistance.
이상 상술한 바와 같이, 본 발명에 따른 반도체 소자의 비트라인 형성방법은 다음과 같은 효과가 있다.As described above, the bit line forming method of the semiconductor device according to the present invention has the following effects.
첫째, 비트라인 콘택 저항을 최소화할 수 있으므로 후속 열처리 공정 마진(margin)을 확보할 수 있으며, 주변 공정에 의한 열화가 있더라도 콘택저항에 대한 충분한 마진을 제공하므로 반도체 소자의 수율향상과 스피트 개선에 기여한다.First, the margin of the bit line contact can be minimized to secure the margin of the subsequent heat treatment process, and it provides a sufficient margin for the contact resistance even if there is deterioration by the surrounding process, contributing to the improvement of the yield and the speed of the semiconductor device. do.
둘째, 추가 이온주입 후, RTP공정에 의한 열처리 공정은 별도의 추가 공정으로 실시하는 것이 아니라 디램 제조공정중 비트라인 형성전에 실시하는 도프트 폴리-실리콘 활성화를 위한 열처리 공정을 단지 뒤쪽으로 미루어 실시하는 것이 되므로 공정이 추가되지는 않는다.Second, after the additional ion implantation, the heat treatment process by RTP process is not performed as a separate additional process, but only after the heat treatment process for activating doped poly-silicon which is performed before forming the bit line in the DRAM manufacturing process. Process is not added.
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