KR20010044869A - Method of forming a metal contact in a semiconductor device - Google Patents

Method of forming a metal contact in a semiconductor device Download PDF

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Publication number
KR20010044869A
KR20010044869A KR1019990047912A KR19990047912A KR20010044869A KR 20010044869 A KR20010044869 A KR 20010044869A KR 1019990047912 A KR1019990047912 A KR 1019990047912A KR 19990047912 A KR19990047912 A KR 19990047912A KR 20010044869 A KR20010044869 A KR 20010044869A
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South Korea
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forming
junction part
contact hole
junction
semiconductor device
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KR1019990047912A
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Korean (ko)
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이정호
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990047912A priority Critical patent/KR20010044869A/en
Publication of KR20010044869A publication Critical patent/KR20010044869A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for manufacturing a metal contact of a semiconductor device is provided to control dopant diffusion in a process for forming a silicide layer to maintain high doping density of a junction part, by arbitrarily causing physical and chemical damage to the junction part, so that the high doping density of the junction part is maintained and only diffusion capacity of the junction part is reduced. CONSTITUTION: A silicon substrate(11) is prepared which has a contact hole in a junction part(13). The surface of the junction part exposed by the contact hole is processed with argon plasma so that diffusion capacity of the junction part decreases while the junction part maintains an electrical characteristic of a dopant. A barrier metal layer(18) is formed on the entire structure including the contact hole. After a silicide layer(19) is formed on the surface of the junction part by a heat treatment process, and a tungsten plug(20) is formed inside the contact hole.

Description

반도체 소자의 금속 콘택 형성방법{Method of forming a metal contact in a semiconductor device}Method of forming a metal contact in a semiconductor device

본 발명은 반도체 소자의 금속 콘택 형성방법에 관한 것이다.The present invention relates to a method for forming a metal contact of a semiconductor device.

일반적으로, 반도체 소자가 고집적화 되어감에 따라 콘택 저항을 개선시키는 방안이 연구되어지고 있다. 최근 널리 적용되고 있는 콘택 저항 개선방안으로 콘택 홀 저면의 콘택 부위에 실리사이드층을 형성하는 방안이 있다.In general, as semiconductor devices are highly integrated, a method of improving contact resistance has been studied. As a method of improving contact resistance, which has been widely applied in recent years, there is a method of forming a silicide layer on a contact portion of a bottom of a contact hole.

종래 반도체 소자의 금속 콘택 형성방법을 첨부도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional method for forming a metal contact of a semiconductor device is as follows.

도 1a 내지 도 1c는 종래 반도체 소자의 금속 콘택 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a metal contact formation method of a conventional semiconductor device.

도 1a를 참조하면, 실리콘 기판(1) 상에 높은 농도로 도핑된 접합부(3)를 갖는 트랜지스터(2)을 형성한 후 제 1 층간절연막(4) 및 제 2 층간절연막(5)을 형성한다. 그후 콘택 홀이 형성될 영역이 개방된 감광막 패턴(6)을 제 2 층간절연막(5) 상에 형성한다.Referring to FIG. 1A, after forming a transistor 2 having a junction 3 doped at a high concentration on a silicon substrate 1, a first interlayer insulating film 4 and a second interlayer insulating film 5 are formed. . Thereafter, a photosensitive film pattern 6 having an open area where a contact hole is to be formed is formed on the second interlayer insulating film 5.

도 1b를 참조하면, 감광막 패턴(6)을 마스크로 이용한 건식식각공정으로 제 2 및 1 층간절연막(5 및 4)을 식각하여 접합부(3)가 노출된 콘택 홀(7)을 형성한 후 감광막 패턴(6)을 제거한다. 콘택 홀(7)을 포함한 전체 구조상에 Ti 및 TiN을 증착 시켜 장벽 금속층(8)을 형성한다.Referring to FIG. 1B, the second and first interlayer insulating layers 5 and 4 are etched by a dry etching process using the photoresist pattern 6 as a mask to form a contact hole 7 through which the junction 3 is exposed, and then the photoresist layer. Remove the pattern (6). The barrier metal layer 8 is formed by depositing Ti and TiN on the entire structure including the contact hole 7.

도 1c는 열처리 공정을 실시하여 접합부(3) 표면에 실리사이드층(9)을 형성한 후, 콘택 홀(7) 내에 텅스텐 플러그(10)를 형성한다.In FIG. 1C, a silicide layer 9 is formed on the surface of the junction part 3 by performing a heat treatment process, and then a tungsten plug 10 is formed in the contact hole 7.

상기에서, 실리사이드층 형성공정시 높은 농도로 도핑된 접합부의 도펀트는 실리사이드층으로 확산되어 들어가는 경향이 있다. 이로인해 접합부의 도펀트는 접합부의 도핑 농도 감소를 초래하게 되어 콘택 저항이 증가되는 문제가 있다.In the above, the dopant of the junction doped at a high concentration during the silicide layer forming process tends to diffuse into the silicide layer. As a result, the dopant of the junction causes a decrease in the doping concentration of the junction, thereby increasing the contact resistance.

따라서, 본 발명은 실리사이드층 형성시 접합부의 도펀트가 실리사이드층으로 확산되는 것을 억제시켜 콘택 저항이 증가되는 것을 방지할 수 있는 반도체 소자의 금속 콘택 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal contact of a semiconductor device capable of preventing diffusion of a dopant in a junction into a silicide layer when the silicide layer is formed, thereby preventing an increase in contact resistance.

상기한 목적을 달성하기 위한 본 발명은 접합부에 콘택 홀이 형성된 실리콘 기판이 제공되는 단계; 상기 콘택 홀을 통해 노출된 상기 접합부 표면을 아르곤 플라즈마 처리하고, 이로 인하여 상기 접합부는 도펀트의 전기적 특성을 유지하면서 확산 능력이 저하된 상태가 되는 단계; 상기 콘택 홀을 포함한 전체구조상에 장벽 금속층을 형성하는 단계; 및 열처리공정으로 상기 접합부 표면에 실리사이드층을 형성한 후 상기 콘택 홀 내에 텅스텐 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 한다.The present invention for achieving the above object is a step of providing a silicon substrate with a contact hole formed in the junction; Argon plasma treatment of the surface of the junction exposed through the contact hole, whereby the junction is in a state in which its diffusion ability is reduced while maintaining electrical properties of a dopant; Forming a barrier metal layer on the entire structure including the contact hole; And forming a tungsten plug in the contact hole after forming a silicide layer on the surface of the junction part by a heat treatment process.

도 1a 내지 도 1c는 종래 반도체 소자의 금속 콘택 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a metal contact formation method of a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 콘택 형성방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a metal contact forming method of a semiconductor device according to the present invention.

〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>

1 및 11 : 실리콘 기판 2 및 12 : 트랜지스터1 and 11: silicon substrate 2 and 12: transistor

3 및 13 : 접합부 4 및 14 : 제 1 층간절연막3 and 13 junction 4 and 14 first interlayer insulating film

5 및 15 : 제 2 층간절연막 6 및 16 : 감광막 패턴5 and 15: second interlayer insulating film 6 and 16: photosensitive film pattern

7 및 17 : 콘택 홀 8 및 18 : 장벽금속층7 and 17: contact holes 8 and 18: barrier metal layer

9 및 19 : 실리사이드층 10 및 20 : 텅스텐 플러그9 and 19: silicide layer 10 and 20: tungsten plug

100 : 아르곤 플라즈마100: argon plasma

이하, 첨부한 도면을 참조하여 본 발명은 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 콘택 형성방법을 설명하기 위한 소자의 단면도이다.2A to 2C are cross-sectional views of devices for explaining a method for forming a metal contact of a semiconductor device according to the present invention.

도 2a를 참조하면, 실리콘 기판(11) 상에 높은 농도로 도핑된 접합부(13)를 갖는 트랜지스터(12)을 형성한 후 제 1 층간절연막(14) 및 제 2 층간절연막(15)을 형성한다. 그후 콘택 홀이 형성될 영역이 개방된 감광막 패턴(16)을 제 2 층간절연막(15) 상에 형성한다.Referring to FIG. 2A, after forming a transistor 12 having a junction 13 doped at a high concentration on a silicon substrate 11, a first interlayer insulating film 14 and a second interlayer insulating film 15 are formed. . Thereafter, a photosensitive film pattern 16 having an open area where a contact hole is to be formed is formed on the second interlayer insulating film 15.

도 2b를 참조하면, 감광막 패턴(16)을 마스크로 이용한 건식 식각공정으로 제 2 및 1 층간절연막(15 및 14)을 식각하여 접합부(13)가 노출된 콘택 홀(17)을 형성한 후 아르곤 플라즈마(100)를 이용하여 콘택 홀(17) 내부를 프라즈마 처리한다. 상기에서, 아르곤 플라즈마(100)는 400 내지 500W 의 고주파 전력으로 형성한다. 아르곤 플라즈마(100) 처리에 의해 접합부(13)의 표면은 물리적, 화학적 손상을 입게되고, 이로인하여 접합부(13)는 주입된 활성 도판트의 전기적 특성은 그대로 유지되면서 확산 능력만 저하된 상태가 된다.Referring to FIG. 2B, the second and first interlayer insulating layers 15 and 14 are etched by a dry etching process using the photoresist pattern 16 as a mask to form a contact hole 17 in which the junction 13 is exposed, and then argon. The plasma 100 is used to plasma-process the inside of the contact hole 17. In the above, the argon plasma 100 is formed of a high frequency power of 400 to 500W. The argon plasma 100 treatment causes the surface of the junction 13 to be physically and chemically damaged. As a result, the junction 13 is in a state where only the diffusion ability is reduced while maintaining the electrical characteristics of the implanted active dopant. .

도 2c를 참조하면, 감광막 패턴(16)을 제거한 후 콘택 홀(17)을 포함한 전체구조상에 Ti 및 TiN을 증착시켜 장벽금속층(18)을 형성한다. 이후, 열처리공정을 실시하여 접합부(13)의 표면에 실리사이드층(19)을 형성하고, 콘택 홀(17) 내에 텅스텐 플러그(20)를 형성한다.Referring to FIG. 2C, after removing the photoresist pattern 16, the barrier metal layer 18 is formed by depositing Ti and TiN on the entire structure including the contact hole 17. Thereafter, a heat treatment process is performed to form a silicide layer 19 on the surface of the junction 13 and to form a tungsten plug 20 in the contact hole 17.

상기에서, Ti/TiN 장벽금속층(18)은 물리적 기상증착(PVD), 화학 기상증착 (CVD) 및 이온 금속 플라즈마(IMP;ionized metal plasma) 방법 중 어느 하나의 방법을 이용하여 1000 내지 1500Å 두께로 형성한다. 열처리공정은 600 내지 800℃에서 10 내지 30 초 동안 실시한다.In the above, the Ti / TiN barrier metal layer 18 has a thickness of 1000 to 1500 Å using any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and ionized metal plasma (IMP) method. Form. The heat treatment process is carried out at 600 to 800 ℃ for 10 to 30 seconds.

상술한 바와 같이 본 발명은 콘택 홀 형성후 아르곤 플라즈마를 처리하여 접합부에 물리적, 화학적 손상을 임의로 주어 접합부에 주입된 활성 도펀트의 전기적 특성은 그대로 유지하면서 확산 능력만 저하되게 함으로써, 실리사이드층 형성공정시 도펀트 확산이 억제되어 접합부의 높은 도핑 농도를 유지할 수 있게 하여 반도체 소자의 콘택 저항을 감소 시킬 수 있다.As described above, the present invention treats argon plasma after forming a contact hole, thereby physically and chemically damaging the junction to reduce the diffusion ability while maintaining the electrical properties of the active dopant implanted at the junction. Dopant diffusion can be suppressed to maintain a high doping concentration of the junction, thereby reducing the contact resistance of the semiconductor device.

Claims (4)

접합부에 콘택 홀이 형성된 실리콘 기판이 제공되는 단계;Providing a silicon substrate having contact holes formed in the junction; 상기 콘택 홀을 통해 노출된 상기 접합부 표면을 아르곤 플라즈마 처리하고, 이로 인하여 상기 접합부는 도펀트의 전기적 특성을 유지하면서 확산 능력이 저하된 상태가 되는 단계;Argon plasma treatment of the surface of the junction exposed through the contact hole, whereby the junction is in a state in which its diffusion ability is reduced while maintaining electrical properties of a dopant; 상기 콘택 홀을 포함한 전체구조상에 장벽 금속층을 형성하는 단계; 및Forming a barrier metal layer on the entire structure including the contact hole; And 열처리공정으로 상기 접합부 표면에 실리사이드층을 형성한 후 상기 콘택 홀 내에 텅스텐 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.And forming a tungsten plug in the contact hole after forming a silicide layer on the surface of the junction part by a heat treatment process. 제 1 항에 있어서,The method of claim 1, 상기 아르곤 플라즈마는 400 내지 500W 의 고주파 전력으로 형성하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.The argon plasma is a metal contact forming method of a semiconductor device, characterized in that for forming a high frequency power of 400 to 500W. 제 1 항에 있어서,The method of claim 1, 상기 장벽금속층은 물리적 기상증착, 화학적 기상증착 및 이온화 금속 플라즈마 방법 중 어느 하나의 방법을 이용하여 Ti 및 TiN을 1000 내지 1500Å 두께로 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.The barrier metal layer is formed by depositing Ti and TiN to a thickness of 1000 to 1500Å by any one of physical vapor deposition, chemical vapor deposition and ionized metal plasma method. 제 1 항에 있어서,The method of claim 1, 상기 실리사이드층은 600 내지 800℃에서 10 내지 30 초 동안 열처리공정을 실시하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.The silicide layer is formed by performing a heat treatment process for 10 to 30 seconds at 600 to 800 ℃ metal contact forming method of a semiconductor device.
KR1019990047912A 1999-11-01 1999-11-01 Method of forming a metal contact in a semiconductor device KR20010044869A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7169704B2 (en) 2002-06-21 2007-01-30 Samsung Electronics Co., Ltd. Method of cleaning a surface of a water in connection with forming a barrier layer of a semiconductor device
KR100730472B1 (en) * 2001-06-28 2007-06-19 매그나칩 반도체 유한회사 Fabricating method of image sensor
US9685527B2 (en) 2015-02-17 2017-06-20 Samsung Electronics Co., Ltd. Methods of forming metal silicide layers including dopant segregation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100730472B1 (en) * 2001-06-28 2007-06-19 매그나칩 반도체 유한회사 Fabricating method of image sensor
US7169704B2 (en) 2002-06-21 2007-01-30 Samsung Electronics Co., Ltd. Method of cleaning a surface of a water in connection with forming a barrier layer of a semiconductor device
US7452810B2 (en) 2002-06-21 2008-11-18 Samsung Electronics Co., Ltd. Method of forming a barrier layer of a semiconductor device
US9685527B2 (en) 2015-02-17 2017-06-20 Samsung Electronics Co., Ltd. Methods of forming metal silicide layers including dopant segregation

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