KR930011113B1 - Manufacturing method of contact plug for semiconductor device - Google Patents
Manufacturing method of contact plug for semiconductor device Download PDFInfo
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- KR930011113B1 KR930011113B1 KR1019910011259A KR910011259A KR930011113B1 KR 930011113 B1 KR930011113 B1 KR 930011113B1 KR 1019910011259 A KR1019910011259 A KR 1019910011259A KR 910011259 A KR910011259 A KR 910011259A KR 930011113 B1 KR930011113 B1 KR 930011113B1
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- Prior art keywords
- layer
- forming
- silicon
- contact hole
- silicon layer
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000003213 activating effect Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 230000008018 melting Effects 0.000 claims description 12
- 238000002844 melting Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000012535 impurity Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
제1a~e도는 종래 기술에 따른 접촉플러그 제조공정도.Figure 1a to e is a contact plug manufacturing process according to the prior art.
제2a~e도는 이 발명에 따른 접촉플러그 제조공정도.2a to e is a contact plug manufacturing process according to the present invention.
제3도는 이 발명에 따른 다른 실시예의 접촉플러그 단면도.3 is a cross-sectional view of a contact plug of another embodiment according to the present invention.
제4a~b도는 이 발명에 따른 또다른 실시예의 접촉플러그 제조공정도이다.Figures 4a to b is a manufacturing process of the contact plug of another embodiment according to the present invention.
이 발명은 반도체장치의 접촉플러그 제조방법에 관한 것으로, 특히 애스팩트비(aspect ratio)가 큰 반도체장치의 접촉플러그(confacf plug)의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a contact plug of a semiconductor device, and more particularly, to a method of manufacturing a contact plug of a semiconductor device having a large aspect ratio.
최근 반도체 제조기술의 발달과 반도체장치의 고집적화 추세에 따라 반도체장치가 소형화, 경량화 되어가고 있으며, 또한 접촉플러그를 소형화하고 접촉 효율을 높이기 위한 연구가 활발히 진행되고 있다. 특히 접촉구(cantact hole)가 1㎛ 이하의 크기로 감소되고 애스팩트비가 급격히 증가되면 금속배선층과 반도체기판과의 접촉이 반도체장치의 효율과 신뢰성에 큰 영향을 미치게 된다.Recently, with the development of semiconductor manufacturing technology and the trend of high integration of semiconductor devices, semiconductor devices have become smaller and lighter, and researches for miniaturizing contact plugs and improving contact efficiency have been actively conducted. In particular, when the contact hole is reduced to a size of 1 μm or less and the aspect ratio is rapidly increased, the contact between the metallization layer and the semiconductor substrate greatly affects the efficiency and reliability of the semiconductor device.
제1a~e도는 종래 기술에 따른 접촉플러그의 제조공정도이다. 제1a도를 참조하면, 반도체기판(1)상에 통상의 방법으로 반도체기판과 다른 도전형을 가지는 확산영역(2)을 형성한다. 그후, SiO2및 BPSG등으로 절연막(3)을 형성하며, 상기 절연막(3)상에 포토레지스트 패턴을 형성한다. 그다음, 상기 포토레지스트패턴을 식각마스크로 하여 상기 절연막(3)의 노출된 부분을 제거하여 접촉구(5)를 형성한 후 포토레지스터패턴을 제거한다. 제1d도를 참조하면, 상기 절연막(3)의 상부에 CVD(Chemical Vapor Deposition)방법으로 확산영역(2)과 같은 도전형의 불순물로 도핑된 다결정실리콘층(9)을 접촉구(5)가 매몰되도록 형성한다. 그다음, 상기 다결정실리콘층(9)의 상부에 Ti, W, Co 및 Pt등의 고융점 금속을 물리증착등의 방법으로 제1금속층(11)을 형성한다. 제1c도를 참조하면, 상기 다결정실리콘층(9)과 제1금속층(11)을 열처리등의 방법으로 실리사이드화하여 제1실리사이드층(12)을 형성한다. 제1b도를 참조하면, 상기 제1실리사이드층을 에치백(etch back)하여 절연막(3)을 노출시킨다. 그다음, 상기 접촉구(5)내의 다결정실리콘층(9)을 실리사이드화하기 위한 제2금속층(14)을 물리증착등의 방법으로 형성한다. 제1e도를 참조하면, 상기 구조의 다결정실리콘층(9)과 제2금속층(14)을 열처리등의 방법으로 실리사이드화하여 접촉플러그(15)를 형성한다. 이때 접촉플러그(15)의 하부에 실리사이드화하지 않은 다결정실리콘층(9)이 남게 된다.1a to e is a manufacturing process diagram of the contact plug according to the prior art. Referring to FIG. 1A, a diffusion region 2 having a conductivity type different from that of a semiconductor substrate is formed on the semiconductor substrate 1 in a conventional manner. Thereafter, an insulating film 3 is formed of SiO 2 , BPSG, or the like, and a photoresist pattern is formed on the insulating film 3. Next, the exposed portion of the insulating layer 3 is removed using the photoresist pattern as an etching mask to form the contact hole 5, and then the photoresist pattern is removed. Referring to FIG. 1D, the contact hole 5 is formed on the insulating layer 3 by a polycrystalline silicon layer 9 doped with a conductive impurity such as the diffusion region 2 by a chemical vapor deposition (CVD) method. Form to be buried. Then, the first metal layer 11 is formed on the polycrystalline silicon layer 9 by a method such as physical vapor deposition of high melting point metals such as Ti, W, Co, and Pt. Referring to FIG. 1C, the polysilicon layer 9 and the first metal layer 11 are silicided by a method such as heat treatment to form the first silicide layer 12. Referring to FIG. 1B, the insulating layer 3 is exposed by etching back the first silicide layer. Then, the second metal layer 14 for silicideing the polysilicon layer 9 in the contact hole 5 is formed by physical vapor deposition or the like. Referring to FIG. 1E, the contact silicon 15 is formed by silicidating the polysilicon layer 9 and the second metal layer 14 having the above structure by a heat treatment method. At this time, the polysilicon layer 9 not silicided remains at the bottom of the contact plug 15.
상기 종래기술에 의한 접촉플러그 제조방법은 확산영역과 금속실리사이드층과의 사이에 실리사이드화하지 않은 다결정실리콘층이 남게되어 접촉면의 직렬기생 저항이 커지는 문제점이 있었다. 또한 확산영역과 금속실리사이드 접합면의 직렬기생 저항이 커지는 문제점이 있었다. 또한 확산영역과 금속실리사이드 접합면의 직렬기생 저항을 감소시키기 위해 상기 다결정실리콘층을 확산영역과 같은 도전형의 불순물로 도핑하여야 하는 등 공정이 복잡한 등의 문제점이 있었다. 따라서 이 발명의 목적은 간단한 공정으로 확산영역과 금속실리사이드층과의 접촉면을 균일하게 형성하여 접합면의 직렬기생저항을 감소시킬 수 있는 반도체장치의 접촉플러그 그 제조방법을 제공함에 있다.According to the conventional method of manufacturing a contact plug, there is a problem in that a series parasitic resistance of a contact surface is increased because a non-silicided polysilicon layer remains between a diffusion region and a metal silicide layer. In addition, there is a problem that the series parasitic resistance between the diffusion region and the metal silicide junction surface increases. In addition, in order to reduce the series parasitic resistance of the diffusion region and the metal silicide junction surface, the polysilicon layer needs to be doped with a conductive impurity such as the diffusion region. Accordingly, an object of the present invention is to provide a method for manufacturing a contact plug of a semiconductor device which can reduce the series parasitic resistance of the junction surface by uniformly forming a contact surface between the diffusion region and the metal silicide layer in a simple process.
상기와 같은 목적을 달성하기 위하여 이 발명은 반도체장치의 제조방법에 있어서, 반도체 기판상에 반도체 기판과 다른 도전형의 불순물로 확산영역을 형성하는 과정과, 상기 반도체기판의 상부에 절연막을 형성하는 과정과, 상기 절연막의 소정부분을 제거하여 확산영역이 노출되도록 접촉구를 형성하는 과정과, 상술한 구조의 전표면에 실리콘층을 형성하고 고융점 금속의 이온주입층을 형성한후 열처리하여 실리 사이드화하는 공정을 적어도 1회 이상 반복하는 과정과, 상기 금속실리사이드층의 상부에 상기 접촉구가 메워지도록 실리콘층을 형성하는 과정과, 상기 접촉구를 제외한 실리콘층 및 금속실리사이드층을 제거하는 공정과, 상기 접촉구를 메운 실리콘층을 고융점 금속의 이온주입층을 형성하는 과정과, 상기 이온주입층의 금속이온을 활성화시켜 실리콘층을 실리사이드화하는 과정으로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a diffusion region on a semiconductor substrate with impurities of a conductivity type different from that of a semiconductor substrate, and forming an insulating film on the semiconductor substrate; Forming a contact hole to expose the diffusion region by removing a predetermined portion of the insulating film, forming a silicon layer on the entire surface of the above-described structure, forming an ion implantation layer of a high melting point metal, and then performing heat treatment Repeating the step of at least one or more times, forming a silicon layer so that the contact hole is filled in the upper portion of the metal silicide layer, and removing the silicon layer and the metal silicide layer except for the contact hole. And forming an ion implantation layer of a high melting point metal in the silicon layer filling the contact hole, and activating a metal ion of the ion implantation layer. It is characterized by consisting of a process of silicidating the silicon layer by the formation.
상기와 같은 목적을 달성하기 위해 이 발명은 또한, 반도체기판의 소정부분에 반도체기판과 다른 도전형의 불순물로 확산영역을 형성하는 과정과, 상기 반도체기판의 상부에 절연막을 형성하는 과정과, 절연막의 소정부분을 제거하여 접촉구를 형성하는 과정과, 상기 확산영역의 상부에 선택적 에피층을 형성하고 고융점 금속의 이온주입층을 형성하는 공정을 1회 이상 반복하는 과정과, 상기 이온주입층을 열처리하여 선택적 에피층을 실리사이드화하는 과정으로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention also provides a process for forming a diffusion region with impurities of a conductivity type different from a semiconductor substrate in a predetermined portion of the semiconductor substrate, forming an insulating film on the semiconductor substrate, and Forming a contact hole by removing a predetermined portion of the method, repeating a process of forming a selective epitaxial layer on the diffusion region and forming an ion implantation layer of a high melting point metal one or more times, and the ion implantation layer Heat-treating the selective epitaxial layer.
이하, 첨부한 도면을 참조하여 이 발명을 상세하게 설명한다.Hereinafter, this invention is demonstrated in detail with reference to attached drawing.
제2a~e도는 이 발명에 따른 접촉플러그 제조방법의 일실시예를 나타내는 공정도이다. 제2a도를 참조하면, 반도체기판(21)의 소정부분의 표면에 이온주입 및 확산등의 방법으로 반도체기판(21)과 다른 도전형의 확산영역(22)을 형성한다. 그 다음, 상기 반도체기판(21)상에 SiO2및 BPSG등의 절연막(23)을 형성하고, 상기 절연막(23)의 상부에 포토레지스트 패턴을 형성한다. 그다음, 상기 절연막(23)의 노출된 부분을 제거하여 확산영역(22)의 상부에 접촉구(25)를 형성한 후, 상기 포토레지스트 패턴을 제거한다. 제2b도를 참조하면, 상기 절연막(23)과 접촉구(25) 내벽의 표면에 다결정실리콘 또는 비정질실리콘을 CVD 방법으로 침적하여 제1실리콘층(29)을 형성하며, 상기 제1실리콘층(29)을 실리사이드화 시킬 Ti, W, Co 또는 Pt등의 고융점 금속이온을 주입하여 제1금속 이온층(31)을 형성한다. 이때 제1금속이온층(31)은 제1실리콘층(29)을 완전히 실리사이드화할 수 있는 금속이온량을 주입하여야 한다.2a to e are process drawings showing an embodiment of the method for manufacturing a contact plug according to the present invention. Referring to FIG. 2A, a diffusion type 22 having a conductivity type different from that of the semiconductor substrate 21 is formed on the surface of a predetermined portion of the semiconductor substrate 21 by ion implantation and diffusion. Next, an insulating film 23 such as SiO 2 and BPSG is formed on the semiconductor substrate 21, and a photoresist pattern is formed on the insulating film 23. Next, the exposed portion of the insulating layer 23 is removed to form the contact hole 25 on the diffusion region 22, and then the photoresist pattern is removed. Referring to FIG. 2B, the first silicon layer 29 is formed by depositing polysilicon or amorphous silicon on the surfaces of the insulating layer 23 and the contact hole 25 by a CVD method, and forming the first silicon layer ( 29) to form the first metal ion layer 31 by implanting high melting point metal ions such as Ti, W, Co or Pt. In this case, the first metal ion layer 31 should be injected with the amount of metal ions that can completely silicide the first silicon layer 29.
제2c도를 참조하면, 상기 제1금속이온층(31)의 금속이온들을 열처리등의 방법으로 활성화시켜 상기 제1다결정실리콘층(29)을 실리사이드화하여 제1실리사이드층(33)을 형성한다. 그다음, 제1실리사이드층(33)의 상부에 다결정실리콘 또는 비정질실리콘을 CVD 방법으로 침적하여 제2실리콘층(35)을 형성한다. 이때 제2실리콘층(35)은 접촉구(25)를 완전히 매몰시킨다. 제2d도를 참조하면, 상기 제2실리콘층(35) 및 제1실리사이드층(33)을 에치백하여 절연막(23)의 상부를 노출시킨다. 이때 상기 개구부(25)내에는 제2다결정실리콘층(35)이 남아있게 된다. 그다음, 상기 구조의 전표면에 고융점 금속이온을 주입하여 제2금속이온층(39)을 형성한다. 상기 이온주입 공정시 마스크가 없으므로 이온주입 에너지를 적당히 조절하여 금속이온이 절연막(23) 또는 제1실리사이층(33) 및 접촉구(25)를 메운 제2실리콘층(37)을 관통하여 반도체기판(21)과 확산영역(22)에 주입되지 않도록 한다. 제2e도를 참조하면, 상기 제2금속이온층(39)의 금속이온들을 열처리 방법으로 활성화시켜 실리사이드화하여 제2실리사이층(40)을 형성한다. 상기에서 제1 및 제2금속실리사이드층들(33), (40)은 접촉플러그(41)가 된다.Referring to FIG. 2C, the first polycrystalline silicon layer 29 is silicided by activating metal ions of the first metal ion layer 31 by heat treatment or the like to form a first silicide layer 33. Next, polysilicon or amorphous silicon is deposited on the first silicide layer 33 by CVD to form a second silicon layer 35. At this time, the second silicon layer 35 completely embeds the contact hole 25. Referring to FIG. 2D, the upper portion of the insulating layer 23 is exposed by etching back the second silicon layer 35 and the first silicide layer 33. At this time, the second polysilicon layer 35 remains in the opening 25. Next, a high melting point metal ion is implanted into the entire surface of the structure to form a second metal ion layer 39. Since there is no mask during the ion implantation process, the ion implantation energy is appropriately controlled so that the metal ion penetrates the insulating layer 23 or the first silicon layer 33 and the second silicon layer 37 filling the contact hole 25 to form a semiconductor. It is not injected into the substrate 21 and the diffusion region 22. Referring to FIG. 2E, the metal ions of the second metal ion layer 39 are silicided by activation by heat treatment to form a second silicide layer 40. In the above, the first and second metal silicide layers 33 and 40 become contact plugs 41.
제3도는 이 발명에 따른 접촉플러그 제조방법의 다른 실시예를 나타내는 단면도이다. 제3도는 애스팩트비가 제2a~e도의 경우보다 큰 접촉구에 접촉플러그를 형성한것을 나타낸다. 제3도를 참조하면, 제3도는 제2e도에 상응하는 도면으로서 애스팩트비가 상대적으로 커서 제2실리콘층으로 접촉구(25)를 매몰할 경우 제2실리콘층에 고융점금속을 이온주입하여도 실리사이드화하지 않는 실리콘의 부분이 많아지게 된다. 제2a도와 같은 방법으로 반도체기판(21)의 상부에 확산영역(22)과 절연막(23)을 형성한다. 그다음, 제1실리사이드층(33) 및 제2실리사이드층(43)을 형성한다. 이때 제2실리콘층(43)이 접촉구(25)를 매몰시키지 않도록 한다. 그후 제3실리콘층(45)으로 접촉구를 매몰시키고, 상기 절연막(23)의 상부가 노출되도록 제3실리콘층(45)과 제2실리사이드층(43) 및 제1실리사이드층(33)을 제거한다. 그다음, 이온주입과 열처리 방법에 의해 제3실리사이드층(47)을 형성한다. 이때 접촉플러그(41)의 중앙에 실리사이드화 하지 않은 제3실리콘층(45)의 일부가 남게된다. 상기 미반응 실리콘층(45)은 금속실리사이드층(33), (43), (47)으로 둘러싸여 있으므로 접촉플러그(41)의 전기전도성에 영향을 미치지 않는다.3 is a cross-sectional view showing another embodiment of the method for manufacturing a contact plug according to the present invention. FIG. 3 shows that the contact plug is formed in the contact hole whose aspect ratio is larger than that in FIGS. Referring to FIG. 3, FIG. 3 is a view corresponding to FIG. 2e. The aspect ratio is relatively large, and when a contact hole 25 is buried in the second silicon layer, ion implanted with a high melting point metal into the second silicon layer. The portion of the silicon that does not suicide is also increased. In the same manner as in FIG. 2A, the diffusion region 22 and the insulating layer 23 are formed on the semiconductor substrate 21. Next, the first silicide layer 33 and the second silicide layer 43 are formed. At this time, the second silicon layer 43 does not bury the contact hole 25. Thereafter, the contact hole is buried in the third silicon layer 45, and the third silicon layer 45, the second silicide layer 43, and the first silicide layer 33 are removed to expose the upper portion of the insulating layer 23. do. Then, the third silicide layer 47 is formed by ion implantation and heat treatment. At this time, a part of the third silicon layer 45 not silicided is left in the center of the contact plug 41. Since the unreacted silicon layer 45 is surrounded by the metal silicide layers 33, 43, and 47, it does not affect the electrical conductivity of the contact plug 41.
제4a~b도는 이 발명에 따른 접촉플러그 제조방법의 또다른 실시예를 나타낸 공정도이다. 제4a도를 참조하면, 제4a도는 제2a도 상태로 확산영역(22) 및 접촉구(25)를 형성한후 확산영역(22)의 상부에 선택적 에피택셜성장(Selective Epitaxial Growth)법으로 제1에피층(51)을 형성한다. 그다음 Ti, Co, W 또는 Pt등 고융점 금속이온을 제1에피층(51)과 완전히 실리사이드화할 수 있는 량만큼 제1에피층(51)에 주입하여 제1금속이온층(52)을 형성한다. 그후 제1에피층의 상부에 선택적 에피택셜 성장법으로 제2에피층(53)을 형성하고, 제2에피층(53)에 금속이온을 주입하여 제2금속이온층(54)을 형성한다. 제4b도를 참조하면, 열처리 방법으로 상기 제1금속이온층(52) 및 제2금속이온층(54)의 금속이온들을 활성화시켜 상기 제1 및 제2에피층(51), (53)을 실리사이드화하여 접촉플러그(41)를 형성한다.4a to b is a process chart showing another embodiment of the method for manufacturing a contact plug according to the present invention. Referring to FIG. 4A, FIG. 4A illustrates the diffusion region 22 and the contact hole 25 in the state of FIG. 2A, and then, by using the selective epitaxial growth method on the diffusion region 22. One epitaxial layer 51 is formed. Then, high melting point metal ions such as Ti, Co, W, or Pt are injected into the first epitaxial layer 51 in an amount sufficient to completely silicide the first epitaxial layer 51 to form the first metal ion layer 52. Thereafter, a second epitaxial layer 53 is formed on the first epitaxial layer by selective epitaxial growth, and metal ions are injected into the second epitaxial layer 53 to form a second metal ion layer 54. Referring to FIG. 4B, the first and second epitaxial layers 51 and 53 are silicided by activating metal ions of the first metal ion layer 52 and the second metal ion layer 54 by a heat treatment method. To form the contact plug 41.
상술한 바와같이 애스팩트비가 큰 접촉구에 선택적 에피층, 다결정실리콘층 및 비정질실리콘층을 형성한후 고융점 금속을 이온주입하는 공정을 다수 반복하여 접촉플러그를 형성하는 방법으로 확산영역과 금속실리사이드층이 직접 접촉하므로 접촉면의 직렬기생저항을 줄이기 위한 불순물의 도핑을 할 필요가 없다. 따라서 이 발명은 별도의 불순물 도핑공정없이 확산영역과 접촉플러그 사이의 접촉면의 직렬기생저항을 감소시킬 수 있어 공정이 간단해지는 잇점이 있다.As described above, after forming the selective epi layer, the polysilicon layer, and the amorphous silicon layer in the contact hole having a large aspect ratio, the process of ion implanting a high melting point metal is repeated to form a contact plug by forming a diffusion region and a metal silicide. Since the layers are in direct contact, there is no need for doping of impurities to reduce the series parasitic resistance of the contact surface. Therefore, the present invention can reduce the series parasitic resistance of the contact surface between the diffusion region and the contact plug without an impurity doping process, thereby simplifying the process.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011259A KR930011113B1 (en) | 1991-07-03 | 1991-07-03 | Manufacturing method of contact plug for semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011259A KR930011113B1 (en) | 1991-07-03 | 1991-07-03 | Manufacturing method of contact plug for semiconductor device |
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| KR930003252A KR930003252A (en) | 1993-02-24 |
| KR930011113B1 true KR930011113B1 (en) | 1993-11-24 |
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