KR100558034B1 - Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process - Google Patents
Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process Download PDFInfo
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- KR100558034B1 KR100558034B1 KR1019990025924A KR19990025924A KR100558034B1 KR 100558034 B1 KR100558034 B1 KR 100558034B1 KR 1019990025924 A KR1019990025924 A KR 1019990025924A KR 19990025924 A KR19990025924 A KR 19990025924A KR 100558034 B1 KR100558034 B1 KR 100558034B1
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- bit line
- semiconductor device
- tungsten
- forming
- plug
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- 238000000034 method Methods 0.000 title claims abstract description 25
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 25
- 239000010937 tungsten Substances 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 title 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 2
- -1 Bitline Chemical compound 0.000 abstract 2
- 239000010408 film Substances 0.000 description 23
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Classifications
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
- F16B7/00—Connections of rods or tubes, e.g. of non-circular section, mutually, including resilient connections
- F16B7/04—Clamping or clipping connections
- F16B7/044—Clamping or clipping connections for rods or tubes being in angled relationship
- F16B7/048—Clamping or clipping connections for rods or tubes being in angled relationship for rods or for tubes without using the innerside thereof
- F16B7/0493—Clamping or clipping connections for rods or tubes being in angled relationship for rods or for tubes without using the innerside thereof forming a crossed-over connection
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
- F16B2/00—Friction-grip releasable fastenings
- F16B2/20—Clips, i.e. with gripping action effected solely by the inherent resistance to deformation of the material of the fastening
- F16B2/22—Clips, i.e. with gripping action effected solely by the inherent resistance to deformation of the material of the fastening of resilient material, e.g. rubbery material
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
- F16B2/00—Friction-grip releasable fastenings
- F16B2/20—Clips, i.e. with gripping action effected solely by the inherent resistance to deformation of the material of the fastening
- F16B2/22—Clips, i.e. with gripping action effected solely by the inherent resistance to deformation of the material of the fastening of resilient material, e.g. rubbery material
- F16B2/24—Clips, i.e. with gripping action effected solely by the inherent resistance to deformation of the material of the fastening of resilient material, e.g. rubbery material of metal
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
- F16B2200/00—Constructional details of connections not covered for in other groups of this subclass
- F16B2200/99—Fasteners with means for avoiding incorrect assembly or positioning
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 텅스텐 비트라인을 구비하는 반도체 소자 제조 방법에 있어서 비트라인 형성을 위한 식각 과정에서 비트라인과 그 하부 전도층을 연결하는 플러그가 손상되는 것을 방지할 수 있는, 텅스텐 비트라인 및 질화티타늄 플러그를 구비하는 반도체 소자 제조 방법에 관한 것으로, WF6 가스를 이용한 식각과정에서 식각되지 않는 TiN으로 하부 전도층과 비트라인을 연결하기 위한 플러그를 형성하고, 텅스텐으로 비트라인을 형성하는데 특징이 있다. The present invention provides a tungsten bit line and a titanium nitride plug which can prevent the plug connecting the bit line and the lower conductive layer from being damaged during the etching process for forming the bit line in the semiconductor device manufacturing method including the tungsten bit line. The present invention relates to a method of manufacturing a semiconductor device having a semiconductor device, the method comprising: forming a plug for connecting a lower conductive layer and a bit line with TiN that is not etched in an etching process using a WF 6 gas, and forming a bit line with tungsten.
텅스텐, 비트라인, TiN, 플러그, WF6, 식각Tungsten, Bitline, TiN, Plug, WF6, Etch
Description
도1 및 도2는 종래 기술에 따른 반도체 소자의 비트라인 형성 방법을 보이는 공정도,1 and 2 is a process chart showing a method for forming a bit line of a semiconductor device according to the prior art,
도3a 및 도3b는 본 발명의 일실시예에 따른 반도체 소자의 비트라인 형성 공정도.3A and 3B illustrate a process of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
30: 하부 전도층 31: 층간절연막30: lower conductive layer 31: interlayer insulating film
32: TiN 33: 텅스텐막32: TiN 33: tungsten film
C: 콘택홀C: contact hole
본 발명은 반도체 메모리 소자 제조 분야에 관한 것으로, 특히 반도체 소자의 비트라인 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method of forming a bit line of a semiconductor device.
초고집적 반도체 소자에서 비트라인을 형성하기 위하여 텅스텐 실리사이드를 증착한다. 텅스텐 실리사이드층은 박막의 비저항이 매우 높을 뿐만 아니라 고온에서 실리콘산화물층과의 열적 안정성도 매우 나쁘다. 따라서, 비트라인 형성을 위해 먼저 화학기상증착법(chemical vapor deposition)으로 폴리실리콘막을 증착한 후 폴리실리콘막 상에 텅스텐 실리사이드를 증착하여 사용하고 있다. Tungsten silicide is deposited to form bit lines in ultra-high density semiconductor devices. Tungsten silicide layer not only has a very high resistivity of the thin film but also has a very poor thermal stability with the silicon oxide layer at a high temperature. Therefore, in order to form a bit line, a polysilicon film is first deposited by chemical vapor deposition and then tungsten silicide is deposited on the polysilicon film.
그러나, 반도체 소자의 고집적화에 의해 비트라인의 선폭이 감소하고 이에 따라 선저항이 크게 증가하고 있어 소자의 신호처리 속도를 지연시키는 등 특성이 저하되고 있는 실정이다.However, due to the high integration of semiconductor devices, the line width of the bit line is reduced and the line resistance is greatly increased, thereby degrading the characteristics such as delaying the signal processing speed of the device.
이러한 문제를 개선하고자 텅스텐 실리사이드층 보다 금속저항이 1/10 정도는 금속 텅스텐막으로 비트라인을 형성하는 연구가 진행되고 있다. 이와 같이 텅스텐을 금속배선으로 사용하는 경우에 비트라인 콘택을 위한 플러그(plug)는 폴리실리콘 또는 텅스텐으로 형성한다.In order to improve this problem, studies have been conducted to form a bit line with a metal tungsten film having a metal resistance of about 1/10 of the tungsten silicide layer. As such, when tungsten is used as the metal wiring, the plug for the bit line contact is formed of polysilicon or tungsten.
첨부된 도면 도1의 (A) 및 (B)는 플러그(12)와 비트라인(13) 배선이 형성이 완료된 상태를 보이는 단면도 및 평면도로서, 미설명 도면부호 '10'은 하부 전도층, '11'은 층간절연막, 'C'는 콘택홀을 각각 나타낸다.1 (A) and (B) are cross-sectional views and a plan view showing a state in which the
도1에 도시한 바와 같이 비트라인(13) 배선 폭이 상대적으로 콘택홀에 비하여 넓은 경우에는, 비트라인(13)이 콘택홀을 충분하게 덮어 플러그(12)와 비트라인(13) 사이의 단선이 발생하지 않는다.As shown in FIG. 1, when the wiring width of the
그러나, 소자의 고집적화가 가속화됨에 따라서 비트라인 배선폭 및 콘택홀 크기는 감소하게 되고, 이에 따라 도2의 (A) 및 (B)에 도시한 바와 같이 콘택홀(C)과 비트라인(13) 사이의 오정렬(mis-align)이 발생할 수도 있다.However, as the high integration of the device is accelerated, the bit line wiring width and the contact hole size are reduced. As a result, the contact holes C and the
이와 같이 오정렬이 발생하면 콘택홀(C) 내부의 플러그(12)가 노출되고 비트라인(13) 형성을 위한 텅스텐막 식각 과정에서 식각제인 WF6에 의해 텅스텐 또는 폴리실리콘으로 이루어지는 플러그(12)가 식각되어 콘택홀 내에 공공(void, V)이 발생하는 문제점이 있다.When misalignment occurs as described above, the
다시 말하면, 비트라인 콘택홀(C) 내에 매립되어 있던 폴리실리콘 또는 텅스텐 플러그가 식각됨으로써 전기적 흐름의 단절을 초래하여 소자의 특성에 나쁜 영향을 미치게 된다.In other words, the polysilicon or tungsten plugs embedded in the bit line contact holes C are etched, which causes breakage of electrical flow and adversely affects device characteristics.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 텅스텐 비트라인을 구비하는 반도체 소자 제조 방법에 있어서 비트라인 형성을 위한 식각 과정에서 비트라인과 그 하부 전도층을 연결하는 플러그가 손상되는 것을 방지할 수 있는, 텅스텐 비트라인 및 질화티타늄 플러그를 구비하는 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the above problems in the semiconductor device manufacturing method having a tungsten bit line to prevent damage to the plug connecting the bit line and the lower conductive layer during the etching process for forming the bit line. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a tungsten bit line and a titanium nitride plug.
상기와 같은 목적을 달성하기 위한 본 발명은 반도체 소자 제조 방법에 있어서, 전도층 상에 형성된 층간절연막을 선택적으로 식각하여 상기 전도층을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀 내부에 TiN 플러그를 형성하는 단계; 상기 TiN 플러그가 형성된 전체 구조 상에 텅스텐막을 증착하는 단계; 및 WF6 가스를 이용한 식각으로 상기 텅스텐막을 선택적으로 식각하여 텅스텐비트라인을 형성하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a contact hole exposing the conductive layer by selectively etching an interlayer insulating layer formed on the conductive layer; Forming a TiN plug in the contact hole; Depositing a tungsten film on the entire structure in which the TiN plug is formed; And selectively etching the tungsten film by etching using WF 6 gas to form a tungsten bit line.
본 발명은 WF6 가스를 이용한 식각과정에서 식각되지 않는 TiN으로 하부 전도층과 비트라인을 연결하기 위한 플러그를 형성하고, 텅스텐으로 비트라인을 형성하는데 특징이 있다.The present invention is characterized by forming a plug for connecting the lower conductive layer and the bit line with TiN that is not etched in the etching process using WF 6 gas, and forming the bit line with tungsten.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
먼저, 도3a에 도시한 바와 같이 하부전도층(30) 상에 형성된 층간절연막(31)을 선택적으로 식각하여 하부전도층(30)을 노출시키는 콘택홀(C)을 형성하고, 전체 구조 상에 금속 TiN막(32)을 증착한다.First, as shown in FIG. 3A, the
콘택홀의 지름은 0.2 ㎛ 이하로 매우 작기 때문에 종래의 물리기상증착법(physical vapor deposition) 방법으로는 매립 특성이 양호한 TiN막을 형성할 수 없으므로 다음과 같은 조건의 화학기상증착법으로 TiN막(32)을 형성한다. 즉, 증착용 소스로는 유기 소스(organic source)인 TiCl4를 5 sccm 내지 20 sccm 주입하고, 300 ℃ 내지 800 ℃ 온도, 0.5 torr 내지 100 torr 압력에서 100 W 내지 1 ㎾의 RF 전력을 인가한다. 이때, 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition) 방법을 이용할 수도 있다.Since the contact hole has a diameter of 0.2 μm or less, a TiN film having good buried characteristics cannot be formed by a conventional physical vapor deposition method. Thus, the TiN
이와 같이 형성된 TiN막(32)을 화학기계적 연마(chemical mechanical polishing) 또는 에치백(etch back) 방법으로 평탄화시켜 콘택홀(C) 내부에 TiN막(32) 플러그를 형성한다.The TiN
다음으로, 층간절연막(31) 및 TiN막(32) 플러그 상에 금속 텅스텐막(33)을 증착한다.Next, a
이어서, 텅스텐막(33)을 패터닝하기 위한 마스크 공정 및 WF6를 이용한 식각 공정을 실시하여 도3b의 (A) 및 (B)에 도시한 바와 같이 텅스텐막(33) 비트라인을 형성한다. 마스크 공정시 발생하는 오정렬에 따라 콘택홀 내부의 TiN막(32)이 노출되더라도 TiN막(32)은 WF6에 의해 식각되지 않기 때문에 플러그의 손상은 발생하지 않는다.Subsequently, a mask process for patterning the
전술한 바와 같이 이루어지는 본 발명은 비트라인 배선 형성 과정 뿐만 아니라 금속 배선 형성 공정에도 이용될 수 있다.The present invention made as described above can be used not only for the bit line wiring forming process but also for the metal wiring forming process.
한편, 상기 본 발명의 실시예에서는 TiN막(32)을 콘택홀 전체에 매립하는 경우를 설명하였지만, 텅스텐 또는 폴리실리콘 등으로 플러그의 일부를 형성하고 플러그 상부에 TiN막을 형성할 수도 있다.Meanwhile, in the embodiment of the present invention, the case in which the TiN
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 비트라인 형성을 위한 식각 과정에서 플러그가 손상되는 것을 효과적으로 방지하여 공정 여유도를 증가시킬 수 있으며 소자의 특성 저하를 방지할 수 있다.The present invention made as described above can effectively prevent damage to the plug in the etching process for forming the bit line can increase the process margin and can prevent the deterioration of the characteristics of the device.
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KR1019990025924A KR100558034B1 (en) | 1999-06-30 | 1999-06-30 | Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process |
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KR1019990025924A KR100558034B1 (en) | 1999-06-30 | 1999-06-30 | Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process |
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KR20010005126A KR20010005126A (en) | 2001-01-15 |
KR100558034B1 true KR100558034B1 (en) | 2006-03-07 |
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KR1019990025924A KR100558034B1 (en) | 1999-06-30 | 1999-06-30 | Method for forming semiconductor device capable of preventing plug loss during tungsten bit line formation process |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06349774A (en) * | 1993-06-08 | 1994-12-22 | Sony Corp | Method of forming buried plug |
KR19980070982A (en) * | 1997-01-31 | 1998-10-26 | 가네꼬히사시 | Semiconductor device and manufacturing method |
KR100218728B1 (en) * | 1995-11-01 | 1999-09-01 | 김영환 | Manufacturing method of metal interconnection of semiconductor device |
KR100221760B1 (en) * | 1995-07-31 | 1999-09-15 | 가네꼬 히사시 | Semiconductor device including protective layer for protecting via hole from etching |
-
1999
- 1999-06-30 KR KR1019990025924A patent/KR100558034B1/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06349774A (en) * | 1993-06-08 | 1994-12-22 | Sony Corp | Method of forming buried plug |
KR100221760B1 (en) * | 1995-07-31 | 1999-09-15 | 가네꼬 히사시 | Semiconductor device including protective layer for protecting via hole from etching |
KR100218728B1 (en) * | 1995-11-01 | 1999-09-01 | 김영환 | Manufacturing method of metal interconnection of semiconductor device |
KR19980070982A (en) * | 1997-01-31 | 1998-10-26 | 가네꼬히사시 | Semiconductor device and manufacturing method |
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KR20010005126A (en) | 2001-01-15 |
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