KR20060008431A - Method for forming metal interconnection line of semiconductor device - Google Patents

Method for forming metal interconnection line of semiconductor device Download PDF

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KR20060008431A
KR20060008431A KR1020040057299A KR20040057299A KR20060008431A KR 20060008431 A KR20060008431 A KR 20060008431A KR 1020040057299 A KR1020040057299 A KR 1020040057299A KR 20040057299 A KR20040057299 A KR 20040057299A KR 20060008431 A KR20060008431 A KR 20060008431A
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South Korea
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contact hole
forming
layer
etch stop
metal film
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KR1020040057299A
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Korean (ko)
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임병혁
최동구
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주식회사 하이닉스반도체
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Priority to KR1020040057299A priority Critical patent/KR20060008431A/en
Publication of KR20060008431A publication Critical patent/KR20060008431A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 금속배선 형성시 갭필(Gap-Fill) 마진을 확보하여 매립불량으로 인한 보이드(Void) 형성을 방지할 수 있는 반도체 소자의 금속배선 형성방법을 개시한다. 개시된 본 발명은 비트라인이 형성된 반도체 기판을 제공하는 단계; 상기 비트라인을 포함한 기판 결과물 상에 하드마스크막과 층간절연막 및 식각정지용 질화막을 차례로 형성하는 단계; 상기 식각정지용 질화막 상에 스토리지 노드용 산화막을 형성하는 단계; 상기 스토리지 노드용 산화막, 식각정지용 질화막, 층간절연막 및 하드마스크막을 건식 식각하여 비트라인 부분을 노출시키는 콘택홀을 형성하는 단계; 상기 식각정지용 질화막의 높은 식각선택비를 이용하여 콘택홀 하부의 면적을 증가시켜 후속의 금속배선 공정에서 갭필 마진을 확보하기 위해 콘택홀 표면에 플라즈마 처리를 실시하는 단계; 상기 콘택홀 표면에 베리어 금속막을 증착하는 단계; 및 상기 베리어 금속막 상에 배선용 금속막을 증착하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for forming metal wiring of a semiconductor device that can prevent void formation due to a poor filling by securing a gap-fill margin when forming metal wiring. The disclosed invention provides a method of forming a semiconductor substrate including: Sequentially forming a hard mask layer, an interlayer dielectric layer, and an etch stop nitride layer on the substrate product including the bit line; Forming an oxide layer for a storage node on the etch stop nitride layer; Forming a contact hole exposing the bit line by dry etching the storage node oxide layer, the etch stop nitride layer, the interlayer insulating layer, and the hard mask layer; Performing a plasma treatment on the surface of the contact hole to increase the area under the contact hole by using a high etching selectivity of the etch stop nitride film to secure a gap fill margin in a subsequent metallization process; Depositing a barrier metal film on a surface of the contact hole; And depositing a wiring metal film on the barrier metal film.

Description

반도체 소자의 금속배선 형성방법{METHOD FOR FORMING METAL INTERCONNECTION LINE OF SEMICONDUCTOR DEVICE}METHOD FOR FORMING METAL INTERCONNECTION LINE OF SEMICONDUCTOR DEVICE}

도 1a 내지 1d 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11 : 반도체 기판 12 : 비트라인11 semiconductor substrate 12 bit line

13 : 하드마스크막 14 : 층간절연막13 hard mask film 14 interlayer insulating film

15 : 식각정지용 질화막 16 : 스토리지 노드용 산화막15 nitride film for etch stop 16: oxide film for storage node

17 : 감광막 패턴 18 : 콘택홀17 photosensitive film pattern 18: contact hole

19 : 베리어 금속막 20 : 배선용 금속막19: barrier metal film 20: wiring metal film

21 : 금속배선21: metal wiring

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 금속배선 형성시 갭필(Gap-Fill) 마진을 확보하여 매립불량으로 인한 보이드(Void) 형성을 방지할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to secure a gap-fill margin when forming a metal wiring, thereby preventing the formation of voids due to buried defects. It relates to a formation method.                         

반도체 소자의 고집적화에 따라 디자인 룰(design rule)이 작아지면서 배선 공정, 예컨데, 비트라인에 사용되는 물질로서 금속을 사용하게 되었다. 여기서, 실리콘 기판을 사용하는 반도체 소자는 금속배선 형성시 배선용 금속막으로부터의 전자 이동 및 확산에 의한 전기적 특성 저하를 방지하기 위해 배선용 금속막 아래에 베리어 금속막을 배치시키고 있다. 이러한 베리어 금속막으로서는 Ti막을 가장 많이 사용하고 있으며, 대부분의 반도체 제조사들이 Ti막을 베리어 금속막으로 채용하여 금속배선, 예컨데, 텅스텐 배선을 형성하고 있다.As the integration of semiconductor devices increases, design rules become smaller, and metals are used as materials used in wiring processes, for example, bit lines. Here, in the semiconductor device using the silicon substrate, the barrier metal film is disposed under the metal film for wiring in order to prevent the electrical property deterioration due to electron movement and diffusion from the metal film for wiring during formation of the metal wiring. As the barrier metal film, the Ti film is most frequently used, and most semiconductor manufacturers adopt the Ti film as the barrier metal film to form metal wiring, for example, tungsten wiring.

최근, 반도체 소자의 집적도와 함께 스토리지 노드(Storage Node)의 정전용량을 확보하기 위해 산화막의 높이가 증가하고 있는 추세이다. 현재 금속배선의 하부층은 산화막과 질화막을 구성되어 있으며 산화막의 높이의 증가와 함께 산화막과 질화막을 건식 식각하여 금속배선을 형성하기 위한 콘택홀을 형성하는데에 그 한계가 있다. Recently, the height of the oxide layer is increasing to secure the capacitance of the storage node along with the degree of integration of semiconductor devices. Currently, the lower layer of the metal wiring includes an oxide film and a nitride film, and there is a limit in forming a contact hole for forming metal wiring by dry etching the oxide film and the nitride film with an increase in the height of the oxide film.

이러한 문제점으로 인해 베리어 금속막과 배선용 금속막을 증착하여 금속배선을 형성하는 후속의 공정에서 콘택홀 하부의 면적 확보의 한계와 함께 금속배선 증착 기술의 한계성으로 인해 콘택홀 하부에서 매립불량으로 인한 보이드가 발생하게 된다. 결국, 보이드 형성으로 인해 콘택홀의 저항 값을 증가시키고, 소자 동작에 필요한 전원을 원할하게 공급하지 못하게 되어 소자의 성능이 저하되는 문제점이 있다. Due to this problem, in the subsequent process of depositing the barrier metal film and the wiring metal film to form the metal wiring, there is a limit of securing the area under the contact hole and the voids due to the poor filling in the contact hole under the metal wiring deposition technology. Will occur. As a result, due to the void formation, the resistance value of the contact hole is increased, and power supply required for device operation cannot be supplied smoothly, thereby degrading device performance.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 금속배선 형성시 갭필 마진을 확보하여 매립불량으로 인한 보이드 형성을 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which is designed to solve the above problems, and to prevent void formation due to a poor filling by securing a gap fill margin when forming a metal wiring. have.

상기 목적을 달성하기 위한 본 발명은, 비트라인이 형성된 반도체 기판을 제공하는 단계; 상기 비트라인을 포함한 기판 결과물 상에 하드마스크막과 층간절연막 및 식각정지용 질화막을 차례로 형성하는 단계; 상기 식각정지용 질화막 상에 스토리지 노드용 산화막을 형성하는 단계; 상기 스토리지 노드용 산화막, 식각정지용 질화막, 층간절연막 및 하드마스크막을 건식 식각하여 비트라인 부분을 노출시키는 콘택홀을 형성하는 단계; 상기 식각정지용 질화막의 높은 식각선택비를 이용하여 콘택홀 하부의 면적을 증가시켜 후속의 금속배선 공정에서 갭필 마진을 확보하기 위해 콘택홀 표면에 플라즈마 처리를 실시하는 단계; 상기 콘택홀 표면에 베리어 금속막을 증착하는 단계; 및 상기 베리어 금속막 상에 배선용 금속막을 증착하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, providing a semiconductor substrate with a bit line formed; Sequentially forming a hard mask layer, an interlayer dielectric layer, and an etch stop nitride layer on the substrate product including the bit line; Forming an oxide layer for a storage node on the etch stop nitride layer; Forming a contact hole exposing the bit line by dry etching the storage node oxide layer, the etch stop nitride layer, the interlayer insulating layer, and the hard mask layer; Performing a plasma treatment on the surface of the contact hole to increase the area under the contact hole by using a high etching selectivity of the etch stop nitride film to secure a gap fill margin in a subsequent metallization process; Depositing a barrier metal film on a surface of the contact hole; And depositing a wiring metal film on the barrier metal film.

여기에서, 상기 플라즈마 처리를 실시하는 단계는 500∼1000W의 파워를 사용하여 20∼100mTorr의 압력 및 0∼100℃의 온도에서 수행하는 것을 특징으로 한다.The plasma treatment may be performed at a pressure of 20 to 100 mTorr and a temperature of 0 to 100 ° C. using a power of 500 to 1000 W.

상기 플라즈마 처리를 실시하는 단계는 NF3 가스를 10∼14sccm, He 가스를 98∼102sccm 및 O2 가스를 28∼32sccm으로 주입하여 수행하는 것을 특징으로 한다.The plasma treatment may be performed by injecting 10-14 sccm of NF3 gas, 98-102 sccm of He gas, and 28-32 sccm of O2 gas.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.                     

먼저, 본 발명의 기술적 원리를 살펴보면, 본 발명은 비트라인이 형성된 반도체 기판 상에 금속배선 형성시 매립불량으로 인해 보이드가 형성되는 종래 공정과 달리, 금속배선을 형성하기 위한 콘택홀 형성 후, 콘택홀 표면에 플라즈마 처리를 실시하여 콘택홀 하부의 면적을 증가시킴으로써 금속배선 공정에서 갭필 마진을 확보하여 매립 불량으로 인한 보이드 형성을 방지할 수 있다.First, referring to the technical principle of the present invention, unlike the conventional process in which voids are formed due to a poor filling when forming metal wires on a semiconductor substrate on which a bit line is formed, a contact hole is formed after forming a contact hole for forming metal wires. Plasma treatment is performed on the hole surface to increase the area under the contact hole, thereby securing a gap fill margin in the metallization process, thereby preventing void formation due to buried defects.

도 1a 내지 1d 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도이다.1A to 1D are cross-sectional views illustrating processes of forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

도 1a에 도시된 바와 같이, 비트라인(12)이 형성된 반도체 기판(11)을 제공한다. 그 다음, 상기 비트라인(12)을 포함한 기판 결과물 상에 하드마스크막(13)과 층간절연막(14)을 형성한다. 이어서, 상기 층간절연막(14) 상에 식각정지용 질화막(15) 및 스토리지 노드용 산화막(16)을 차례로 형성한다. 그 다음, 상기 스토리지 노드용 산화막(16) 상에 콘택홀 형성 영역을 한정하는 감광막 패턴(17)을 형성한다.As shown in FIG. 1A, a semiconductor substrate 11 having a bit line 12 is provided. Next, the hard mask film 13 and the interlayer insulating film 14 are formed on the substrate product including the bit line 12. Subsequently, an etch stop nitride film 15 and a storage node oxide film 16 are sequentially formed on the interlayer insulating film 14. Next, a photoresist pattern 17 defining a contact hole forming region is formed on the storage node oxide layer 16.

도 1b에 도시된 바와 같이, 상기 감광막 패턴(17)을 이용해서 상기 비트라인(12)이 노출되도록 스토리지 노드용 산화막(16), 식각정지용 질화막(15), 층간절연막(14) 및 하드마스크막(13)을 건식 식각하여 콘택홀(18)을 형성한다.As shown in FIG. 1B, an oxide film 16 for a storage node, an nitride film 15 for etching stop, an interlayer insulating film 14, and a hard mask film are exposed so that the bit line 12 is exposed using the photoresist pattern 17. Dry etching is performed to form the contact hole 18.

도 1c에 도시된 바와 같이, 상기 식각정지용 질화막(15)의 높은 식각선택비를 이용하여 콘택홀(18) 표면에 플라즈마 처리를 실시한다. 이때, 상기 플라즈마 처리는 500∼1000W의 파워를 사용하여 20∼100mTorr의 압력 및 0∼100℃의 온도에서 NF3 가스를 10∼14sccm, He 가스를 98∼102sccm 및 O2 가스를 28∼32sccm으로 주입하여 수행한다. 여기에서, 상기 콘택홀(18) 표면에 플라즈마 처리를 실시함으로써 10nm 이상의 콘택홀(18) 하부의 면적(A)을 증가시킴으로 인해 후속의 금속배선 공정에서 갭필 마진을 확보할 수 있다. 이로 인해 금속배선 공정에서 매립 불량으로 인한 보이드 형성을 방지할 수 있다.As shown in FIG. 1C, a plasma treatment is performed on the surface of the contact hole 18 using a high etching selectivity of the etch stop nitride film 15. At this time, the plasma treatment is performed by injecting 10-14 sccm of NF3 gas, 98-102 sccm of He gas and 28-32 sccm of O2 gas at a pressure of 20-100 mTorr and a temperature of 0-100 ° C. using a power of 500-1000 W. Perform. In this case, by performing a plasma treatment on the surface of the contact hole 18 to increase the area A of the lower portion of the contact hole 18 of 10 nm or more, it is possible to secure a gap fill margin in a subsequent metallization process. As a result, it is possible to prevent the formation of voids due to poor filling in the metallization process.

도 1d에 도시된 바와 같이, 상기 콘택홀(18) 표면에 베리어 금속막(19)을 증착한 후에 상기 베리어 금속막(19) 상에 배선용 금속막(20)을 증착하여 본 발명에 따른 금속배선(21)을 증착한다. 이때, 상기 베리어 금속막(19)은 티타늄/티타늄질화막(Ti/TiN)으로 형성하며, 상기 배선용 금속막(20)은 텅스텐으로 형성한다.As shown in FIG. 1D, the barrier metal film 19 is deposited on the contact hole 18, and then the wiring metal film 20 is deposited on the barrier metal film 19. (21) is deposited. In this case, the barrier metal film 19 is formed of titanium / titanium nitride film (Ti / TiN), and the wiring metal film 20 is formed of tungsten.

이상, 본 발명은 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 수 있을 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and those skilled in the art may make many modifications and variations without departing from the spirit of the present invention. It will be appreciated.

이상에서와 같이, 본 발명은 금속배선을 형성하기 위한 콘택홀 형성 후, 콘택홀 표면에 플라즈마 처리를 실시하여 콘택홀 하부의 면적을 증가시킴으로써 금속배선 공정에서 갭필 마진을 확보하여 매립 불량으로 인한 보이드 형성을 방지할 수 있다.As described above, in the present invention, after forming the contact hole for forming the metal wiring, the surface of the contact hole is increased by performing plasma treatment on the contact hole surface, thereby securing a gap fill margin in the metal wiring process, thereby causing voids due to poor filling. Formation can be prevented.

Claims (3)

비트라인이 형성된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having bit lines formed thereon; 상기 비트라인을 포함한 기판 결과물 상에 하드마스크막과 층간절연막 및 식각정지용 질화막을 차례로 형성하는 단계;Sequentially forming a hard mask layer, an interlayer dielectric layer, and an etch stop nitride layer on the substrate product including the bit line; 상기 식각정지용 질화막 상에 스토리지 노드용 산화막을 형성하는 단계;Forming an oxide layer for a storage node on the etch stop nitride layer; 상기 스토리지 노드용 산화막, 식각정지용 질화막, 층간절연막 및 하드마스크막을 건식 식각하여 비트라인 부분을 노출시키는 콘택홀을 형성하는 단계;Forming a contact hole exposing the bit line by dry etching the storage node oxide layer, the etch stop nitride layer, the interlayer insulating layer, and the hard mask layer; 상기 식각정지용 질화막의 높은 식각선택비를 이용하여 콘택홀 하부의 면적을 증가시켜 후속의 금속배선 공정에서 갭필 마진을 확보하기 위해 콘택홀 표면에 플라즈마 처리를 실시하는 단계; Performing a plasma treatment on the surface of the contact hole to increase the area under the contact hole by using a high etching selectivity of the etch stop nitride film to secure a gap fill margin in a subsequent metallization process; 상기 콘택홀 표면에 베리어 금속막을 증착하는 단계; 및Depositing a barrier metal film on a surface of the contact hole; And 상기 베리어 금속막 상에 배선용 금속막을 증착하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And depositing a wiring metal film on the barrier metal film. 제 1 항에 있어서, 상기 플라즈마 처리를 실시하는 단계는 500∼1000W의 파워를 사용하여 20∼100mTorr의 압력 및 0∼100℃의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the performing of the plasma treatment is performed at a pressure of 20-100 mTorr and a temperature of 0-100 ° C. using a power of 500-1000 W. 3. 제 1 항에 있어서, 상기 플라즈마 처리를 실시하는 단계는 NF3 가스를 10∼ 14sccm, He 가스를 98∼102sccm 및 O2 가스를 28∼32sccm으로 주입하여 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the plasma treatment is performed by injecting 10 to 14 sccm of NF 3 gas, 98 to 102 sccm of He gas, and 28 to 32 sccm of O 2 gas. .
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8211793B2 (en) 2006-08-18 2012-07-03 Samsung Electronics Co., Ltd. Structures electrically connecting aluminum and copper interconnections and methods of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8211793B2 (en) 2006-08-18 2012-07-03 Samsung Electronics Co., Ltd. Structures electrically connecting aluminum and copper interconnections and methods of forming the same

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