KR20050007641A - Method for forming a copper metal line in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a copper metal interconnection of a semiconductor device is provided to improve connection reliability between upper and lower copper metal interconnections by eliminating a copper layer re-deposited on the inner sidewall of a via hole formed by an RF(radio frequency) sputter cleaning process by a cleaning process using a fluorine-based solution. CONSTITUTION: A diffusion barrier layer(18) and an interlayer dielectric are formed on a semiconductor substrate(10) having a lower copper metal interconnection. The interlayer dielectric is patterned to form a via hole by an etch process using a via hole etch mask. The via hole etch mask is removed by a strip process using oxygen gas. An ARC(anti-reflective coating) is deposited to fill the via hole. A trench(32) is formed by an etch process using a trench etch mask. The trench etch mask and the ARC are removed to expose a part of the diffusion barrier layer by a strip process using the oxygen gas. The exposed diffusion barrier layer is removed to expose the lower copper metal interconnection by an etch process. The byproduct remaining the upper surface of the exposed lower copper metal interconnection is eliminated by an RF sputter cleaning process. The copper layer formed on the inner sidewall of the via hole by the RF sputter cleaning process is eliminated by a cleaning process using a fluorine-based solution. An upper copper metal interconnection is formed to fill the via hole and the trench.

Description

Method for forming a copper metal line in semiconductor device

The present invention relates to a method of forming a copper metal wiring of a semiconductor device, and more particularly, to a method of forming a copper metal wiring of a semiconductor device capable of improving connection reliability of upper and lower copper metal wiring.

In a semiconductor device or an electronic device, a conductor film such as aluminum (Al) or tungsten (W) is deposited on an insulating film as a metal wiring forming technique, and then the conductor film is subjected to a conventional photolithography process and dry etching ( The technique of forming metal wiring by patterning through dry etching process has been established and widely used in this field.

Recently, as a way to reduce the RC delay centering on logic devices that require high integration and high performance among semiconductor devices, a method of using a low-resistance metal such as copper (Cu) as a wiring instead of aluminum or tungsten has been studied. have. In RC, 'R' represents wiring resistance, and 'C' represents dielectric constant of the insulating film.

In the metallization process using copper, the patterning process is more difficult than aluminum or tungsten. Accordingly, a so-called 'damascene' process is used in which a trench is first formed and a metal wiring is formed to fill the trench. A single damascene process is currently used. ) And dual damascene process. The single damascene process is a method of forming a via hole and then filling the via hole with a conductive material, forming a wiring trench on the upper portion thereof, and then filling the trench with a wiring material to form a metal wiring. The dual damascene process is a method for forming metal vias by forming via holes and wiring trenches and then filling the wiring material with via holes and wiring trenches at the same time. In addition, various methods are suggested.

However, copper is difficult to produce as volatile by-products due to reaction with radicals and the like, and thus, the dry etching process itself is difficult. In addition, even when the RF sputter cleaning process is performed at a high temperature, as shown in FIG. 1, the lower copper metal wiring A is redeposited and aggregated around the via hole B. agglomeration) occurs, thereby increasing the resistance of the via hole. Further, a problem arises in that the reliability of the copper metal wiring is lowered, such as voids being formed in the copper metal wiring by a subsequent heat treatment process (for example, at a temperature of about 300 ° C to 400 ° C).

Therefore, a preferred embodiment of the present invention is to improve the connection reliability of the upper and lower copper metal wiring.

1 to 6 are cross-sectional views illustrating a method of forming a copper metal wiring of a semiconductor device according to a preferred embodiment of the present invention.

FIG. 7 is a SEM (Scanning Electron Microscope) and TEM (Transmission) for showing the cohesion after the copper layer and the subsequent process of redepositing the inner wall of the via hole during the RF sputter cleaning process in the prior art; Electron Microscope).

<Explanation of symbols for main parts of drawing>

10 semiconductor substrate 12 semiconductor structure layer

14: first interlayer insulating film 16: lower copper metal wiring

18 diffusion barrier film 20 second interlayer insulating film

22: capping layer 24: via hole

26 sidewall oxide film 28 antireflection film

30: trench etching mask 32: trench

According to an aspect of the present invention, a step of forming a diffusion barrier and an interlayer insulating film on the semiconductor substrate on which the lower copper metal wiring is formed, and forming a via hole by patterning the interlayer insulating film through an etching process using a via hole etching mask; Removing the via hole etching mask through a strip process using oxygen gas, depositing an antireflection film to fill the via hole, and forming the trench through an etching process using a trench etching mask; The trench etching mask and the anti-reflection film are removed by using a strip process using oxygen gas to expose a portion of the diffusion barrier, and the diffusion barrier exposed in the step is removed through an etching process to remove the lower copper metallization. This exposed step and the high frequency sputter cleaning process Removing by-products remaining on the upper surface of the lower copper metal wires exposed through the copper, and removing the copper layer formed on the inner wall of the via hole by the high frequency sputter cleaning process through a cleaning process using a fluorine-based solution. And forming an upper copper metal wiring such that the via hole and the trench are filled with the copper metal wiring of the semiconductor device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 to 6 are cross-sectional views illustrating a method of forming a copper metal wiring of a semiconductor device according to a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 6 are the same components having the same function.

Referring to FIG. 1, a semiconductor substrate 10 having a predetermined semiconductor structure layer 12 formed thereon is provided. The semiconductor structure layer 12 may include a transistor, a memory cell, a capacitor, a junction layer, a conductive layer, and the like. Subsequently, on the semiconductor structure layer 12, as a low dielectric material, for example, PLAEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), FSG (Fluorinated Silicate Glass), silicon oxide, fluorine-containing silicon oxide Alternatively, an insulating film (hereinafter referred to as 'first interlayer insulating film') 14 is deposited using fluorine-containing oxide or the like. In general, fluorine-containing silicon oxide has a lower dielectric constant than silicon oxide, and the dielectric constant can be controlled by adjusting the fluorine content. After the first interlayer insulating layer 14 is formed, a lithography process is performed to form contact holes (not shown) in the first interlayer insulating layer 14, and the lower copper metal wiring 16 is embedded to fill the contact holes. Are formed sequentially. Meanwhile, a barrier film may be formed on an inner surface of the contact hole before the lower metal wiring 16 is deposited. In this case, the barrier film may include Ta, TaN, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, Co. And CoSi ₂ .

After the lower copper metallization 16 is formed, a diffusion barrier 18, a second interlayer insulating film 20, and a capping layer 22 are sequentially formed on the entire structure. The diffusion barrier 18 is formed of any one of a nitride film (eg, SiN), a nitride oxide film (eg, SiON), a carbide film (eg, SiC), and an oxide film (eg, SiO ₂ ), or the films are at least doubled. It may be formed of a laminated structure, the structure is formed to a thickness of 200 ~ 1500Å. The second interlayer insulating film 20 is preferably formed of a film having a dielectric constant of 2.5 to 4.3 band. For example, it is formed of an OSG (Organo Silicate Glass) film and is formed to a thickness of 5000 kPa to 20000 kPa. The capping layer 22 is formed of one of a nitride film (eg, SiN), a nitride oxide film (eg, SiON), a carbide film (eg, SiC), and an oxide film (eg, SiO ₂ ), or the films are at least doubled. It may be formed of a laminated structure, the structure is formed to a thickness of 500Å to 3000Å. Meanwhile, an etch stop layer (not shown) may be formed in the middle of the second interlayer insulating layer 20 regardless of the type and thickness of the material.

Referring to FIG. 2, after the capping layer 22 is formed in FIG. 1, a dual damascene process is performed. Here, the process proceeds in a pre-via manner. After the photoresist (not shown) is applied on the entire structure, a photoresist pattern (hereinafter referred to as a "via hole etching mask") is sequentially performed by sequentially performing an exposure process and a developing process using a photomask. ) Is formed. Next, a via hole 24 is formed by performing an etching process using the via hole etching mask. In this case, the etching process is carried out by a dry etching method, using C _x F _y H _z (x, y, z is 0 or natural water) gas as the main etching gas, O ₂ , N ₂ , SF ₆ It is carried out using additive gases such as, Ar, He and the like. As a result, a portion of the diffusion barrier 18 is exposed through the via hole 24. Subsequently, the via hole etching mask is removed through a strip using oxygen (O ₂ ) gas. At this time, the sidewall oxide layer 26 is formed to be relatively thick (for example, 5 kPa to 100 kPa) as a by-product on the sidewall of the second interlayer insulating film 20 exposed through the via hole 24 by the oxygen gas used in the strip process. The strip process is preferably carried out at a temperature of 40 ℃ to 300 ℃.

Referring to FIG. 3, an anti-reflection film 28 is formed to fill the via hole 24. In this case, the anti-reflection film 28 may be formed of an organic material with a thickness of 300 kPa to 1600 kPa, or may be formed of a SiN, SiC, or SiON film with a thickness of 300 kPa to 1500 kPa. Alternatively, the organic material may be formed in a stacked structure of an SiN, SiC, or SiON film. The anti-reflection film 28 may also function to prevent the lower copper metal wiring 16 from being damaged during the subsequent trench formation process. Subsequently, after the photoresist (not shown) is coated on the entire structure, a photoresist pattern (hereinafter referred to as a trench etch mask) 30 is sequentially formed by sequentially performing an exposure process and a development process using a photomask. . Next, a trench 32 is formed by performing an etching process using the trench etching mask 30. In this case, the etching process may be performed in the same manner as the etching process of the via hole 24 described in FIG. 2, or by adjusting the ratio of x, y, z to C _x F _y H _z gas differently. It can also be adjusted to increase or decrease the etch selectivity for.

Referring to FIG. 4, after the trench 30 is formed in FIG. 3, the trench etch mask 28 is removed through a strip process using oxygen gas. In this case, the strip process is preferably carried out at a temperature of 150 ℃ or less in order not to increase the dielectric constant between the copper metal wiring. For example, it is carried out at a temperature of 50 ° C to 150 ° C. Through this stripping process, the antireflective film 28 remaining in FIG. Subsequently, the diffusion barrier 18 exposed through the via hole 24 is removed through an etching process. In this case, the etching process is performed using C _x F _y H _z gas as the main etching gas, and using additive gases such as O ₂ , N ₂ , SF ₆ , Ar, He, and the like. In this case, it is preferable that the C / F ratio is reduced by increasing the ratio of y or z, or by increasing the addition amount of O ₂ , N ₂ gas or the like. As a result, a part of the lower copper metal wiring 16 is exposed through the via hole 24.

Referring to FIG. 5, an etching residue, a by-product, or a copper oxide layer formed by oxidizing an upper surface of the lower copper metal interconnection 16 remaining on the upper surface of the lower copper metal interconnection 16 exposed in FIG. 4 is removed. In order to achieve this, a high frequency sputter cleaning process is performed. In this case, the high frequency sputter cleaning process is not limited to the source gas, but is carried out in a dry manner using plasma. By the high frequency sputter cleaning process, copper atoms of the lower copper metal wire 16 may be redeposited on the inner wall of the via hole 24 as shown in FIG. 5.

Referring to FIG. 6, a cleaning process is performed to lift-off copper atoms redeposited on the inner wall of the via hole 24 by a high frequency sputter cleaning process in FIG. 5. At this time, the cleaning process is a fluorine-based solution such as HF or BOE (Buffered Oxide Etchant). Through this cleaning process, the sidewall oxide film 26 formed on the inner wall of the second interlayer insulating film 20 is also removed. Thereafter, an upper copper metal wiring (not shown) is formed in the via hole 24 and the trench 32 through a general process.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In particular, in the preferred embodiment of the present invention, the dual damascene pattern forming process is performed in a pre-via method, which is an example of a post-via method, a self aligned method, or a hard mask. It is also applicable to the etching method using). In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after the trench is formed, via holes are formed by RF sputter cleaning performed to remove by-products remaining on the upper surface of the lower copper metallization. By removing the copper layer redeposited on the inner wall of the through a cleaning process using a fluorine-based solution, it is possible to facilitate the connection between the upper copper metal wiring and the lower copper metal wiring formed through the subsequent process. Thereby, it is possible to improve the connection reliability between upper and lower copper metal wiring.

Claims (6)

(a) forming a diffusion barrier layer and an interlayer dielectric layer on the semiconductor substrate on which the lower copper metallization is formed; (b) forming a via hole by patterning the interlayer insulating layer through an etching process using a via hole etching mask; (c) removing the via hole etching mask through a strip process using oxygen gas; (d) depositing an anti-reflection film to fill the via holes; (e) forming the trench through an etching process using a trench etching mask; (f) removing the trench etching mask and the anti-reflection film through a strip process using the oxygen gas to expose a portion of the diffusion barrier; (g) exposing the lower copper metal wiring by removing the diffusion barrier film exposed in the step (f) through an etching process; (h) removing by-products remaining on the upper surface of the lower copper metal wire exposed through the high frequency sputter cleaning process; (i) removing the copper layer formed on the inner wall of the via hole by the high frequency sputter cleaning process through a cleaning process using a fluorine-based solution; And (J) forming the upper copper metal wiring so that the via hole and the trench is buried. The method of claim 1, And wherein the interlayer insulating film is formed of a film having a dielectric constant of 2.5 to 4.3 band. The method of claim 1, And forming a capping layer made of at least one of a nitride film, an oxynitride film, a carbide film, and an oxide film on the interlayer insulating film. The method of claim 1, In the step (c), the stripping process is performed at a temperature of 40 ° C. to 300 ° C. such that a sidewall oxide film is formed as a by-product on the sidewall of the interlayer insulating film exposed through the via hole by the oxygen gas. Wiring formation method. The method of claim 4, wherein A copper metal wiring forming method for a semiconductor device, wherein the sidewall oxide film is formed to a thickness of 5 kPa to 100 kPa. The method of claim 1, The high frequency sputter cleaning process is a method of forming a copper metal wiring of a semiconductor device is carried out in a dry manner using a plasma (plasma).