KR100532446B1 - Method for forming metal interconnection layer of semiconductor device - Google Patents

Abstract

Disclosed is a method of forming a metal wiring of a semiconductor device in which a dual damascene structure suppresses generation of fences generated around a via hole and is less affected by the density of the via hole. The method of the present invention forms a first photoresist layer pattern defining via holes after forming an interlayer insulating layer, a hard mask layer capable of acting as an antireflection film, and a photoresist layer on the semiconductor substrate. Partial etching of the hard mask layer and the interlayer insulating layer is performed by using the first photoresist layer pattern as an etch mask to form a partial via hole, and after removing the remaining first photoresist layer pattern, a front surface of the semiconductor substrate including the partial via hole. After the photoresist layer is formed in the second photoresist pattern, the second photoresist pattern defining a trench wiring region overlapping at least a portion of the partial via hole is formed while the photoresist layer remains in the partial via hole. After forming the hard mask layer pattern using the second photoresist pattern as an etching mask, the remaining second photoresist pattern is removed, and the interlayer insulating layer is partially etched using the hard mask layer pattern as the etching mask to form a trench wiring. A full via hole extending from the region and the partial via hole is formed. Subsequently, a second conductive layer is filled in the full via hole and the trench wiring region.

Description

Method for forming metal interconnection layer of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device by a dual damascene process.

As the integration degree of a semiconductor element increases, the metal wiring layer which has a multilayer wiring structure becomes necessary, and the space | interval between metal wiring becomes narrow gradually. Accordingly, parasitic resistance (R) and capacitance (C) components existing between metal wiring layers adjacent to each other on the same layer or between each wiring layer adjacent to each other up and down have become the most important problems.

In metallization systems, parasitic resistance and capacitance components degrade the device's electrical performance by delay induced by RC. In addition, parasitic resistance and capacitance components present between the wiring layers increase the total power consumption of the chip and increase the signal leakage. Therefore, it is very important to develop a multi-layered wiring technology with a small RC in an ultra-high density semiconductor device.

In order to form a high performance multilayer wiring structure with small RC, it is necessary to form a wiring layer using a metal having a low resistivity or to use an insulating film having a low dielectric constant. In order to reduce the resistance in a metal wiring layer, the research which uses the metal with low specific resistance, for example, copper as a metal material which forms a metal wiring layer, is currently active actively. Copper wiring is difficult to obtain by direct patterning by photolithography. Therefore, the dual damascene process is mainly used to form copper wiring.

1 to 3 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to a conventional example in a process sequence.

Referring to FIG. 1, a first stopper layer 104, a first interlayer insulating layer 105, a second stopper layer 106, and a first stopper layer 104 are formed on a semiconductor substrate 100 on which a predetermined first conductive layer 102 is formed. Two interlayer insulating layers 107 are formed in sequence. Subsequently, the second interlayer insulating layer 107, the second stopper layer 106, and the first interlayer insulating layer 105 are sequentially etched by a photolithography process to obtain a full via hole having a first width W1. , 112).

Subsequently, the photoresist layer is formed on the entire surface of the semiconductor substrate 100 on which the full via holes 112 are formed, and then exposed and developed to have a second width W2 larger than the first width W1. A photoresist pattern 110 is formed to partially expose the second interlayer insulating layer 107 overlapping the full via hole 112. In this case, the photoresist layer partially remains in the full via hole 112.

Referring to FIG. 2, the second interlayer insulating layer 107 is dry-etched using the photoresist pattern 110 as an etching mask until the surface of the second stopper layer 106 is exposed. By etching, a trench wiring region 114 having a second width W2 is formed in the second interlayer insulating layer 107. At this time, the photoresist layer remains in the full via hole 112, and the photoresist layer is partially etched according to the etching selectivity while the second interlayer insulating layer 107 is etched.

Referring to FIG. 3, the photoresist layer remaining in the full via hole 112 and the photoresist pattern 110 remaining on the second interlayer insulating layer 107 are removed by a conventional ashing method. Subsequently, after removing the first stopper layer 104 exposed to the bottom of the full via hole 112, a dual damascene is formed by forming a second conductive layer (not shown) in the full via hole 112 and the trench wiring region 114. The structure is complete.

According to the prior art, since the density of the via hole 112 varies depending on the region, the control of the critical dimension (CD) during the photo process due to the difference in coating thickness of the photoresist layer during the photo process for the trench wiring region 114 and It is difficult to control the profile of the pattern, and may cause a problem of poor photoresist development in the via hole 112, and subsequent etching of the trench wiring region 114 as the photoresist layer remains due to the poor development of the photoresist in the via hole 112. In this case, there is a problem in that the fence 116 is formed along the periphery of the via hole 112 by the blocking role.

4 through 6 are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to another conventional example, and illustrates a technique using a buried material layer formed in a via hole.

Referring to FIG. 4, as shown in FIG. 1, a first stopper layer 104, a first interlayer insulating layer 105, and a second interlayer insulating layer are formed on a semiconductor substrate 100 on which a predetermined first conductive layer 102 is formed. Layers 107 are formed in turn. Subsequently, the second interlayer insulating layer 107 and the first interlayer insulating layer 105 are sequentially etched by a photolithography process to form a full via hole 112 having a first width W1. Subsequently, a buried material layer 116 of organic or inorganic material is formed in the full via hole 112.

Subsequently, the photoresist layer is formed on the entire surface of the semiconductor substrate 100 on which the full via holes 112 are formed, and then exposed and developed to have a second width W2 larger than the first width W1. A photoresist pattern 110 is formed to partially expose the second interlayer insulating layer 107 overlapping the full via hole 112. In this case, the photoresist layer partially remains in the full via hole 112.

Referring to FIG. 5, a portion of the second interlayer insulating layer 107 is etched using the photoresist pattern 110 as an etching mask. By etching, a trench wiring region 114 having a second width W2 is formed in the second interlayer insulating layer 107. At this time, the photoresist layer and the buried material layer 116 remain in the full via hole 112, and the photoresist layer is partially etched according to the etching selectivity while the second interlayer insulating layer 107 is etched.

Referring to FIG. 6, after the remaining photoresist pattern 110 is removed, the buried material layer 116 is subsequently removed in the full via hole 112. Subsequently, after removing the first stopper layer 104 exposed to the bottom of the full via hole 112, a dual damascene is formed by forming a second conductive layer (not shown) in the full via hole 112 and the trench wiring region 114. The structure is complete.

According to the prior art, in order to solve the problem of the coating thickness of the photoresist layer due to the difference in density of the via hole 112 can be solved to some extent by embedding organic or inorganic material in the via hole 112, the buried material layer In the case of an organic material such as BARC (Bottom Anti-Reflection Coating) or photoresist, a fence 116 is also generated along the periphery of the via hole 112, and thus, between the first conductive layer 102 and the second conductive layer (not shown). The electrical connection may be poor, and when the buried material layer is an inorganic material such as HSQ (Hydrogen Silsesquioxane), there is a disadvantage in that the strip process for removing it is very difficult.

The technical problem to be solved by the present invention is to solve the problems of the prior art, while preventing the formation of the pattern due to the difference in the thickness of the photoresist coating caused by the difference in the density of the via holes for each region of the fence generated around the via hole The present invention provides a method for forming a metal wiring of a semiconductor device that suppresses generation, minimizes ash damage when using a low dielectric material, and can actively cope with next-generation photo processes such as ArF photoresist without etching resistance.

In addition, another technical problem to be achieved by the present invention is that when the interlayer insulating layer is etched to form the wiring region and the via hole, the stopper layer is etched and the conductive layer is exposed to the outside, so that the metal is formed on the upper portion of the conductive layer in the photoresist pattern removing process. It is possible to prevent the problem of forming an oxide layer, to prevent ashing damage caused by the ashing process, and to prevent the via hole from being opened due to the remaining photoresist in the partial via hole when forming the photoresist pattern. The present invention provides a method for forming a metal wiring of a semiconductor device, which can prevent a defective profile of a via hole even if a mis-alignment of a photoresist pattern occurs.

According to another aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: forming an interlayer insulating layer on a semiconductor substrate; Forming a hard mask layer on the interlayer insulating layer to serve as an anti-reflection film; Forming a first photoresist pattern defining a via hole on the hard mask layer; Forming a partial via hole by partially etching the hard mask layer and the interlayer insulating layer using the first photoresist pattern as an etching mask; Forming a photoresist layer on the entire surface of the semiconductor substrate including the partial via hole; Forming a second photoresist pattern defining a trench wiring region in which at least a portion of the photoresist layer overlaps with the photoresist layer in the partial via hole; Etching the hard mask layer by using the second photoresist pattern as an etching mask to form a hard mask layer pattern; Removing the remaining second photoresist pattern; Partially etching the interlayer insulating layer using the hard mask layer pattern as an etch mask to form a full via hole in which a trench wiring region and the partial via hole extend; And filling a second conductive layer in the full via hole and trench wiring region.

On the other hand, the metal wiring forming method of a semiconductor device according to the second aspect of the present invention for achieving the technical problem of the present invention, forming an interlayer insulating layer on a semiconductor substrate; Forming a hard mask layer on the interlayer insulating layer to serve as an anti-reflection film; Forming a first photoresist pattern defining a via hole on the hard mask layer; Forming a partial via hole by partially etching the hard mask layer and the interlayer insulating layer using the first photoresist pattern as an etching mask; Forming a buried material layer filling the partial via hole; Forming a photoresist layer on the entire surface of the semiconductor substrate; Forming a second photoresist pattern defining a trench wiring region at least partially overlapping the partial via hole; Etching the hard mask layer by using the second photoresist pattern as an etching mask to form a hard mask layer pattern; Removing the remaining second photoresist pattern and the buried material layer in the partial via hole; Partially etching the interlayer insulating layer using the hard mask layer pattern as an etch mask to form a full via hole in which a trench wiring region and the partial via hole extend; And filling a second conductive layer in the full via hole and trench wiring region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is described in the following embodiments. It is not limited. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements in the figures.

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<Example 1>

7 to 14 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a first embodiment of the present invention according to a process sequence.

Referring to FIG. 7, a first stopper layer 404 is formed on the semiconductor substrate 400 on which the first conductive layer 402 is formed. The first conductive layer 402 may be an impurity doped region formed in the semiconductor substrate 400 or another metal wiring layer such as a copper (Cu) wiring layer or other tungsten. The first stopper layer 404 has a high etching selectivity with respect to the first interlayer insulating layer 405 formed thereon, such as a carbide-based or nitride-based insulator, specifically, SiC, SiCN, BN, or SiN. Can be formed into one.

Subsequently, a first interlayer insulating layer 405 is formed on the first stopper layer 404. For example, the first interlayer insulating layer 405 may use any of an organic oxide or an inorganic oxide. For example, an SiOC film, a porous SiO ₂ film, a PSG (phosphorous silicate glass) film, or BPSG (boron) may be used. phosphorous silicate glass (USG) film, USG (undoped silicate glass) film, fluorine doped silicate glass (FSG) film, high density plasma (HDP) film, plasma enhanced-tetra ethyl ortho silicate (PE-TEOS) film or spin on glass A material film having a low dielectric constant such as a film can be used. The first interlayer insulating layer 405 is formed of a material film having a large etching selectivity with the first stopper layer 404. Subsequently, a second stopper layer 406 is formed on the first interlayer insulating layer 405. The second stopper layer 406 has a high etching selectivity with respect to the second interlayer insulating layer 407 formed thereon, for example, carbide-based or nitride-based insulators, specifically SiC, SiCN, BN, or SiN. Can be formed into one.

Next, a second interlayer insulating layer 407 is formed on the second stopper layer 406. The second interlayer insulating film 407 may be formed of an inorganic oxide or an organic oxide like the first interlayer insulating layer 405 described above. For example, the SiOC film, the porous SiO ₂ film, the PSG film, the BPSG film, and the USG may be used. It is preferable to form a material film having a low dielectric constant such as a film, an FSG film, an HDP film, a PE-TEOS film, or an SOG film. The second interlayer insulating layer 407 is formed of a material film having a large etching selectivity with the second stopper layer 406. The second interlayer insulating layer 407 may be formed of a material film different from that of the first interlayer insulating layer 405, but is preferably formed of the same material film as the first interlayer insulating layer 405.

Next, a hard mask layer 408 is formed on the second interlayer insulating layer 407. The hard mask layer 408 is a material layer having a high etching selectivity with respect to the second interlayer insulating film 407 and may serve as an anti-reflection layer (ARL) in a subsequent photolithography process. Do. Materials that may strongly exhibit the role of the antireflection layer include, for example, carbon nitride based insulators including SiCN, oxynitride based insulators including SiON, and carbon oxynitride based insulators including SiCON. As TaN, TiN, TiON, TaON, and the like, the role of the anti-reflection layer is weaker than these, AlN, AlON and the like.

Accordingly, the hard mask layer 408 may be formed of a single layer of materials capable of simultaneously acting as the antireflection layer, or may be combined with the above-described antireflection layer materials or combined with another material layer not serving as an antireflection layer. Can be formed. Although not sufficient as the anti-reflection layer, it is a hard mask layer material having excellent etching selectivity and interlayer insulating layers of low-k material formed under the hard mask layer 408. For example, AlO, TaO, TiO Metal oxides are included.

In the present invention, when the anti-reflective layer material is used as a single layer, the hard mask layer 408 may be formed to have a thickness of about 1000 Å and may be used. When the anti-reflective layer and the anti-reflective layer are formed of a multilayer comprising other anti-reflective layers, the multilayer Can be formed to a thickness of about 1000Å, and when the above-described antireflective material and a material that does not function as an antireflective layer are formed in multiple layers, the upper layer of the antireflective material formed on the upper layer is about 600Å It is formed to a thickness, and does not play the role of an anti-reflection layer formed on the lower layer, but the lower layer having an etch selectivity with the interlayer insulating layer below, the thickness of the metal oxide can be formed to a thickness of about 100 to 200 Å. have.

Subsequently, a first photoresist pattern 410 is formed on the hard mask layer 408 to partially expose the top surface of the hard mask layer 408 with a first width W1 corresponding to the via hole described later. That is, after the photoresist is applied on the hard mask layer 408, the photoresist is exposed and developed to form the first photoresist pattern 410.

Referring to FIG. 8, the hard mask layer 408, the second interlayer insulating layer 407, and the second stopper layer 406 are etched using the first photoresist pattern 410 as an etching mask. In this case, the hard mask layer 408 is etched using the first photoresist pattern 410 as an etch mask to form a hard mask layer pattern, and then the second interlayer insulating layer 407 and the second stopper layer are used as etch masks. 406 may be etched to form a partial via hole. By etching, the partial via hole 412 having the first width W1 is formed in the second interlayer insulating layer 407. Next, the first photoresist pattern 410 is removed. The first photoresist pattern 410 may be removed using a conventional method such as a ashing process. Referring to FIG. 9, a photoresist layer is formed on a semiconductor substrate 400 on which a partial via hole 412 is formed. In this case, a photoresist layer remains in the partial via hole 412. In addition, since the hard mask layer itself of the present invention acts as an anti-reflection film on the hard mask layer 408, a separate anti-reflection layer is not formed, but an anti-reflection layer may be additionally formed before application of the photoresist layer, if necessary. A second photo exposing and developing a portion of the hard mask layer 408 in which the trench wiring region 418 to be described later is formed, having a second width W2 greater than the first width W1 by exposing and developing the photoresist layer. The resist pattern 416 is formed. The trench wiring region 418 is formed to overlap at least a portion corresponding to the position of the partial via hole 412.

Referring to FIG. 10, the hard mask layer 408 on the second interlayer insulating layer 407 is dry-etched using the second photoresist pattern 416 as an etching mask to form a second hard mask layer pattern 408b. do. In the forming of the second hard mask pattern 408 b, the photoresist layer 416 remaining in the partial via hole 412 is simultaneously formed by etching the hard mask layer 408. It may be simultaneously etched up to the bottom, and at this time, the etching selectivity with the photoresist layer 416 at the time of etching the hard mask layer 408 is low, for example, less than 2: 1 CF ₄ , CH ₂ F ₂ It can be etched using a fluorine-containing gas, including CHF ₃ , CH ₃ F, NF ₃ , SF ₆ . At this time, the oxygen-containing gas containing O ₂ , CO, CO ₂ , nitrogen containing gas containing N ₂ , N ₂ 0, or any one or more of an inert gas containing Ar, He, Xe may be further used. have. Meanwhile, in the forming of the second hard mask pattern 408b using the second photoresist pattern 416 as an etching mask, remaining in the partial via hole 412 before etching the hard mask layer 408. The method may further include etching the photoresist layer 416 up to the bottom surface of the hard mask layer 408, in which case a mixture of one or more of an etching gas among an oxygen-containing gas, a nitrogen-containing gas, and a hydrogen-containing gas is used. Use gas. Meanwhile, in the forming of the second hard mask pattern 408b using the second photoresist pattern 416 as an etching mask, CF ₄ , CH ₂ F ₂ , CHF ₃ , CH ₃ F, NF ₃ , SF It can be etched using a fluorine-containing gas including ₆ , oxygen-containing gas containing O ₂ , CO, CO ₂ , nitrogen containing gas containing N ₂ , N ₂ 0, or containing Ar, He, Xe It may also be carried out using any one or more gases of inert gas.

On the other hand, when the hard mask layer 408 is formed of any one of metal nitrides including AlN, TaN, TiN, metal oxides including AlO, TaO, TiO, or a combination thereof, the hard mask The etching of layer 408 may be performed using a chloride containing gas comprising Cl ₂ , BCl ₃ instead of using a pullulouru containing gas.

Referring to FIG. 11, the second photoresist pattern 416 is removed. The second photoresist pattern 416 may be removed using a conventional method such as an ashing process using a mixed gas containing oxygen, nitrogen or hydrogen.

Referring to FIG. 12, an etching process is performed using the second hard mask layer pattern 408b as an etching mask. At this time, the second interlayer insulating layer 407 and the second stopper layer 406 are etched in the trench wiring region 418 to form the trench wiring region 418, and the first interlayer insulating layer in the partial via hole 412. 405 is etched to form a full via hole 412a. In the step of etching the first and second interlayer insulating layers 407 and 405 using the second hard mask layer pattern 408b as an etching mask, C ₄ F ₈ , C ₄ F ₆ , and C ₅ F ₈ may be used. CxFy-based gas containing, CH ₂ F ₂ , CHxFy-based gas comprising CH ₃ F, O ₂ , CO, Oxygen-containing gas containing CO ₂ , N ₂ , Ni-containing gas containing N ₂ 0, He, It is carried out using an inert gas containing Ar, Xe.

Referring to FIG. 13, the first stopper layer 404 exposed through the full via hole 412a is etched and removed. The removing of the first stopper layer 404 may include an oxygen-containing gas including O ₂ , CO, and CO ₂ in a fluorine-containing gas including CF ₄ , CH ₂ F ₂ , and CHF ₃ , N ₂ , and N ₂ 0. Nitrogen-containing gas or hydrogen-containing gas may be used by mixing any one or more gases.

Referring to FIG. 14, a conductive material layer such as copper or tungsten is formed in the exposed trench wiring region 418 and the full via hole 412a, and then a second conductive layer 420 is formed through a surface planarization process. In this case, the second hard mask layer pattern 408b may also be removed by etching, or the subsequent process may be performed without leaving the second hard mask layer 408b.

<Example 2 example>

15 to 20 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a second preferred embodiment of the present invention according to a process sequence.

Referring to FIG. 15, a first stopper layer 404 is formed on the semiconductor substrate 400 on which the first conductive layer 402 is formed. The first conductive layer 402 may be an impurity doped region formed in the semiconductor substrate 400 or another metal wiring layer such as a copper (Cu) wiring layer or other tungsten. The first stopper layer 404 has a high etching selectivity with respect to the first interlayer insulating layer 405 formed thereon, such as a carbide-based or nitride-based insulator, specifically, SiC, SiCN, BN, or SiN. Can be formed into one.

Subsequently, a first interlayer insulating layer 405 is formed on the first stopper layer 404. As the first interlayer insulating layer 405, an organic oxide or an inorganic oxide may be used as in the first embodiment. Subsequently, a second interlayer insulating layer 407 is formed on the first interlayer insulating layer 405. The second interlayer insulating film 407 may be formed of an inorganic oxide or an organic oxide like the first interlayer insulating layer 405 described above. The second interlayer insulating layer 407 may be formed of a material film different from that of the first interlayer insulating layer 405, but is preferably formed of the same material film as the first interlayer insulating layer 405.

Next, a hard mask layer is formed on the second interlayer insulating layer 407. The hard mask layer is a material layer having a high etching selectivity with respect to the second interlayer insulating film 407 and may serve as an anti-reflection layer (ARL) in a subsequent photolithography process. Materials that may strongly exhibit the role of the antireflection layer include, for example, carbon nitride based insulators including SiCN, oxynitride based insulators including SiON, and carbon oxynitride based insulators including SiCON. As TaN, TiN, TiON, TaON, and the like, the role of the anti-reflection layer is weaker than these, AlN, AlON and the like.

Accordingly, the hard mask layer 408 may be formed of a single layer of materials capable of simultaneously acting as the antireflection layer, or may be combined with the above-described antireflection layer materials or combined with another material layer not serving as an antireflection layer. Can be formed. Although not sufficient as the anti-reflection layer, it is a hard mask layer material having excellent etching selectivity and interlayer insulating layers of low-k material formed under the hard mask layer 408. For example, AlO, TaO, TiO Metal oxides are included.

In the present invention, as in the first embodiment, when the anti-reflection layer material is used as a single layer, the hard mask layer 408 may be formed to have a thickness of about 1000 Å, and the anti-reflection materials and the anti-reflection layer may be used. In the case of forming a multi-layered material that does not play the role of the anti-reflective material formed in the upper layer of about 600 두께 thickness, the thickness of the metal oxide that does not perform the role of the anti-reflective layer formed in the lower layer is about 100 To about 200 kPa.

Subsequently, a first photoresist pattern (not shown) is formed on the hard mask layer to partially expose the top surface of the hard mask layer with a first width W1 corresponding to the via hole described later. The hard mask layer and the second interlayer insulating layer 407 are etched using the etch mask to form a partial via hole 412 having a first width W1 in the second interlayer insulating layer 407. Next, the first photoresist pattern is removed.

Referring to FIG. 16, a buried material layer 411 is formed on the entire surface of the semiconductor substrate 400 where the partial via hole 412 is formed. The buried material layer 411 may use an organic material layer by SOD or CVD such as BARC (Bottom Anti-Reflection Coating), which is a carbon-based organic material. The buried material layer 411 may fill or partially fill the partial via hole 412. The buried material layer 411 may be formed to have an appropriate thickness on the first hard mask layer pattern 408 a. Subsequently, a photoresist layer is formed on the buried material layer 411. A second photoresist pattern exposing and developing a portion of the hard mask layer on which the trench wiring region 418, which will be described later, to have a second width W2 greater than the first width W1, is formed by exposing and developing the photoresist layer ( 416). The trench wiring region 418 is formed to overlap at least a portion corresponding to the position of the partial via hole 412.

Referring to FIG. 17, the second hard mask layer pattern may be formed by dry etching the buried material layer 411 and the hard mask layer on the second interlayer insulating layer 407 using the second photoresist pattern 416 as an etching mask. 408b). In the forming of the second hard mask pattern 408b, the buried material layer 411 remaining in the partial via hole 412 at the same time as the hard mask layer 408 is etched is lower than the bottom surface of the hard mask layer. At the same time, when the hard mask layer is etched, the etching selectivity with the photoresist layer 416 is low, for example, less than 2: 1 CF ₄ , CH ₂ F ₂ , CHF ₃ , CH ₃ It can be etched using a fluorine-containing gas including F, NF ₃ , SF ₆ . It may also be carried out using any one or more of an oxygen containing gas containing O ₂ , CO, CO ₂ , a nitrogen containing gas containing N ₂ , N ₂ 0, or an inert gas containing Ar, He, Xe. .

Meanwhile, in the forming of the second hard mask pattern 408b using the second photoresist pattern 416 as an etching mask, the buried material remaining in the partial via hole 412 before the hard mask layer is etched. The method may further include etching the layer 411 up to the bottom of the hard mask layer, wherein at least one of an etching gas among an oxygen-containing gas, a nitrogen-containing gas, or a hydrogen-containing gas is used. Meanwhile, in the forming of the second hard mask pattern 408b using the second photoresist pattern 416 as an etching mask, CF ₄ , CH ₂ F ₂ , CHF ₃ , CH ₃ F, NF ₃ , SF It can be etched using a fluorine-containing gas including ₆ , oxygen-containing gas containing O ₂ , CO, CO ₂ , nitrogen containing gas containing N ₂ , N ₂ 0, or containing Ar, He, Xe It may also be carried out using any one or more gases of inert gas.

On the other hand, when the hard mask layer is formed of any one of metal nitrides including AlN, TaN, TiN, metal oxides including AlO, TaO, TiO or a combination thereof, the hard mask layer is etched May be carried out using a chloride containing gas comprising Cl ₂ , BCl ₃ . Referring to FIG. 18, the second photoresist pattern 416 and the buried material layer 411 are removed. The second photoresist pattern 416 may be removed using a conventional method such as an ashing process using a mixed gas containing oxygen, nitrogen or hydrogen.

Referring to FIG. 19, an etching process is performed using the second hard mask layer pattern 408b as an etching mask. At this time, in the trench wiring region 418, the second interlayer insulating layer 407 is etched to form the trench wiring region 418, and in the partial via hole 412, the first interlayer insulating layer 405 is etched to form the full via hole. 412a is formed. In the step of etching the first and second interlayer insulating layers 407 and 405 using the second hard mask layer pattern 408b as an etching mask, C ₄ F ₈ , C ₄ F ₆ , and C ₅ F ₈ may be used. CxFy-based gas containing, CH ₂ F ₂ , CHxFy-based gas comprising CH ₃ F, O ₂ , CO, Oxygen-containing gas containing CO ₂ , N ₂ , Ni-containing gas containing N ₂ 0, He, It is carried out using an inert gas containing Ar, Xe.

Referring to FIG. 20, the first stopper layer 404 exposed through the full via hole 412a is etched and removed. The removing of the first stopper layer 404 may include an oxygen-containing gas including O ₂ , CO, and CO ₂ in a fluorine-containing gas including CF ₄ , CH ₂ F ₂ , and CHF ₃ , N ₂ , and N ₂ 0. Nitrogen-containing gas or hydrogen-containing gas may be used by mixing any one or more gases. Continue. After forming a conductive material layer such as copper or tungsten in the exposed trench wiring region 418 and the full via hole 412a, the second conductive layer 420 is formed through a surface planarization process. In this case, the second hard mask layer pattern 408b may also be removed by etching, or the subsequent process may be performed without removing the hard mask layer 408b.

Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited thereto, and various modifications can be made within the scope of the spirit of the present invention.

According to the present invention, by forming a via hole as a partial via hole first, and forming a photoresist layer or a buried material layer in the via hole, it is possible to suppress the photoresist thickness difference caused by the difference in density of the via holes and the adverse effect of pattern formation. It is possible to suppress the occurrence of the fence generated when forming the trench wiring region.

In addition, according to the present invention, the process can be simplified by using a hard mask layer that can act as an anti-reflection film, and when a low dielectric material is used, next-generation photoresist can be minimized and etch resistance can be minimized. It can easily cope with.

In addition, according to the present invention, when the interlayer insulating layer is etched to form the wiring region and the via hole, the stopper layer is etched so that the first conductive layer is not exposed to the outside. The same problem as the conventional method in which the metal oxide layer is formed on the upper surface does not occur. In addition, since the present invention fills the via vias with organic or inorganic materials after forming the via via holes and before forming the second photoresist pattern, the photoresist remains on the bottom of the via via holes when forming the second photoresist pattern. The same problem as the conventional one that does not open does not occur.

In addition, since the present invention fills the via vias with organic or inorganic materials after forming the via via holes and before forming the second photoresist pattern, even if a mis-alignment of the second photoresist pattern occurs, a conventional via hole profile may be used. Defect does not occur.

In the present invention, since the wiring region and the via hole are formed using the hard mask layer as an etch mask after removing the second photoresist pattern, damage caused by the ashing process appearing on the surface of the interlayer insulating film as in the prior art does not occur.

As mentioned above, although the preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.

1 to 3 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to a conventional example in a process sequence.

4 to 6 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to another conventional example, according to a process sequence.

7 to 14 are process cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to a first embodiment of the present invention in a process sequence.

15 to 20 are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to a second exemplary embodiment of the present invention according to a process sequence.

<Description of Symbols for Main Parts of Drawings>

100, 400; Semiconductor substrates 102 and 402; First conductive layer

104, 404; First stopper layers 105 and 405; First interlayer insulating layer

106, 406; Second stopper layers 107 and 407; Second interlayer insulating layer

408; Hard mask layers 110, 410, 416; Photoresist pattern

112, 412; Via hole 114,418; Trench wiring area

420; Second conductive layer

Claims (25)

Forming an interlayer insulating layer on the semiconductor substrate; Forming a hard mask layer on the interlayer insulating layer to serve as an anti-reflection film; Forming a first photoresist pattern defining a via hole on the hard mask layer; Partially etching the hard mask layer and the interlayer insulating layer to form a partial via hole; Removing the remaining first photoresist pattern; Forming a photoresist layer on the entire surface of the semiconductor substrate including the partial via hole; Forming a second photoresist pattern defining a trench wiring region in which at least a portion of the photoresist layer overlaps with the photoresist layer in the partial via hole; Etching the hard mask layer by using the second photoresist pattern as an etching mask to form a hard mask layer pattern; Removing the remaining second photoresist pattern and the photoresist layer remaining in the partial via hole together; Partially etching the interlayer insulating layer using the hard mask layer pattern as an etch mask to form a full via hole in which a trench wiring region and the partial via hole extend; And And embedding a second conductive layer in the full via hole and trench wiring region. Forming an interlayer insulating layer on the semiconductor substrate; It may serve as an anti-reflection film on the interlayer insulating layer, to form a hard mask layer formed of any one or a combination thereof selected from the group consisting of SiCN, SiON, SiCON, TaN, TiON, TaON, AlN and AlON step; Forming a first photoresist pattern defining a via hole on the hard mask layer; Partially etching the hard mask layer and the interlayer insulating layer to form a partial via hole; Forming a buried material layer filling the partial via hole; Forming a photoresist layer on the entire surface of the semiconductor substrate; Forming a second photoresist pattern defining a trench wiring region at least partially overlapping the partial via hole; Etching the hard mask layer by using the second photoresist pattern as an etching mask to form a hard mask layer pattern; Removing the remaining photoresist pattern and the buried material layer in the partial via hole; Partially etching the interlayer insulating layer using the hard mask layer pattern as an etch mask to form a full via hole in which a trench wiring region and the partial via hole extend; And And embedding a second conductive layer in the full via hole and trench wiring region. The method of claim 1 or 2, wherein the interlayer insulating layer comprises a first interlayer insulating layer and a second interlayer insulating layer. 4. The method of claim 3, further comprising a second stopper layer between the first interlayer insulating layer and the second interlayer insulating layer. 3. The first stopper layer of claim 1, further comprising a first stopper layer between the semiconductor substrate and the interlayer insulating layer, wherein the first stopper layer is exposed under the full via hole before filling the second conductive layer. Forming a metal wiring of the semiconductor device, characterized in that it further comprises the step of removing. The metal of the semiconductor device of claim 1, wherein the hard mask layer is formed of one or a combination of SiCN, SiON, SiCON, TaN, TiN, TiON, TaON, AlN, and AlON. Wiring formation method. 7. The method of claim 2 or 6, wherein the hard mask layer has a thickness of about 1000 GPa. The method of claim 1, wherein the hard mask layer is formed of a multilayer. 9. The method of claim 8, wherein the hard mask layer comprises a multilayer film composed of an antireflection film and another antireflection film. 10. The method of claim 9, wherein the thickness of the multilayer film is about 1000 GPa. 10. The method of claim 8, wherein the hard mask layer is a multilayer film including an upper layer of an anti-reflection film on an upper layer and a lower layer of an interlayer insulating layer and an lower layer of an etch selectivity on a lower portion of the hard mask layer. . The method of claim 11, wherein the lower layer is made of any one material selected from the group consisting of AlO, TaO, and TiO. 12. The method of claim 11, wherein the upper layer is about 600 GPa and the lower layer is about 100 to 200 GPa. The method of claim 1, wherein the forming of the hard mask pattern by using the second photoresist pattern as an etching mask comprises: forming a photoresist layer remaining in the partial via hole at the same time as the etching of the hard mask layer; A metal wiring forming method for a semiconductor device, characterized in that simultaneously etching up to the bottom. The method of claim 14, wherein the forming of the hard mask pattern using the second photoresist pattern as an etching mask comprises: fluorine including CF ₄ , CH ₂ F ₂ , CHF ₃ , CH ₃ F, NF ₃ , and SF _6; A metal wiring forming method of a semiconductor device, characterized in that the etching using the containing gas. The semiconductor device of claim 14, wherein the forming of the hard mask pattern using the second photoresist pattern as an etching mask comprises etching the chloride-containing gas including Cl ₂ and BCl ₃ . Metal wiring formation method. The method of claim 1, wherein the forming of the hard mask pattern by using the second photoresist pattern as an etching mask comprises: forming a photoresist layer remaining in the partial via hole before etching the hard mask layer. Forming a metal wiring of the semiconductor device, characterized in that it further comprises the step of etching to the bottom. The method of claim 15, wherein the forming of the hard mask pattern by using the second photoresist pattern as an etching mask includes an oxygen-containing gas including O ₂ , CO, and CO _2, and nitrogen including N ₂ and N ₂ 0. A method for forming metal wirings in a semiconductor device, characterized by further using any one or more of an inert gas containing a containing gas, He, Ar, Xe. The method of claim 1, wherein the etching of the interlayer insulating layer using the hard mask layer pattern as an etching mask is performed using a CF-based gas. The method of claim 19, wherein in the etching of the interlayer insulating layer using the hard mask layer pattern as an etching mask, a CHxFy-based gas including CH ₂ F ₂ and CH ₃ F, O ₂ , CO, and CO ₂ are included. And at least one or more of an oxygen-containing gas, a nitrogen-containing gas including N ₂ and N ₂ 0, and an inert gas including He, Ar, and Xe. 3. The metal line formation of claim 2, wherein the buried material layer is formed to fill a part of the partial via hole or to completely fill the partial via hole and to maintain a predetermined thickness on the hard mask layer. Way. The method of claim 2, wherein in the forming of the hard mask pattern using the second photoresist pattern as an etching mask, a buried material remaining in the partial via hole at the same time as the etching of the hard mask layer, is formed on the bottom surface of the hard mask layer. The metal wiring forming method of a semiconductor device characterized in that the etching simultaneously up to. The method of claim 22, wherein the forming of the hard mask pattern using the second photoresist pattern as an etching mask comprises fluorine including CF ₄ , CH ₂ F ₂ , CHF ₃ , CH ₃ F, NF ₃ , and SF ₆ . A metal wiring forming method of a semiconductor device, characterized in that the etching using the containing gas. The semiconductor device of claim 22, wherein the forming of the hard mask pattern using the second photoresist pattern as an etching mask is performed by using a chloride-containing gas including Cl ₂ and BCl ₃ . Metal wiring formation method. 3. The method of claim 2, wherein the forming of the hard mask pattern using the second photoresist pattern as an etching mask comprises forming a buried material layer remaining in the partial via hole before etching the hard mask layer. Forming a metal wiring of the semiconductor device, characterized in that it further comprises the step of etching to the bottom.