KR101138075B1 - Method for Forming Dual Damascene Pattern - Google Patents

Abstract

The present invention relates to a method of forming a dual damascene pattern, and more particularly, copper wiring using a porous low-K dielectric, one of the inter-metal dielectrics. the process during the dual damascene is formed, by using a double hard mask layer (dual hard mask film) in each of the etching processes for forming a via hole and a trench, by the subsequent step of O ₂ ashing (O ₂ base ashing) process The present invention relates to a double damascene pattern formation method capable of preventing damage of the porous low dielectric layer.

Description

Method for Forming Dual Damascene Pattern

1A and 1D are cross-sectional views illustrating a method of forming a conventional dual damascene pattern.

2A to 2L are cross-sectional views illustrating a method for forming a dual damascene pattern of the present invention.

<Brief description of the main parts of the drawing>

1, 121: etching target layer 3, 123: porous low dielectric film for via hole

5: hard mask film 5-1: hard mask film pattern

7 photoresist pattern 8, 130 via hole for metal wiring

125: first hard mask film 125-1: first hard mask pattern

127: second hard mask film 127-1: second hard mask film pattern

129: first photoresist pattern 131: porous low dielectric film for trench

133: third hard mask film 133-1: third hard mask film pattern

135: fourth hard mask film 135-1: fourth hard mask film pattern

137: second photoresist pattern 139: trench for metal wiring

141: copper layer 143: copper wiring

The present invention relates to a method of forming a dual damascene pattern, and more particularly, copper wiring using a porous low-K dielectric, one of the inter-metal dielectrics. the dual damascene is formed (dual damascene) of the time step, by using a double hard mask layer (dual hard mask film) in each of the etching process for forming the via hole and trench, subsequent processing O ₂ ashing (O ₂ base ashing The present invention relates to a double damascene pattern formation method capable of preventing damage to the porous low-k dielectric layer.

In general, as the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of the device continues to shrink into the sub-half-micron area, while improving performance and reliability. Circuit density at the sides is increasing.

In order to meet these demands, there is a problem in that parasitic capacitors are generated between device wirings by reducing the line width of semiconductor wirings. Therefore, it is necessary to develop dielectric materials that can be formed between metal wirings and reduce resistance between devices. The dielectric material is an insulating material having a low dielectric constant (Low-k) having a dielectric constant value of 3 or less, such as porosity oxide.

On the other hand, since the copper thin film used as a material for forming the metal wiring has a higher melting point than aluminum, the resistance to electro-migration (EM) is large, so that the reliability of the semiconductor device can be improved, and the specific resistance is high. Low signal transmission speeds can be used, making them useful interconnect materials for integration circuits.

However, since the etching property of the copper is very poor, when forming a copper wiring using an insulating material having a low dielectric constant value, the SA to simultaneously form a via hole and a wiring line connecting the lower wiring and the upper wiring. (self align) Use the dual damascene process.

The SA dual damascene process is mainly used in forming bit lines, word lines, or metal interconnections such as DRAMs, and via holes for connecting upper metal interconnections and lower metal interconnections in multilayer metal interconnection processes. Since it can be formed at the same time, there is an advantage that it is possible to prevent the step caused by the process in the metal wiring is easy to follow-up process.

A part of the dual damascene method for forming a conventional metal wiring will be described using Figs. 1A to 1D.

Referring to FIG. 1A, a porous low dielectric film 3 is formed on the etched layer 1, and then a hard mask film 5 is formed.

A photoresist layer (not shown) is formed on the hard mask layer of FIG. 1A, and then a lithography process is performed to form the photoresist pattern 7 as shown in FIG. 1B.

An etching process is performed on the hard mask layer 3 using the photoresist pattern 7 of FIG. 1B as an etching mask to form the hard mask pattern 5-1 as shown in FIG. 1C.

The ashing process is performed on the resultant of FIG. 1C to remove the photoresist pattern 7, and then the etching process is performed on the lower porous low-k dielectric layer 3 using the remaining hard mask pattern 5-1 as an etching mask. As a result, a via contact hole 8 as shown in FIG. 1D is formed.

Thereafter, after the SA double damascene process of forming a trench (not shown) as a subsequent process for the formed via contact hole, a metal layer (not shown) is embedded to form a metal wiring (not shown).

At present, as the line width of the device is reduced to 90 nm or less, a material having a dielectric constant value of 2.7 or less is used as the porous low dielectric film 3, and an amount of doping of carbon contained in the existing porous low dielectric film is controlled. In addition, the porosity in the material was increased to obtain a lower low dielectric constant (k = ˜2.3).

However, the porous low-dielectric film has a large specific surface area and is easily deteriorated by oxygen as the doped carbon content or porosity increases. That is, before or after the etching process for forming the via contact hole, or before or after the etching process for forming a trench which is a subsequent process, an O ₂ ashing process for removing the used photoresist pattern and etching mask patterns is performed. Carbon, which is a major component of the exposed porous low dielectric film, reacts with the oxygen to form a polymer, thereby depleting carbon in the low dielectric film, or increasing porosity as it flies to CO ₂ gas, thereby increasing the dielectric constant value. As a result, the characteristics of the device deteriorate, such as degradation of the low dielectric film quality and leakage of the metal wiring, thereby reducing the reliability of the wiring.

In order to improve this, the ashing gas is used instead of oxygen gas to suppress the increase of dielectric constant by minimizing ashing loss by using hydrogen (H ₂ ) or nitrogen (NH ₃ ), but this also lower ashing ratio. (rate) and residues (residue) has the disadvantage that occurs.

Accordingly, the present inventors have completed the present invention by developing a new dual damascene method that can improve the above-mentioned conventional problems without developing expensive equipment.

According to the present invention, a via hole and a trench are formed using a double hard mask in a double damascene pattern formation process consisting of vias and trenches, thereby preventing the dielectric constant value of the low dielectric interlayer insulating film from rising during the subsequent ashing process. An object thereof is to provide a method for forming a damascene pattern.

In the present invention to achieve the above object

(a) forming a porous low dielectric film for via holes on the etched layer;

(b) sequentially forming a double hard mask layer of a first hard mask layer and a second hard mask layer on the porous low dielectric layer;

(c) forming a first photoresist pattern on the second hard mask layer by a lithography process;

(d) forming a second hard mask layer pattern by performing an etching process on the second hard mask layer until the first hard mask layer is exposed using the first photoresist pattern as an etching mask;

(e) exposing the second hardmask film pattern by removing the first photoresist pattern by an ashing process on the resultant product;

(f) forming a via hole for metal wiring by performing a partial etching process on the first hard mask layer and the porous low dielectric layer for the via hole using the second hard mask layer pattern as an etching mask;

(g) forming a porous low dielectric film for trenches on the first hard mask film including the via hole for metal wiring;

(h) sequentially forming a double hard mask layer of a third hard mask layer and a fourth hard mask layer on the porous low-k dielectric layer;

(i) forming a second photoresist pattern on the fourth hard mask layer by a lithography process;

(j) forming a fourth hard mask layer pattern by performing an etching process on the fourth hard mask layer until the third hard mask layer is exposed using the second photoresist pattern as an etching mask;                     

(k) exposing the fourth hard mask layer pattern by removing a second photoresist pattern through an ashing process on the resultant;

(l) a trench for metal wiring by performing a partial etching process on the third hard mask film, the porous low dielectric film for trenches and via holes for metal wiring until the etched layer is exposed using the fourth hard mask film pattern as an etching mask; Forming a; And

(m) a method of forming a dual damascene pattern, comprising the step of embedding the planarized copper wiring on the entire surface including the trench for metal wiring.

Hereinafter, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 2A, after forming the porous low dielectric film 123 for the via hole on the etched layer 121, the double hard mask films of the first hard mask film 125 and the second hard mask film 127 are sequentially formed. Form.

In this case, the porous low-k dielectric layer forms a SiOC-based material in a thickness of 3000 to 5000 kPa by a spin on glass (SOG) method.

The first hard mask film is formed of silica carbide (SiC) or silica nitride (SiN) with a thickness of 100 to 1000 Pa by chemical vapor deposition (hereinafter referred to as "CVD").

The second hard mask layer may include silica (SiO ₂ ), low pressure-tetraethoxysilicate glass (LP-TEOS), plasma enhanced-tetraethoxysilicate glass (PE-TEOS), and fluorosilicate, which are easier to etch than the first hard mask layer. glass) or PE-SiH ₄ (plasma enhanced-silane) is formed to a thickness of 100 ~ 1000Å by CVD method.

After forming a photoresist layer (not shown) on the second hard mask layer 127 of FIG. 2A, a photo / etch process is performed to form a first photoresist pattern 129 as shown in FIG. 2B. .

Using the first photoresist pattern 129 of FIG. 2B as an etching mask, an etching process is performed on the second hard mask layer 127 until the first hard mask layer 125 is exposed. As illustrated, the second hard mask film pattern 127-1 is formed.

In this case, the etching process is performed by a plasma dry etching method using a gas such as CF ₄ , C ₄ F ₈ , C ₂ F ₆ or CHF ₃ .

Next, an ashing process is performed on the first photoresist pattern remaining on the second hard mask layer pattern 127 of FIG. 2C to remove the first photoresist pattern 129 as illustrated in FIG. 2D. do.

The ashing process is performed by using RIE ashing or RF power using O ₂ , H ₂ and NH ₃ gas.

At this time, since the first hard mask film is formed on the via hole porous low dielectric layer 123, the porous low dielectric layer is prevented from being damaged during the ashing process.                     

A partial etching process is performed on the first hard mask layer 125 and the porous low dielectric layer 123 for the via hole using the second hard mask layer pattern 127-1 exposed after the ashing process of FIG. 2D as an etching mask. As shown in FIG. 2E, the via hole 130 for metal wiring is formed.

In this case, the etching process may be performed by the same plasma dry etching method as the above method, in which the porous low-dielectric film 123 for the via hole is partially etched during etching.

In addition, as illustrated in FIG. 2F, the porous low dielectric layer 131, the third hard mask layer 133, and the fourth hard layer may be formed on the first hard mask layer including the metal wiring via hole 130 of FIG. 2E. The double hard mask film of the mask film 135 is formed sequentially.

In this case, the porous low dielectric film is formed to a thickness of 2000 ~ 5000Å by the same method as the porous low dielectric film forming method for via holes.

The third hard mask layer is formed of SiC or SiN to a thickness of 100 ~ 1000Å by using a CVD method, the fourth hard mask layer is SiO ₂ , LP-TEOS, PE- is a material that is more easily etched than the third hard mask layer TEOS, FSG or PE-SiH ₄ is formed to a thickness of 100 to 1000 mm by CVD.

A photoresist layer (not shown) is formed on the fourth hard mask layer 135 of FIG. 2F, and then a photo / etch process is performed to form the second photoresist pattern 137 as illustrated in FIG. 2G. Form.

Using the second photoresist pattern 137 of FIG. 2G as an etching mask, an etching process is performed on the fourth hard mask layer 135 until the third hard mask layer 133 is exposed. As illustrated, the fourth hard mask film pattern 135-1 is formed.

In this case, the etching process is performed in the same manner as the hard mask pattern method for forming via holes.

The second photoresist pattern 127 is formed by performing an ashing process on the second photoresist pattern 137 remaining on the fourth hard mask layer pattern 135-1 of FIG. 2H. Remove it.

The ashing process is performed by using RIE ashing or F power using O ₂ , H ₂ and NH ₃ gas.

In this case, since a third hard mask film is formed on the trench porous low dielectric layer 131, the trench porous low dielectric layer is prevented from being damaged during the ashing process.

The third hard mask layer 133, the porous low-k dielectric layer 131, and the trench may be exposed until the etched layer 121 is exposed using the fourth hard mask layer pattern 135-1 of FIG. 2I as an etch mask. A partial etching process is performed on the metallization via hole 130 to form the metallization trench 139 as shown in FIG. 2J.                     

In this case, the etching process is performed using a gas such as CF ₄ , C ₄ F ₈ , C ₂ F ₆ or CHF ₃ using a plasma dry etching method.

In addition, by applying the SA double damascene process in the process, since the organic anti-reflective coating (BARC) coating process and the BARC etching process applied during the trench etching is not used, the process step is reduced.

Referring to FIG. 2K, a copper layer 141 is embedded in the entire surface including the trench 139 for metal wiring formed in FIG. 2J, and then a planarization process using the porous low-dielectric film 131 for polishing as a polishing stop film. As shown in FIG. 2L, the copper wiring 143 from which the third hard mask layer 133 is removed is formed.

The copper layer is performed by sputtering, CVD, or electroplating. In the case of forming the electroplating method, a seed metal film (not shown) is preferably formed on the barrier metal layer and then embedded.

As described above, in the present invention, in the metal wiring forming process using the porous low dielectric film, a double hard mask film is formed on each porous low dielectric film, thereby preventing the porous low dielectric film from being damaged by a general ashing process. The constant can be prevented from increasing.

In addition, by applying the SA double damascene process in the metal wiring forming process, it is possible to delete the BARC coating and etching process applied during the trench etching, resulting in a reduction of the process step.

As described above, the present invention forms a double hard mask on top of each porous low dielectric layer during the metal wiring formation process using the porous low dielectric layer, thereby preventing damage to the porous low dielectric layer by a subsequent ashing process. The increase of the constant can be prevented.

In addition, by applying the SA double damascene process in the metal wiring forming process, it eliminates the BARC coating and etching process applied during the trench etching, resulting in a reduction of the process step.

Claims (20)

(a) forming a porous low dielectric film for via holes on the etched layer; (b) sequentially forming a double hard mask layer of a first hard mask layer and a second hard mask layer on the porous low dielectric layer, and forming a first photoresist pattern on the second hard mask layer; (c) etching the second hard mask layer using the first photoresist pattern as an etching mask to form a second hard mask layer pattern; (d) removing the first photoresist pattern by performing an ashing process, and then performing a partial etching process on the first hard mask layer and the porous low dielectric layer for the via hole using the second hard mask layer pattern. Forming a wiring via hole and removing the second hard mask layer pattern; (e) forming a porous low dielectric film for trenches on the first hard mask film including the via holes for the metallization; (f) sequentially forming a double hard mask layer of a third hard mask layer and a fourth hard mask layer on the porous low-k dielectric layer, and forming a second photoresist pattern on the fourth hard mask layer; (g) etching the fourth hard mask layer to form a fourth hard mask layer pattern by using the second photoresist pattern as an etch mask so that the open region covers the via hole region for the metallization; (h) removing the second photoresist pattern by performing an ashing process, and using the fourth hard mask layer pattern as an etch mask, the third hard mask layer and the porous low dielectric layer for the trench until the etched layer is exposed. And forming a trench for metal wiring by performing a partial etching process on the metal wiring via hole, and removing the fourth hard mask pattern. And (i) embedding the planarized copper wiring on the entire surface including the trench for metal wiring. The method of claim 1, The via hole porous low-dielectric film is a dual damascene pattern forming method characterized in that the SiOC-based material formed by a spin on glass (SOG) method. The method of claim 1, The via-hole porous low-dielectric film is a double damascene pattern forming method characterized in that formed in 3000 ~ 5000Å thickness. The method of claim 1, The first hard mask layer is formed of silica carbide (SiC) or silica nitride (SiN), wherein the dual damascene pattern forming method. The method of claim 1, And said first hard mask film is formed to a thickness of 100 to 1000 GPa. The method of claim 1, The second hard mask layer may be formed of silica (SiO ₂ ), LP-TEOS (low pressure-tetraethoxysilicate glass), PE-TEOS (plasma enhanced-tetraethoxysilicate glass), FSG (fluorosilicate glass) or PE-SiH ₄ (plasma enhanced-silane) Double damascene pattern forming method, characterized in that formed as. The method of claim 1, And said second hard mask film is formed to a thickness of 100 to 1000 GPa. The method of claim 1, The via hole forming etching process is performed by a plasma dry etching method using CF ₄ , C ₄ F ₈ , C ₂ F ₆ or CHF ₃ gas. delete The method of claim 1, The first photoresist pattern removing process is performed using O ₂ , H ₂ and NH ₃ gas. The method of claim 1, The trench low dielectric film is a double damascene pattern forming method characterized in that the SiOC-based material formed by a spin on glass (SOG) method. The method of claim 1, The trench low-dielectric film forming method of the double damascene pattern, characterized in that formed in 2000 ~ 5000Å thickness. The method of claim 1, The third hard mask film is a double damascene pattern formation method, characterized in that formed of SiC or SiN. The method of claim 1, And said third hard mask film is formed to a thickness of 100 to 1000 GPa. The method of claim 1, The fourth hard mask layer is formed of SiO ₂ , LP-TEOS, PE-TEOS, FSG, or PE-SiH ₄ . The method of claim 1, And said fourth hard mask film is formed to a thickness of 100 to 1000 GPa. The method of claim 1, The trench forming etching process may be performed by a plasma dry etching method using CF ₄ , C ₄ F ₈ , C ₂ F _6, or CHF ₃ gas. delete The method of claim 1, The second photoresist pattern removal process is performed using O ₂ , H ₂ and NH ₃ gas. The method of claim 1, The copper wirings are formed by sputtering, chemical vapor deposition (CVD), or electroplating.

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