KR101005738B1 - Method for forming a dual damascene pattern in semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a dual damascene pattern of a semiconductor device, and includes a etch stop layer or a diffusion barrier layer formed of a nitride material by depositing a liner oxide along a top surface of a structure after via holes are formed. Dual damascene pattern of a semiconductor device capable of preventing via hole poisoning and etch stop in an isolated via hole by preventing direct contact with a photoresist pattern formed through this subsequent process. A formation method is disclosed.

Via hole poisoning phenomenon, liner oxide

Description

Method for forming a dual damascene pattern in semiconductor device             

1 to 7 are cross-sectional views illustrating a method of forming a dual damascene pattern of a semiconductor device according to an exemplary embodiment of the present invention.

FIG. 8 is a SEM photograph in which via hole poisoning occurs by a dual damascene pattern formation process according to the related art.

Description of the Related Art

10 semiconductor substrate 12 semiconductor structure layer

14: first interlayer insulating film 16: lower metal wiring

18 diffusion barrier film 20 second interlayer insulating film

22: etch stop film 24: third interlayer insulating film

26 capping layer 28 first antireflection film

30: via hole etching mask 32: via hole

34 liner oxide film 36 second antireflection film

38: trench etching mask 40: trench

The present invention relates to a method for forming a dual damascene pattern of a semiconductor device. In particular, a via hole poisoning phenomenon and an etch stop phenomenon in an isolated via hole may be prevented. A method for forming a dual damascene pattern of a semiconductor device.

In a semiconductor device or an electronic device, a conductor film such as aluminum (Al) or tungsten (W) is deposited on an insulating film as a metal wiring forming technique, and then the conductor film is subjected to a conventional photolithography process and dry etching ( The technique of forming metal wiring by patterning through dry etching process has been established and widely used in this field. In particular, recently, a method of using a low-resistance metal such as copper (Cu) instead of aluminum or tungsten as wiring to reduce the RC delay centering on logic devices requiring high integration and high performance among semiconductor devices has recently been used. Is being studied. In RC, 'R' represents wiring resistance, and 'C' represents dielectric constant of the insulating film.

The metallization process using copper is more difficult to pattern than the metallization process using aluminum or tungsten. Accordingly, a so-called 'damascene' process is used in which a trench is first formed and a metal wiring is formed to fill the trench. Commonly used damascene processes include a single damascene process and a dual damascene process. The single damascene process is a method of forming a via hole and then filling the via hole with a conductive material, forming a wiring trench on the upper portion thereof, and then filling the trench with a wiring material to form a metal wiring. The dual damascene process is a method of forming a metallization by forming a via hole and a wiring trench, and subsequently filling the wiring material with the via hole and the wiring trench. In addition, various methods are suggested.

However, in such various damascene pattern formation processes, misalignment between the via hole and the trench occurs due to the limitation of the stacking capability of the exposure apparatus. As a result, the interlayer insulating film etching process for embedding the copper metal wiring is subject to many limitations. In addition, a via hole poisoning phenomenon occurs as shown in FIG. 8 during the interlayer insulating layer etching process. In addition, an etch stop phenomenon occurs in an isolated via hole (that is, a via hole formed to be separated from an area where the via hole is densely formed).

The via hole poisoning phenomenon occurs after the via-via is first formed through a dual damascene process, that is, a dry etching process in a pre-via manner, and a pattern of an etching mask for forming a trench for forming a trench is patterned. The cause is caused by the use of N ₂ gas and NH ₃ gas used in the via hole dry etching process and the photoresist pattern removal process, and the gas containing the nitrogen component during film deposition, that is, the NH ₃ gas. It is reported. For example, the via hole poisoning may occur in a process of forming an etching mask for forming a trench. Generally, the acidic H ⁺ generated at a site exposed by an alkaline developer in a developing process performed by applying a photoresist and using a photo mask is neutral (H ₂ O). Should change and dissolve. However, as the H ⁺ remains in the via hole without dissolving to the upper part of the via hole by NH ⁺ , NH ₂ ⁺ , NH ₃ ⁺ and the like remaining in the via hole, a mushroom-like poisoning phenomenon occurs.

The etch stop phenomenon of the isolated via hole is generated by a carbon component in the interlayer insulating film when the dielectric constant is formed using an OSG (Organo Silica Glass) film having a dielectric constant of 2.0 to 2.8. This is because the area of the photoresist pattern around (ie, the area where the via hole is not formed) is larger than the area of the photoresist pattern around the isolated via hole in the via hole forming process. In addition, in order to lower the interlayer capacitance between the lower metal wiring and the upper metal wiring, SiC having a low dielectric constant is used as an etch stop film or a copper diffusion preventing film. _x H _y F _z (1≤x≤5, 1≤y≤8, 1≤z≤3) If the dry etching process using gas as the main etching gas is used, the C / F ratio can only be increased. none. As a result, an etching stop phenomenon occurs in which the etching is not performed stably in the isolated via hole, but the etching is stopped during the process.

Accordingly, a preferred embodiment of the present invention is to form a dual damascene pattern of a semiconductor device capable of preventing via hole poisoning and etch stop in an isolated via hole. The purpose is to provide a method.

In accordance with an aspect of the present invention, there is provided a method of forming a dual damascene pattern of a semiconductor device, the method including: providing a semiconductor substrate on which a lower metal wiring is formed; And forming a via hole by patterning the first and second interlayer insulating layers through an etching process using a via hole etching mask, forming a liner oxide film along an inner surface of the via hole, and filling the via hole. Removing the liner oxide layer by exposing the anti-reflective layer so that the anti-reflective layer is deposited, forming the trench through an etching process using a trench etching mask, and cleaning process using a fluorine-based solution to expose the diffusion barrier layer; Removing the exposed portion of the diffusion barrier to expose a portion of the lower metal wiring It characterized in that it comprises.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to inform you completely.

1 to 7 are cross-sectional views illustrating a method of forming a dual damascene pattern of a semiconductor device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 7 are the same components having the same function.

Referring to FIG. 1, a semiconductor substrate 10 having a predetermined semiconductor structure layer 12 formed thereon is provided. The semiconductor structure layer 12 may include a transistor, a memory cell, a capacitor, a junction layer, a conductive layer, and the like. Subsequently, on the semiconductor structure layer 12, as a low dielectric material, for example, PLAEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), FSG (Fluorinated Silicate Glass), silicon oxide, fluorine-containing silicon oxide Alternatively, an insulating film (hereinafter referred to as 'first interlayer insulating film') 14 is deposited using fluorine-containing oxide or the like. In general, fluorine-containing silicon oxide has a lower dielectric constant than silicon oxide, and the dielectric constant can be controlled by adjusting the fluorine content. After the first interlayer insulating film 14 is formed, a lithography process is performed to form contact holes (not shown) in the first interlayer insulating film 14, and the lower metal wiring 16 is sequentially formed to fill the contact holes. Is formed. In this case, the lower metal wire 16 may be formed of any one metal material among Cu, W, Al, Pt, Pd, Ru, St, Rh, and Co. It is preferable to form Cu in consideration of the characteristics of the device. Meanwhile, a barrier film may be formed on the inner surface of the contact hole before the lower metal wiring 16 is deposited. In this case, the barrier film may include Ta, TaN, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, Any one of Co and CoSi ₂ or these may be formed in a stacked structure of at least two layers.

After the lower metal wiring 16 is formed, a diffusion barrier 18, a second interlayer dielectric 20, a third interlayer dielectric 24, a capping layer 26, and a first antireflection layer are formed over the entire structure. 28 is formed. The diffusion barrier 18 may be formed of SiN, SiC, SiON, or the like, but is preferably formed of SiN or SiON in consideration of an etching selectivity between the second interlayer insulating films 20 formed of an OSG film. It is formed to a thickness of. The second interlayer insulating film 20 is formed of an OSG film, and has a thickness of 1000 kPa to 7000 kPa. The third interlayer insulating film 24 is formed of an OSG film in the same manner as the second interlayer insulating film 20, and is formed to have a thickness of 1000 GPa to 7000 GPa. The capping layer 26 may be formed of SiON, SiN, or the like. The first anti-reflection film 28 may be formed of an organic material or an inorganic material. Subsequently, after the photoresist (not shown) is applied to the entire structure, a photoresist pattern (hereinafter referred to as a “via hole etching mask”) 30 is formed by sequentially performing an exposure process and a development process using a photo mask. . In this case, an etch stop layer 22 may be formed between the second and third interlayer insulating layers 20 and 24. In this case, the etch stop layer 22 may be formed of SiN, SiC, SiON, etc., but SiN or SiON in consideration of the etching selectivity between the second and third interlayer dielectric layers 20 and 24 formed of OSG films. It is preferably formed of, and is formed from 100 kV to 1500 kV.

Referring to FIG. 2, the first anti-reflection film 28 exposed through the etching process using the via hole etching mask 30 is patterned. In this case, the etching process is performed by a dry etching process, at least one of O ₂ , N ₂ and C _x F _y H _z (1≤x≤5, 1≤y≤8, 1≤z≤3). It is performed using main etching gas and additive gases, such as Ar and He. As a result, a part of the capping layer 26 is exposed through the patterned first anti-reflection film 28.

Referring to FIG. 3, a via hole 32 is formed by performing a patterning process of the first anti-reflection film 28 and an in-situ etching process using the via hole etching mask 30 in FIG. 2. . In this case, the etching process is carried out by a dry etching method, the etching gas using C _x F _y H _z (1≤x≤5, 1≤y≤8, 1≤z≤3) and O ₂ , N ₂ , Ar, He gas, etc. are used. Thereafter, the via hole etching mask 30 is removed through a strip process. A liner oxide 34 is then deposited along the steps of the top surface of the entire structure. In this case, the liner oxide layer 34 may be formed of TEOS (Tetra Ethyle Ortho Silicate), LTO (Low Temperature Oxide), or the like, and has a thickness of 30 kV to 1500 kPa. Here, the liner oxide layer 34 may include a photoresist pattern for the subsequent trench etching mask 38 (see FIG. 4), and a capping layer 26, an etch stop layer 22, or a diffusion barrier layer 18 formed of a SiN layer. Prevents direct contact. In addition, the liner oxide layer 34 functions to prevent the second and third interlayer dielectric layers 20 and 24 from being exposed to the outside and oxidized.

Referring to FIG. 4, after the via hole 32 is formed in FIG. 3, a second anti-reflection film 36 is deposited to fill the via hole 32. In this case, the second anti-reflection film 36 may be deposited with an organic material or an inorganic material. Subsequently, after the photoresist (not shown) is applied to the entire structure, a photoresist pattern (hereinafter referred to as a trench etch mask) 38 is formed by sequentially performing an exposure process and a development process using a photomask. .

Referring to FIG. 5, the trench 40 is formed by performing an etching process using the trench etching mask 38 formed in FIG. 4. In this case, the etch stop layer 22 is used as a barrier during the etching process. The etching process may be performed such that the etching rate between the liner oxide layer 34 and the third interlayer insulating layer 24 is the same. To this end, the etching process is to change the C / F ratio when the C _x F _y H _z (1≤x≤5, 1≤y≤8, 1≤z≤3) gas as the main etching gas (that is, It can be easily controlled by adjusting the x, y ratio or adjusting the amount of added gas O ₂ , N ₂ ). Thereafter, the trench etch mask 38 is removed through a strip process. After the strip process, the cleaning process may be performed on the entire structure.

Referring to FIG. 6, the liner oxide layer 34 remaining in FIG. 5 is removed. In this case, the liner oxide layer 34 is removed through a cleaning process using a fluorine-based solution such as HF or BOE (Buffered Oxide Etchant). The reason why only the liner oxide film 34 is removed is that the second and third interlayer insulating films 20 and 24 are formed of OSG films. That is, the OSG film has a high selectivity to fluorine-based solutions such as HF or BOE. Accordingly, when the cleaning process is performed using the fluorine-based solution, it is possible to selectively remove only the liner oxide film 34. As a result, the diffusion barrier 18 is exposed through the via hole 32 and the trench 40.

Referring to FIG. 7, the diffusion barrier layer 18 exposed in FIG. 6 is removed by performing an etching process using a dry etching method. As a result, the lower metal wiring 16 is exposed through the via hole 32 and the trench 40. Thereafter, an upper metal wiring (not shown) is formed in the via hole 32 and the trench 40 through a general process.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In particular, in the preferred embodiment of the present invention, the pre-via method is applied in the dual damascene pattern forming method, but this is applicable to the post-via method as an example. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after the via hole is formed, a liner oxide film is deposited along the upper surface of the entire structure so that an etch stop film or a diffusion barrier film made of a nitride material is in direct contact with the photoresist pattern formed through a subsequent process. This prevents via hole poisoning and etch stops in isolated via holes.

Claims (7)

Providing a semiconductor substrate having a lower metal wiring formed thereon; Sequentially stacking a diffusion barrier, a first interlayer dielectric, and a second interlayer dielectric on the entire structure; Forming via holes by selectively patterning the second interlayer insulating layer and the first interlayer insulating layer through an etching process using a via hole etching mask; Forming a liner oxide film along an inner surface of the via hole including an upper portion of the second interlayer insulating film; Depositing an anti-reflection film so as to fill the via hole on the liner oxide film; Forming a trench by selectively removing the anti-reflection film, the liner oxide film, the second interlayer insulating film, and the first interlayer insulating film through an etching process using a trench etching mask; Performing a cleaning process using a fluorine-based solution to remove the liner oxide layer to expose the diffusion barrier layer; And And removing the exposed portion of the diffusion barrier layer to expose the lower metal wiring. The method of claim 1, And the first and second interlayer dielectric layers are formed of OSG. The method of claim 1, And forming an etch stop layer functioning as a barrier during the trench formation process between the first and second interlayer insulating layers. The method of claim 1, The liner oxide layer is a dual damascene pattern forming method of the semiconductor device, characterized in that formed by Teos (Tetra Ethyle Ortho Silicate) or LTO (Low Temperature Oxide). The method of claim 1, The diffusion barrier layer is formed of SiN or SiON dual damascene pattern forming method of a semiconductor device. The method of claim 1, And a capping layer formed of a SiN or SiON film on the second interlayer insulating film. The method of claim 1, A method for forming a dual damascene pattern of a semiconductor device, characterized in that HF or BOE solution is used as the fluorine solution used in the cleaning process.

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