KR20030057902A - Method of forming a dual damascene pattern in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a dual damascene pattern of a semiconductor device is provided to be capable of improving etching profile and processing margin by compensating etching damage when forming a trench. CONSTITUTION: A metal diffusion barrier layer(34), the first insulating layer(35), an etch stop layer(36), the second insulating layer(37) and the first anti-reflective layer are sequentially formed on a semiconductor substrate(31) having metal lines(33). A via hole(40a) is formed to expose the metal diffusion barrier layer(34). After removing the first anti-reflective layer, the second anti-reflective layer is formed on the second insulating layer and in the via hole. After partially removing the second anti-reflective layer, the third insulating layer is formed on the exposed second and first insulating layer. A trench(40b) is then formed by selectively etching the second insulating layer. After entirely removing the second anti-reflective layer, the metal diffusion barrier layer is removed to expose the metal lines(33).

Description

Method of forming a dual damascene pattern in a semiconductor device

The present invention relates to a method of forming a dual damascene pattern of a semiconductor device, and more particularly, to a method of forming a dual damascene pattern of a semiconductor device capable of improving an etching profile of a dual damascene pattern formed of a via hole and a trench.

In the CMOS device, a method of reducing the gate delay time by reducing the gate length is used as a method for improving the operation speed of the device. However, as the device becomes highly integrated, an operation speed of the device is determined by a resistance capacitance delay caused by back end of line (BEOL) metallization.

In order to reduce this RC delay, trenches in which via holes and metal wirings are formed in the interlayer insulating film by a dual damascene process while forming a metal wiring using copper having low resistance and an interlayer insulating film with an insulating material having a low dielectric constant are used. Form simultaneously.

In the dual damascene process, trenches are first formed and via holes are formed, and via holes are first formed and trenches are formed. Among them, the method of forming the via holes first and forming the trenches is more popular than the previous method because the mask process is easy.

Hereinafter, a dual damascene pattern formation method according to the dual damascene process of the prior art will be described.

1A to 1D are cross-sectional views of a device for describing a dual damascene pattern forming method of a semiconductor device according to the prior art, and FIGS. 2A to 2D are cross-sectional photographs at the step of forming a dual damascene pattern.

Referring to FIG. 1A, a first interlayer insulating film 12 is formed on a semiconductor substrate 11 on which various elements (not shown) for forming a semiconductor device are formed, and a trench is formed in the first interlayer insulating film 12. Then, a metal material is embedded in the trench to form the metal wiring 13. A barrier metal layer (not shown) is formed at the interface between the metal wiring 13 and the interlayer insulating film 12. At this time, the metal wiring 13 is made of copper.

Subsequently, a metal diffusion barrier 14, a first insulating layer 15, an etch barrier 16, a second insulating layer 17 and a first antireflection layer 18 made of an organic material are sequentially formed on the entire upper portion. . As a result, a second interlayer insulating film is formed, and a first photoresist pattern 19 is formed on the anti-reflection film 18 to expose a region where a via hole is to be formed. The metal diffusion barrier 14 is formed of a nitride film.

Referring to FIG. 1B, the antireflection film 18, the second insulating film 17, the etch stop film 16, and the first insulating film 15 may be etched by an etching process using the first photoresist pattern 19 as an etching mask. The via hole 20a is formed. Thereafter, the first photoresist pattern 19 and the first anti-reflection film 18 are removed.

At this time, an etching process is performed such that an etching rate difference is generated between the insulating film and the metal diffusion barrier layer without the difference in the etching rate between the insulating film and the etching prevention film. In the etching process, the etching is stopped in the metal diffusion barrier 14, thereby forming the via hole 20a on the metal diffusion barrier 14.

Referring to FIG. 1C, the second anti-reflection film 21 made of organic material is formed on the second insulating film 17, and the via hole 20a and the lower metal diffusion barrier film during the etching process for forming the trench in a subsequent process ( In order to prevent the 14 from being etched, the via hole 20a is filled with the second anti-reflection film material 21a by using a flow characteristic of the second anti-reflection film 21. A second photoresist pattern 22 is then formed to expose the region where the trench is to be formed.

Referring to FIG. 1D, the trench 20b is formed by etching the second anti-reflection film 21 and the second insulating film 17 by an etching process using the second photoresist pattern 22 as an etching mask. In this case, while the second anti-reflection film material embedded in the via hole 20a is removed, the exposed metal diffusion barrier 14 is also removed at the same time so that the metal wiring 13 is exposed under the via hole 20a. As a result, the dual damascene pattern 20 including the trench 20b and the via hole 20a is formed. Thereafter, the first photoresist pattern and the second anti-reflection film are removed.

Referring to the problem of the dual damascene process proceeds to the above process step is as follows.

First, as shown in FIG. 2A and FIG. 2B, the thickness of the organic anti-reflection film material 21a filled in the via hole varies according to the pattern density and the via hole size. That is, the larger the via hole size, the larger the via hole density, the less organic anti-reflective coating material is filled in the via hole. It is etched 17a and the etching profile characteristic is reduced.

Second, in the process of etching the trench, a thinning phenomenon occurs in which the anti-reflection film on the second insulating film becomes thinner. As a result, it is difficult to control the etching amount during the etching process of forming the trench while removing the organic anti-reflection film material embedded in the via hole, and as shown in FIGS. 2C and 2D, the second insulating film ( 17) the thickness is different. Therefore, since a high selectivity with the etch stop layer is required, it is difficult to set the etching conditions and the etching profile characteristics are lowered.

Accordingly, the present invention provides an anti-reflection film of a thinly formed portion in the process of forming an anti-reflection film made of organic material on the inside of the via hole and the top of the insulating film in order to prevent the etching damage from occurring in the insulating film by the etching process for forming the trench. By re-depositing the insulating film in the region where the anti-reflective film has been removed and replenishing the thickness, it compensates for the etching damage generated in the insulating film during the etching process to form a trench to secure a process margin and improve the etching profile to solve the above problems. The purpose of the present invention is to provide a method for forming a dual damascene pattern of a semiconductor device which can solve the same and improve the reliability of the process.

1A to 1D are cross-sectional views of a device for explaining a dual damascene pattern forming method of a semiconductor device according to the prior art.

2A to 2D are cross-sectional photo images in the step of forming a dual damascene pattern.

3A to 3F are cross-sectional views of a device for explaining a dual damascene pattern forming method of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 31: semiconductor substrate 12, 32: interlayer insulating film

13, 33: metal wiring 14, 34: metal diffusion barrier

15, 35: first insulating film 16, 36: etching prevention film

17, 37: second insulating film 17a: sidewall etching damage of the second insulating film

18, 38: 1st anti-reflective film 19, 39: 1st photoresist pattern

20a, 40a: Via Hole 20b, 40b: Trench

20, 40: dual damascene pattern 21, 41: second antireflection film

21a, 41a: second antireflection film material 22, 42: second photoresist pattern

43: third insulating film

In the method of forming a dual damascene pattern of a semiconductor device according to the present invention, after forming a via hole in the interlayer insulating film on the lower metal wiring, an insulating film is formed on the exposed surface of the interlayer insulating film to compensate for the etching damage caused in the subsequent trench etching process. It is characterized by further depositing.

In the method of forming a dual damascene pattern of a semiconductor device according to another embodiment of the present invention, a metal wiring is formed and a semiconductor in which a metal diffusion barrier, a first insulating layer, an etch barrier, a second insulating layer, and a first antireflection layer are sequentially formed on the entire upper portion. Providing a substrate, forming a via hole exposing the metal diffusion barrier layer, removing the first antireflection layer, and filling the second hole with a second antireflection layer in the via hole while the second antireflection layer is formed on the second insulating layer. Removing the second antireflection film thinly formed on the surfaces of the first and second insulating films, forming a third insulating film on the exposed surfaces of the first and second insulating films, and forming a second insulating film in a predetermined region. Removing the trench to form the trench, removing the second anti-reflection film formed in the via hole, and removing the metal diffusion prevention film to expose the metal wiring. To step it characterized by comprising.

In the above, the insulating film described in the embodiment of the present invention and the third insulating film described in the other embodiment are formed by the LPD method and selectively formed only on the exposed surface of the interlayer insulating film. The LPD method is characterized in that SiOF is selectively formed only on top of an insulating film containing silicon and oxide by dipping a semiconductor substrate in a mixed aqueous solution in which H ₃ BO ₃ is added to a supersaturated H ₂ SiF ₆ aqueous solution at room temperature.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

3A to 3F are cross-sectional views of devices for describing a dual damascene pattern forming method of a semiconductor device according to the present invention.

Referring to FIG. 3A, a first interlayer insulating film 32 is formed on a semiconductor substrate 31 on which various elements (not shown) for forming a semiconductor element are formed, and a predetermined pattern is formed on the first interlayer insulating film 32. After the trench is formed, the metal wiring 33 is formed by burying a metal material in the trench. A barrier metal layer (not shown) is formed at the interface between the metal wiring 33 and the interlayer insulating film 32. At this time, the metal wiring 33 is made of copper.

Subsequently, the metal diffusion barrier film 34, the first insulating film 35, the etch stop film 36, the second insulating film 37, and the first anti-reflection film 38 made of organic materials are sequentially formed on the entire upper portion. As a result, a second interlayer insulating film is formed, and a first photoresist pattern 39 is formed on the anti-reflection film 38 to expose a region where a via hole is to be formed.

In the above, the metal diffusion barrier 34 is formed of a nitride film, and is formed to a thickness of 500 to 1000 kPa by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method. The first insulating film 35 is made of a low-k material, and is deposited by 4000 to 6000 kV by PECVD. The anti-etching film 36 is formed of a nitride film, and is formed to be 500 to 1000 mW by PECVD. The second insulating film 37 is made of SiO ₂ or a material having a low dielectric constant, and is formed to have a thickness of 3000 to 5000 kPa by the PECVD method.

Referring to FIG. 3B, the first antireflection film 38, the second insulating film 37, the etch stop film 36, and the first insulating film 35 may be formed by an etching process using the first photoresist pattern 39 as an etching mask. The via holes 40a are formed by etching. Thereafter, the first photoresist pattern 39 and the first anti-reflection film 38 are removed.

In the above, in order to form the via holes 40a, the first anti-reflection film 38 is etched first. The etching process of the first anti-reflection film 38 is performed in an etching apparatus generating low ion density of about 1E10ion / cm ³ , maintaining a pressure of 1000 to 1500 mTorr, and applying a bias of 800 to 1200 Watt. proceeds while supplying CHF _3, CF ₄ and Ar in the state. At this time, the supply amount of CHF ₃ is 40 to 60 sccm, the supply amount of CF ₄ is 100 to 150 sccm, the supply amount of Ar is 1000 to 1500 sccm. Meanwhile, the etching process of etching the first anti-reflection film 38 in the region where the via hole is to be formed is performed by excessive etching to remove the first anti-reflection film 38 and simultaneously expose the exposed second insulating film 37 at about 1000 to 2000 kPa. Etch it.

In the process of forming the via hole 40a by etching the second insulating layer 37, the etch stop layer 36, and the first insulating layer 35, it is very important to set the etching conditions according to the etching rate difference of the etching material.

In general, in the etching process of forming the dual damascene pattern, the second insulating film, the anti-etching film, and the first insulating film are first etched to form via holes while the etching conditions are adjusted so that the insulating film and the nitride film are etched at the same speed. The second etching process is performed by forming a trench by second etching the second insulating film while the etching condition is adjusted again to maximize the etching selectivity between the nitride film and the nitride film.

At this time, when the thickness of the etch barrier layer is thicker than 500 Å to 1000 Å, a slight etch rate difference between the etch barrier and the insulation layer causes a large slope in the etching profile, and the thickness of the insulation layer for forming the via hole is 3000 Å or less. The thinner the thickness, the harder it is to set the etching conditions.

Accordingly, in the present invention, the second insulating film 37 is etched in the state where the etching selectivity between the insulating film and the nitride film is as secured as possible so that the etching is completed in the etch stop layer 36, and the etching film is etched so that the insulating film and the nitride film are etched at the same speed. Etching the etch stop layer 36 under controlled conditions, and etching the first insulating layer 35 while maximizing the etch selectivity between the insulating layer and the nitride layer so that the etch stops in the metal diffusion barrier layer 34. The via hole 40a is formed through a three-step etching process.

The etching process of the first insulating film 35 or the second insulating film 37 performed in a state where the etching selectivity is secured to the maximum is performed by using gases having a high C / F ratio (C ₄ F ₈ , C ₅ F ₈ , ...). Hydrogen to remove free fluorine generated by plasma by adding gas (CH ₂ F ₂ , ...) containing hydrogen (Hydrogen) By using the characteristics, the conditions that favor the generation of the polymer, and the method of maintaining the passivation layer (Passivation Layer) of the sidewalls of the via holes by adjusting the amount of O ₂ flow.

The etching process using the above method is performed in an etching apparatus generating low ion density of about 1E10ion / cm ³ , maintaining a pressure of 30 to 50 mTorr, a source power of 1800 to 2000 Watts and a 1500 to 1700 Watts in the bias power applied state, and the process proceeds while supplying C ₄ F ₈ and C ₅ F _8, and any one, CH ₂ F _2, O ₂ and Ar in. At this time, the supply amount of C ₄ F ₈ or C ₅ F ₈ is 15 to 25 sccm, the supply amount of CH ₂ F ₂ is 5 to 10 sccm, the supply amount of O ₂ is 10 to 15 sccm, the supply amount of Ar is 400 to 600 sccm.

The etching process of the anti-etching film 36, which is performed under the condition that the etching conditions are adjusted so that the insulating film and the nitride film have the same etching rate, is performed in an etching apparatus generating low density ions of about 1E10ion / cm ³ , and the pressure is 50 to 70mTorr maintained, and the process proceeds while supplying CHF _3, CF ₄ and Ar in the device by applying a power of 1800 to 1300 to the power source 2200Watt 1600Watt state. At this time, the supply amount of CHF ₃ is 20 to 30 sccm, the supply amount of CF ₄ is 50 to 80 sccm, the supply amount of Ar is 400 to 600 sccm.

Thereafter, a strip process using an O ₂ plasma is used to remove the polymer and the first photoresist pattern 39 generated during the etching process.

Referring to FIG. 3C, the second anti-reflection film 41 made of organic material is formed on the second insulating film 37 to a thickness of 500 to 1000 Å, and the via hole 40a is formed during the etching process to form the trench in a subsequent process. In order to prevent the lower metal diffusion barrier 34 from being etched, the via hole 40a is filled with the second anti-reflective coating material 41a by using a flow characteristic of the second anti-reflection coating 41. A second photoresist pattern 42 is then formed to expose the region where the trench is to be formed. In this case, if the second anti-reflection film 41 is formed too thick, the second anti-reflection film 41 may be excessively etched during the etching process of the second anti-reflection film 41, thereby forming the second anti-reflection film 41 to an appropriate thickness.

In the above description, the thickness of the second anti-reflection film 41 formed on the second insulating film 37 and the second anti-reflection film buried in the via hole 40a are increased according to the area having a large number of via holes 40a per unit area and a small area. The amount of material 41a varies, respectively. That is, a large amount of the second anti-reflective coating material 41a is required to fill all of the via holes 40a in an area having a large number of via holes 40a per unit area, and a small amount of via holes 40a may be used in a small area. Can be landfilled. However, since the amount of the second anti-reflection film material 41a formed per unit area is the same, the amount of the second anti-reflection film material 41a buried in the via hole 40a is relatively large in the region where the number of the via holes 40a is large. Decreases. For this reason, in the region where the number of the via holes 41a is large, the second anti-reflection film material 41a is filled in the via holes 41a little by little to expose the sidewall of the second insulating film 37. In addition, in the region where the number of via holes 40a is large, the thickness of the second anti-reflection film 41 formed on the second insulating film 37 is also reduced.

Referring to FIG. 3D, the second anti-reflection film 41 thinly formed on the surface of the second insulating film 37 is removed in a region where the number of via holes 41 is large per unit area. The second insulating film 37 is exposed to the portion where the second anti-reflection film 41 is removed.

The removal process of the second anti-reflection film 41 is carried out in an etching apparatus generating low density ions of about 1E10ion / cm ³ , maintaining a pressure of 50 to 70 mTorr, source power of 1800 to 2200 Watts and a vise of 1300 to 1600 Watts The process proceeds while supplying CHF ₃ , CF ₄ , O ₂ and Ar with power applied. At this time, the supply amount of CHF ₃ is 20 to 30 sccm, the supply amount of CF ₄ is 50 to 80 sccm, the supply amount of O2 is 10 to 15 sccm, the supply amount of Ar is 400 to 600 sccm.

Referring to FIG. 3E, a third insulating film 43 is selectively formed on the surface of the second insulating film 37 exposed while the second anti-reflection film 41 is removed.

The third insulating layer 43 is formed by a selective liquid phase deposition (LPD) method. In the selective LPD method, a substrate was immersed in a mixed aqueous solution of boric acid (H ₃ BO ₃ ) added to a supersaturated solution of Hydrofluosilicic Acid (H ₂ SiF ₆ ) at room temperature, and then SiOF (Fluorinate Silica Glass; FSG) was added only to silicon and oxide. How to grow. Therefore, the third insulating film 43 formed by the selective LPD method is made of SiOF, and is formed only on the surface of the second insulating film 37 from which the second anti-reflection film 41 has been removed.

By the third insulating film 43 formed by the selective LPD method, the difference in the thickness of the insulating film in the region where the second anti-reflection film 41 remains and the region where the second anti-reflection film 41 is removed can be reduced. Therefore, it is advantageous to set the process conditions by securing the process margin during the etching process for forming the trench, and it is possible to suppress the occurrence of etch damage in the etch stop layer 36. In addition, since the third insulating film 43 formed on the sidewall of the second insulating film 37 is etched instead of the second insulating film 37 during the trench etching process, the etching amount according to the trench etching process is determined by the thickness of the third insulating film 43. Can be used to improve the trench's etch profile.

Referring to FIG. 3F, the second anti-reflection film 41, the third insulating film 43, and the second insulating film 37 are etched by an etching process using the second photoresist pattern 42 as an etching mask, and the trench 40b is etched. To form. As a result, a dual damascene pattern 40 including the trench 40b and the via hole 40a is formed. Thereafter, the second photoresist pattern 42 and the second anti-reflection film 41 on the second insulating layer 37 are removed using the O ₂ plasma, and the second anti-reflection film material embedded in the via hole 40a is removed. The exposed metal diffusion barrier layer 34 is removed to expose the metal wire 33.

In the above, the etching process for forming the trench uses a plasma etching method.

Unlike the via hole etching process, the trench etching process has a large area to be etched. Therefore, in order to make the etching profile vertical, the etching time must be increased to increase the residence time of the radicals. do. However, according to the above conditions, the etch selectivity of the insulating film and the nitride film is lowered, so that the etch stop layer 36 may be over-etched. Therefore, as described below, the trench 40b is formed by a two-step etching method.

The trench etching process is carried out in etching equipment generating low density ions of about 1E10ion / cm ³ . In the first etching process, any one of C ₄ F ₈ and C ₅ F ₈ , O ₂ and C, while maintaining a pressure of 60 to 100 mTorr and applying a source power of 1800 to 2000 Watts and a bias power of 1500 to 1700 Watts The second insulating film 37 is etched at about 1500 to 2000 microseconds while Ar is supplied. At this time, the supply amount of C ₄ F ₈ or C ₅ F ₈ is 15 to 25 sccm, the supply amount of O ₂ is 15 to 25 sccm, the supply amount of Ar is 700 to 1000 sccm.

CH ₂ F and any one of C ₄ F ₈ and C ₅ F ₈ while maintaining a pressure of 30 to 50 mTorr in a secondary etching process and applying a source power of 1800 to 2000 Watts and a bias power of 1500 to 1700 Watts. ₂ , O ₂ and Ar are supplied while the etching is stopped in the etch stop layer 36. At this time, the supply amount of C ₄ F ₈ or C ₅ F ₈ is 15 to 25 sccm, the supply amount of CH ₂ F ₂ is 5 to 10 sccm, the supply amount of O ₂ is 10 to 15 sccm, the supply amount of Ar is 400 to 600 sccm.

In addition, in the etching process of removing the metal diffusion barrier 34 exposed through the via hole 40a, the pressure is maintained at 50 to 70 mTorr and the source power of 800 to 1000 Watts and the bias power of 200 to 400 Watts are applied. It is carried out while supplying CHF ₃ , O ₂ and Ar to minimize the etching damage of the first insulating film 35. At this time, the supply amount of CHF ₃ is 20 to 30 sccm, the supply amount of O ₂ is 20 to 35 sccm, and the supply amount of Ar is 400 to 600 sccm.

As described above, the present invention provides a profile of the dual damascene pattern by minimizing the occurrence of etching damage on the insulating layer on which the dual damascene pattern is formed while supplementing the insulating layer in the region removed from the anti-reflection layer to secure the margin of the etching process. In addition, the process of forming the metal wiring can be performed stably, thereby improving the reliability of the process and the electrical characteristics of the device.

Claims (7)

Forming a via hole in the interlayer insulating film above the lower metal wiring, and further depositing an insulating film on the exposed surface of the interlayer insulating film to compensate for etch damage caused by the subsequent trench etching process. Pattern formation method. The method of claim 1, The insulating film is a method of forming a dual damascene pattern of a semiconductor device, characterized in that formed of SiOF. The method according to claim 1 or 2 And the insulating film is formed by an LPD method and is selectively formed only on an exposed surface of the interlayer insulating film. Providing a semiconductor substrate having a metal wiring formed thereon and having a metal diffusion barrier, a first insulating film, an etch stop, a second insulating film, and a first antireflection film sequentially formed over the entire metal layer; Forming a via hole exposing the metal diffusion barrier layer; Removing the first anti-reflection film, and forming a second anti-reflection film on the second insulating film to fill the via hole with the second anti-reflection film; Partially removing the second anti-reflection film formed on the via hole; Forming a third insulating film on the exposed surfaces of the first and second insulating films, Forming a trench by removing the second insulating film in a predetermined region; Removing the second anti-reflection film formed in the via hole, and removing the metal diffusion prevention film so that the metal wiring is exposed. The method of claim 4, wherein The third insulating film is a method of forming a dual damascene pattern of the semiconductor device, characterized in that formed of SiOF. The method according to claim 4 or 5 And the third insulating film is formed by the LPD method and selectively formed only on the exposed surface of the interlayer insulating film. The method of claim 4, wherein The etching process of the second insulating film for forming the trench may include a first etching process of etching the second insulating film about 1500 to 2000 내지, and a second etching process of etching of the etching prevention film. Dual damascene pattern formation method of a semiconductor device.