KR100727259B1 - Method of formining line in semiconductor device - Google Patents
Method of formining line in semiconductor device Download PDFInfo
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- KR100727259B1 KR100727259B1 KR1020050134358A KR20050134358A KR100727259B1 KR 100727259 B1 KR100727259 B1 KR 100727259B1 KR 1020050134358 A KR1020050134358 A KR 1020050134358A KR 20050134358 A KR20050134358 A KR 20050134358A KR 100727259 B1 KR100727259 B1 KR 100727259B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 6
- 230000002265 prevention Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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Abstract
Description
도 1은 본 발명의 한 실시예에 따른 반도체 소자의 금속 배선을 도시한 단면도이다.1 is a cross-sectional view illustrating metal wiring of a semiconductor device according to an exemplary embodiment of the present invention.
도 2 및 도 3은 도 1의 반도체 소자의 금속 배선을 형성하는 방법을 설명하기 위한 단면도이다.2 and 3 are cross-sectional views for describing a method of forming metal wirings of the semiconductor device of FIG. 1.
본 발명은 반도체 장치의 금속 배선 형성 방법에 관한 것으로 특히, 반사 방지막을 이용한 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring forming method of a semiconductor device, and more particularly to a metal wiring forming method using an antireflection film.
금속 배선, 캐패시터, 트랜지스터 등을 포함하는 반도체 장치는 여러 번의 식각 공정을 거쳐 형성한다. 이러한 식각 공정은 패터닝된 감광막을 마스크로 하부막을 식각 기체 또는 식각액으로 식각한다.Semiconductor devices including metal wirings, capacitors, transistors, and the like are formed through several etching processes. In this etching process, the lower layer is etched with an etching gas or an etchant using the patterned photoresist as a mask.
이때 식각하는 하부막의 반사도가 클 때 감광막을 형성하기 전에 반사를 감소시키기 위한 반사 방지층을 형성한다.In this case, when the reflectivity of the underlying layer to be etched is large, an antireflection layer for reducing reflection is formed before forming the photosensitive layer.
반사 방지층(anti reflective coating, ARC)층은 노광 공정에서 하부 층으로 부터 반사에 의해 빛이 산란되어 발생하는 감광막(PR)의 스탠딩 웨이브(standing wave)를 감소시켜 정확한 CD(critical dimension) 조절을 목적으로 사용하고 있다. The anti-reflective layer (ARC) layer reduces the standing wave of the photoresist film (PR) generated by the light scattered by the reflection from the lower layer in the exposure process, so that accurate CD (critical dimension) control is achieved. I'm using it.
반사 방지층의 재료는 감광막과 굴절률이 비슷하면서도 광흡수율이 크며 감광막 용해제에 안정해야 하는 것 등이 요구되고 있다. 이러한 재료로는 무기 물질이 주로 사용되고 있다.The material of the anti-reflection layer is similar in refractive index to the photoresist, but has a high light absorption rate and needs to be stable to the photoresist solvent. Inorganic materials are mainly used as such materials.
그러나 무기 물질은 특성이 무르기 때문에 형성 후에 열처리하여 경화하는 공정을 필요로 한다.However, because the inorganic material is soft, it requires a step of curing by heat treatment after formation.
따라서 본 발명이 이루고자 하는 기술적 과제는 반사 방지층을 형성하는 공정을 간소화할 수 있는 반도체 장치의 금속 배선 형성 방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method for forming metal wirings in a semiconductor device, which can simplify the process of forming the anti-reflection layer.
상기한 기술적 과제를 이루기 위한 본 발명에 따른 반도체 장치의 금속 배선 형성 방법은 반도체 기판 위에 금속막을 형성하는 단계, 금속막 위에 SiCN:H로 이루어지는 반사 방지막을 형성하는 단계, 반사 방지막 위에 감광막 패턴을 형성하는 단계, 그리고 감광막 패턴을 마스크로 반사 방지막 및 금속막을 식각하여 금속 배선을 형성하는 단계, 그리고 감광막 패턴 및 반사 방지막을 제거하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of forming a metal wiring in a semiconductor device, the method including forming a metal film on a semiconductor substrate, forming an antireflection film made of SiCN: H on the metal film, and forming a photoresist pattern on the antireflection film. And etching the anti-reflection film and the metal film using the photoresist pattern as a mask to form metal wirings, and removing the photoresist pattern and the anti-reflection film.
반사 방지막은 PE-CVD법으로 형성할 수 있다.The antireflection film can be formed by PE-CVD.
반사 방지막은 400℃의 온도에서 1~10Torr의 압력으로 파워를 100~1,000W, TMS(Si(CH3)3H:trimethylsilane)를 10~1,000sccm, He를 10~1,000sccm, NH3을 10~1,000sccm 주입하여 형성할 수 있다.The anti-reflection film has a power of 100 to 1,000 W at a temperature of 400 ° C. at a pressure of 1 to 10 Torr, 10 to 1,000 sccm for TMS (Si (CH 3 ) 3 H: trimethylsilane), 10 to 1,000 sccm for He, and 10 to 1,000 for NH 3. It can be formed by sccm injection.
그러면, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 본 발명의 실시예에 대하여 첨부한 도면을 참고로 하여 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다.Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 명세서 전체를 통하여 유사한 부분에 대해서는 동일한 도면 부호를 붙였다. 층, 막, 영역, 판 등의 부분이 다른 부분 위에 있다고 할 때, 이는 다른 부분 바로 위에있는 경우뿐 아니라 그 중간에 또 다른 부분이 있는 경우도 포함한다. 반대로 어떤 부분이 다른 부분 바로 위에 있다고 할 때에는 중간에 다른 부분이 없는 것을 뜻한다.In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.
이제 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법에 대하여 도면을 참고로 하여 상세하게 설명한다.A method of forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 한 실시예에 따른 반도체 소자의 금속 배선을 도시한 단면도이다.1 is a cross-sectional view illustrating metal wiring of a semiconductor device according to an exemplary embodiment of the present invention.
도 1에 도시한 바와 같이, 기판(100) 위에는 제1 확산 방지층(102), 금속 배선(104), 제2 확산 방지층(106)이 형성되어 있다.As shown in FIG. 1, the first
기판(100)은 반도체 장치의 트랜지스터와 같은 하부 구조물(도시하지 않음) 또는 하부 배선(도시하지 않음)을 포함하며, 금속 배선(108)은 이들 하부 구조물 또는 하부 배선과 연결될 수 있다.The
제1 및 제2 확산 방지층은 티타늄/질화티타늄(Ti/TiN)으로 이루어지고, 금속 배선(104)은 알루미늄으로 이루어진다.The first and second diffusion barrier layers are made of titanium / titanium nitride (Ti / TiN), and the
이상 본 발명의 한 실시예에 따른 반도체 소자의 금속 배선을 제조하는 방법을 기 설명한 도 1과 첨부한 도 2 및 도3을 참조하여 설명한다.The method of manufacturing the metal wiring of the semiconductor device according to the exemplary embodiment of the present invention will be described with reference to FIG. 1 and FIG. 2 and FIG.
도 2 및 도3은 본 발명의 한 실시예에 따른 반도체 소자의 금속 배선을 제조하는 방법 중 중간 단계에서의 단면도이다.2 and 3 are cross-sectional views at an intermediate stage in the method of manufacturing the metal wiring of the semiconductor device according to one embodiment of the present invention.
도 2에 도시한 바와 같이, 반도체 기판(100) 위에 제1 확산 방지막(102a)과 알루미늄막(104a) 및 제2 확산 방지막(106a)을 형성한다. 그리고 제2 확산 방지막(106a) 위에 PE-CVD법으로 SiCN:H으로 이루어지는 반사 방지막(108a)을 형성한다. 반사 방지막(108a)은 400℃의 온도에서 1~10Torr의 압력으로 파워를 100~1,000W, TMS(Si(CH3)3H:trimethylsilane)를 10~1,000sccm, He를 10~1,000sccm, NH3을 10~1,000sccm 주입하여 형성한다.As shown in FIG. 2, a first
그리고 반사 방지막(106a) 위에 사진 공정으로 감광막 패턴(PR)을 형성한다. 감광막 패턴(PR)을 금속 배선이 형성되는 부분에만 남긴다.The photoresist pattern PR is formed on the
다음 도 3에 도시한 바와 같이, 감광막 패턴(PR)을 마스크로 반사 방지막(108a), 제2 확산 방지막(106a), 알루미늄막(104a) 및 제1 확산 방지막(102a)을 식각하여 제2 확산 방지층(106), 금속 배선(104), 제1 확산 방지층(102)을 형성한다.Next, as shown in FIG. 3, the
다음 도 1에 도시한 바와 같이, 감광막 패턴(PR)과 반사 방지막(108a)을 제거한다.Next, as shown in FIG. 1, the photoresist pattern PR and the
이상 설명한 본 발명에서와 같이 SiCN:H로 반사 방지막을 형성하면 열처리로 경화시키는 공정을 생략하므로 반도체 소자의 배선 공정을 간소화할 수 있다.When the anti-reflection film is formed of SiCN: H as described above, the step of curing by heat treatment is omitted, so that the wiring process of the semiconductor device can be simplified.
이상에서 본 발명의 바람직한 실시예에 대하여 상세하게 설명하였지만, 당해 기술 분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 수 있을 것이다. 따라서, 본 발명의 권리 범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자가 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also within the scope of the present invention.
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| KR1020050134358A KR100727259B1 (en) | 2005-12-29 | 2005-12-29 | Method of formining line in semiconductor device |
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| KR1020050134358A KR100727259B1 (en) | 2005-12-29 | 2005-12-29 | Method of formining line in semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105785639A (en) * | 2016-03-30 | 2016-07-20 | 友达光电股份有限公司 | Low-reflection metal structure, display panel and manufacturing method thereof |
| CN108121098A (en) * | 2017-12-19 | 2018-06-05 | 友达光电股份有限公司 | Metal structure and preparation method thereof and the display panel of application |
| CN118248572A (en) * | 2024-05-29 | 2024-06-25 | 浙江创芯集成电路有限公司 | Method for forming semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040021533A (en) * | 2002-09-04 | 2004-03-10 | 에이에스엠 저펜 가부시기가이샤 | Method of Forming a Film on a Semiconductor Substrate |
| KR20050007004A (en) * | 2003-07-10 | 2005-01-17 | 삼성전자주식회사 | Method for forming metal interconnection layer of semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040021533A (en) * | 2002-09-04 | 2004-03-10 | 에이에스엠 저펜 가부시기가이샤 | Method of Forming a Film on a Semiconductor Substrate |
| KR20050007004A (en) * | 2003-07-10 | 2005-01-17 | 삼성전자주식회사 | Method for forming metal interconnection layer of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105785639A (en) * | 2016-03-30 | 2016-07-20 | 友达光电股份有限公司 | Low-reflection metal structure, display panel and manufacturing method thereof |
| CN108121098A (en) * | 2017-12-19 | 2018-06-05 | 友达光电股份有限公司 | Metal structure and preparation method thereof and the display panel of application |
| WO2019119490A1 (en) * | 2017-12-19 | 2019-06-27 | 友达光电股份有限公司 | Metal structure, fabrication method therefor and display panel applied in same |
| JP2021505971A (en) * | 2017-12-19 | 2021-02-18 | 友達光電股▲ふん▼有限公司ＡＵ Ｏｐｔｒｏｎｉｃｓ Ｃｏｒｐｏｒａｔｉｏｎ | Metal structure, its creation method and display panel applying it |
| CN118248572A (en) * | 2024-05-29 | 2024-06-25 | 浙江创芯集成电路有限公司 | Method for forming semiconductor structure |
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