KR100299380B1 - Method of forming metal interconnection for semiconductor device - Google Patents
Method of forming metal interconnection for semiconductor device Download PDFInfo
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- KR100299380B1 KR100299380B1 KR1019980025767A KR19980025767A KR100299380B1 KR 100299380 B1 KR100299380 B1 KR 100299380B1 KR 1019980025767 A KR1019980025767 A KR 1019980025767A KR 19980025767 A KR19980025767 A KR 19980025767A KR 100299380 B1 KR100299380 B1 KR 100299380B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 42
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 3
- 239000006117 anti-reflective coating Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000460 chlorine Substances 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- ONIBWKKTOPOVIA-BYPYZUCNSA-N L-Proline Chemical compound OC(=O)[C@@H]1CCCN1 ONIBWKKTOPOVIA-BYPYZUCNSA-N 0.000 description 1
- ONIBWKKTOPOVIA-UHFFFAOYSA-N Proline Natural products OC(=O)C1CCCN1 ONIBWKKTOPOVIA-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 패시배이션막의 보이드 발생을 방지하여 외부로부터 디바이스를 효과적으로 보호할 수 있는 반도체 소자의 금속배선 형성방법을 제공한다.SUMMARY OF THE INVENTION The present invention provides a method for forming metal wirings in a semiconductor device that can prevent voids from occurring in the passivation film, thereby effectively protecting the device from the outside.
본 발명에 따른 반도체 소자의 금속배선은 배리어 금속막, 배선용 금속막, ARC막이 순차적으로 적층된 구조를 포함한다. ARC막 상에 배선용 금속막에 대한 식각 선택비가 우수한 마스크 패턴용 막을 형성한 다음, 마스크 패턴용 막 및 ARC 막을 제 1 식각공정으로 식각하여, 마스크 패턴을 형성함과 더불어 이후의 배선 프로파일과 동일한 프로파일을 가지는 ARC 막 패턴을 형성한다. 그리고 나서, 마스크 패턴을 식각 마스크로 하는 제 2 식각공정으로 배선용 금속막 및 배리어 금속막을 식각하여 배선을 형성하고, 기판 전면에 패시배이션막을 형성한다. 바람직하게, 배리어 금속막은 Ti/TiN막이고, 배선용 금속막은 알루미늄막이고, ARC막은 TiN막이고, 마스크 패턴용 물질막은 산화막 또는 질화막으로 형성한다. 또한, 제 1 식각공정은 플로린 계열의 개스를 이용하여 진행하고, 패시배이션막은 HDP 산화막으로 형성한다.The metal wiring of the semiconductor device according to the present invention includes a structure in which a barrier metal film, a wiring metal film, and an ARC film are sequentially stacked. After forming a mask pattern film having an excellent etching selectivity with respect to the wiring metal film on the ARC film, the mask pattern film and the ARC film are etched by the first etching process to form a mask pattern and the same profile as that of the subsequent wiring profile. An ARC film pattern is formed. Then, the wiring metal film and the barrier metal film are etched in a second etching process using the mask pattern as an etching mask to form wiring, and a passivation film is formed on the entire substrate. Preferably, the barrier metal film is a Ti / TiN film, the wiring metal film is an aluminum film, the ARC film is a TiN film, and the mask pattern material film is formed of an oxide film or a nitride film. In addition, the first etching process is performed using a florin-based gas, and the passivation film is formed of an HDP oxide film.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 패시배이션막의 보이드 발생을 방지할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring in a semiconductor device capable of preventing voids in a passivation film.
일반적으로, 금속 배선의 형성후 외부로부터의 파티클 또는 수분등의 침투를 방지하기 위하여, 기판 전면에 패시배이션 막을 형성한다. 이러한 패시배이션막으로서, PE(Plasma Enhanced) 산화막 및 PE 질화막의 적층막을 사용한다. 그러나, 반도체 디바이스의 고집적화에 의해 배선간격이 미세해짐에 따라, 상기한 PE 산화막 및 PE 질화막의 적층막으로 이루어진 패시배이션막의 갭필(gap filling) 능력이 저하되어, 배선 사이의 패시배이션막에 보이드(void)가 발생된다.In general, a passivation film is formed on the entire surface of the substrate in order to prevent penetration of particles or moisture from the outside after formation of the metal wiring. As such a passivation film, a laminated film of a PE (Plasma Enhanced) oxide film and a PE nitride film is used. However, as wiring intervals become finer due to higher integration of semiconductor devices, the gap filling ability of the passivation film made of the laminated film of the PE oxide film and the PE nitride film is lowered, so that the passivation film between the wirings is reduced. A void is generated.
이러한, 보이드를 방지하기 위하여, 패시배이션막으로서 HDP(High Density Plasma) 산화막이 제시되었다. 도 1은 HDP 산화막이 적용된 반도체 디바이스의 금속 배선을 나타낸 단면도이다.In order to prevent such voids, an HDP (High Density Plasma) oxide film has been proposed as a passivation film. 1 is a cross-sectional view showing a metal wiring of a semiconductor device to which an HDP oxide film is applied.
도 1을 참조하면, 반도체 기판(10) 상에 절연막(11)을 형성하고, 기판(10)의 소정부분이 노출되도록 절연막(11)을 식각하여 콘택홀(12)을 형성한다. 콘택홀(12) 표면 및 절연막(11) 상에 배리어 금속막으로서 Ti/TiN막(13)을 증착하고, 그 상부에 배선용 금속막으로서 알루미늄막(14)을 증착한다. 알루미늄막(14) 상에 그의 표면 반사를 방지하기 위하여 ARC(Anti-Reflective Coating)막으로서 TiN막(15)을 증착한다. 그런 다음, Cl 개스를 이용한 식각공정으로, TiN막(15), 알루미늄막(14), 및 Ti/TiN막(13)을 패터닝하여 금속배선을 형성하고, 기판 전면에 패시배이션막으로서 HDP 산화막(16)을 형성한다.Referring to FIG. 1, an insulating film 11 is formed on a semiconductor substrate 10, and a contact hole 12 is formed by etching the insulating film 11 to expose a predetermined portion of the substrate 10. A Ti / TiN film 13 is deposited as a barrier metal film on the contact hole 12 surface and the insulating film 11, and an aluminum film 14 is deposited as a wiring metal film thereon. A TiN film 15 is deposited as an ARC (Anti-Reflective Coating) film to prevent surface reflection thereof on the aluminum film 14. Then, in the etching process using Cl gas, the TiN film 15, the aluminum film 14, and the Ti / TiN film 13 are patterned to form metal wiring, and the HDP oxide film is used as a passivation film on the entire substrate. (16) is formed.
그러나, Ti막(15), 알루미늄막(14), 및 Ti/TiN막(13)의 패터닝시, 알루미늄막(14)은 클로린(Cl) 계열의 개스와 화학적인 반응에 의해 식각되는 반면, TiN막(15)은 클로린 개스와 물리적인 반응에 의해 식각된다. 이에 따라, 도 1에 도시된 바와 같이, 금속배선의 프로파일이 균일하지 않고 테이블 탑(table top) 형상을 이루게 되어, 금속배선의 양 측부의 HDP 산화막(16)에 보이드(V1, V2)가 발생한다. 이러한 보이드에 의해, 디바이스내로 수분등이 침투하여, 배선의 부식이 유발되어, 결국 디바이스의 특성이 저하된다. 한편, 이러한 보이드는 배선 간격이 좁아짐에 따라, 더욱더 심하게 발생한다.However, when the Ti film 15, the aluminum film 14, and the Ti / TiN film 13 are patterned, the aluminum film 14 is etched by a chemical reaction with a chlorine-based gas, while TiN The membrane 15 is etched by physical reaction with chlorine gas. Accordingly, as shown in FIG. 1, the profile of the metal wiring is not uniform and forms a table top shape, and voids V1 and V2 are generated in the HDP oxide films 16 on both sides of the metal wiring. do. Due to such voids, moisture or the like penetrates into the device, causing corrosion of the wiring, and eventually deteriorating the characteristics of the device. On the other hand, such voids are more severely generated as the wiring spacing becomes narrower.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 패시배이션막의 보이드 발생을 방지하여 외부로부터 디바이스를 효과적으로 보호할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of effectively protecting a device from the outside by preventing void generation of a passivation film.
도 1은 일반적인 반도체 소자의 금속배선 구조를 나타낸 단면도.1 is a cross-sectional view showing a metal wiring structure of a general semiconductor device.
도 2a 및 도 2d는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.2A and 2D are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device in accordance with an embodiment of the present invention.
도 3은 종래의 배선 프로파일 사진을 나타낸 도면.Figure 3 is a view showing a conventional wiring profile picture.
도 4는 본 발명의 배선 프로파일 사진을 나타낸 도면.4 is a view showing a wiring profile picture of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
20 : 반도체 기판 21 : 절연막20 semiconductor substrate 21 insulating film
22 : 콘택홀 23, 23a : Ti/TiN막22: contact hole 23, 23a: Ti / TiN film
24, 24a : 알루미늄막 25, 25a : TiN막24, 24a: aluminum film 25, 25a: TiN film
26 : 산화막 26a : 산화막 패턴26: oxide film 26a: oxide film pattern
27 : 포토레지스트막 패턴 28 : HDP 산화막27 photoresist film pattern 28 HDP oxide film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선은 배리어 금속막, 배선용 금속막, 및 ARC막이 순차적으로 적층된 구조를 포함한다. ARC막 상에 배선용 금속막에 대한 식각 선택비가 우수한 마스크 패턴용 막을 형성한 다음, 마스크 패턴용 막 및 ARC막을 제 1 식각공정으로 식각하여, 마스크 패턴을 형성함과 더불어 이후의 배선 프로파일과 동일한 프로파일을 가지는 ARC막 패턴을 형성한다. 그리고 나서, 마스크 패턴용막을 식각 마스크로 하는 제 2 식각공정으로 배선용 금속막 및 배리어 금속막을 식각하여 배선을 형성하고, 기판 전면에 패시배이션막을 형성한다.The metal wiring of the semiconductor device according to the present invention for achieving the above object includes a structure in which a barrier metal film, a wiring metal film, and an ARC film are sequentially stacked. After forming a mask pattern film having an excellent etching selectivity with respect to the wiring metal film on the ARC film, the mask pattern film and the ARC film are etched by the first etching process to form a mask pattern and the same profile as the subsequent wiring profile. An ARC film pattern is formed. Then, the wiring metal film and the barrier metal film are etched in a second etching process using the mask pattern film as an etching mask to form wiring, and a passivation film is formed on the entire substrate.
본 실시예에서, 배리어 금속막은 Ti/TiN막이고, 배선용 금속막은 알루미늄막이고, ARC막은 TiN막이고, 마스크 패턴용 물질막은 산화막 또는 질화막으로 형성한다. 또한, 제 1 식각공정은 프로린 계열의 개스를 이용하여 진행하고, 패시배이션막은 HDP 산화막으로 형성한다.In this embodiment, the barrier metal film is a Ti / TiN film, the wiring metal film is an aluminum film, the ARC film is a TiN film, and the mask pattern material film is formed of an oxide film or a nitride film. In addition, the first etching process is performed using a proline-based gas, and the passivation film is formed of an HDP oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 및 도 2d는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.2A and 2D are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(20) 상에 절연막(21)을 형성하고, 기판(20)의 소정부분이 노출되도록 절연막(21)을 식각하여, 콘택홀(22)을 형성한다. 콘택홀(22) 표면 및 절연막(21) 상에 배리어 금속막으로서 Ti/TiN막(23)을 증착하고, 그 상부에 배선용 금속막으로서 알루미늄막(24)을 증착한다. 이때, 알루미늄막은 6,000 내지 9,000Å의 두께로 형성한다. 알루미늄막(24) 상에 그의 표면 반사를 방지하기 위하여 ARC막으로서 TiN막(25)을 형성하고, TiN막(25) 상에 알루미늄막 (24)에 대한 우수한 식각 선택비를 가지는 마스크 패턴용 물질막, 바람직하게 산화막(26)을 증착한다. 이때, 산화막(26)은 LPCVD(Low Pressure Chemical Vapor Deposition) 또는 PECVD(Plasma Enhnaced CVD)를 이용하여 300 내지 3,000Å의 두께로 증착한다. 이때, 산화막(26) 대신에 질화막을 사용할 수 있다. 그런 다음, 산화막(26) 상부에 포토리소그라피로 포토레지스트막 패턴(27)을 형성한다. 이때, 포토레지스트막 패턴(27)의 두께는 종래의 1㎛ 이상의 두께보다 더 얇은 두께로 형성할 수 있다.Referring to FIG. 2A, the insulating film 21 is formed on the semiconductor substrate 20, and the insulating film 21 is etched to expose a predetermined portion of the substrate 20, thereby forming the contact hole 22. A Ti / TiN film 23 is deposited as a barrier metal film on the contact hole 22 surface and the insulating film 21, and an aluminum film 24 is deposited as a wiring metal film thereon. At this time, the aluminum film is formed to a thickness of 6,000 to 9,000 kPa. A mask pattern material which forms a TiN film 25 as an ARC film to prevent surface reflection thereof on the aluminum film 24 and has an excellent etching selectivity with respect to the aluminum film 24 on the TiN film 25. A film, preferably an oxide film 26, is deposited. At this time, the oxide layer 26 is deposited to a thickness of 300 to 3,000 Å using LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhnaced CVD). In this case, a nitride film may be used instead of the oxide film 26. Then, the photoresist film pattern 27 is formed by photolithography on the oxide film 26. In this case, the thickness of the photoresist film pattern 27 may be formed to a thickness thinner than that of the conventional 1 μm or more.
도 2b를 참조하면, 포토레지스트막 패턴(27)을 식각 마스크로하는 제 1 식각공정으로 산화막(26) 및 TiN막(25)을 식각하여, 이후 배선형성을 위한 마스크로 작용할 산화막 패턴(26a)을 형성함과 더불어, 테이블 탑이 없이 이후 형성될 배선의 프로파일과 동일한 프로파일을 가지는 TiN막 패턴(25a)을 형성한다. 이때, 제 1 식각공정은 플로린(F) 계열의 개스를 이용하여 TCP, ICP, RIE, 및 DRM 등의 챔버를 이용하여 진행한다. 그런 다음, 공지된 방법으로 포토레지스트막 패턴(27)을 제거한다.Referring to FIG. 2B, the oxide layer 26 and the TiN layer 25 are etched by the first etching process using the photoresist layer pattern 27 as an etching mask, and then the oxide layer pattern 26a to act as a mask for forming wirings. In addition, the TiN film pattern 25a having the same profile as the profile of the wiring to be subsequently formed without the table top is formed. In this case, the first etching process is performed using a chamber of TCP, ICP, RIE, and DRM using a florin (F) -based gas. Then, the photoresist film pattern 27 is removed by a known method.
도 2c를 참조하면, 산화막 패턴(26a)을 식각 마스크로 하는 제 2 식각공정으로 알루미늄막(24) 및 Ti/TiN막(23)을 식각하여 배선을 형성한다. 제 2 식각공정은 TCP 또는 RIE 등의 챔버를 이용하여 진행하다. TCP를 사용하는 경우, 먼저 200 내지 600W의 소오스 전력과, 100 내지 400W의 바이어스 전력에서, 20 내지 80 SCCM의 BCl3개스와 40 내지 120 SCCM의 Cl2개스로 메인식각(main etch)을 진행하여 알루미뉴막(24)을 제거한다. 그런 다음, 250 내지 300W의 소오스 전력과, 80 내지 250W의 바이어스 전력에서, 메인식각과 마찬가지로 BCl3및 Cl2개스로 오버식각(over etch)을 진행하여 Ti/TiN막(23)을 제거한다. 오버식각시, 개스의 유량은 메인식각과 유사한 범위로 설정하여 진행한다. 또한, RIE를 사용하는 경우, 메인식각 및 오버식각은 200 내지 600W의 전력과 TCP를 사용하는 경우와 동일 개스 및 유량으로 진행한다. 제 2 식각공정에서, 알루미늄막(24)에 대한 산화막 패턴(26a)의 식각 선택비는 약 5 : 1 정도이기 때문에, 산화막 패턴(26a)을 식각 마스크로 사용하는 것이 가능하다. 이때, 산화막 패턴(26a)이 소정 부분 손실된다. 그리고 나서, 산화막 패턴(26a)을 제거한다.Referring to FIG. 2C, wirings are formed by etching the aluminum film 24 and the Ti / TiN film 23 by a second etching process using the oxide film pattern 26a as an etching mask. The second etching process is performed using a chamber such as TCP or RIE. In the case of using TCP, the main etch is first performed with a source power of 200 to 600 W and a bias power of 100 to 400 W, using 3 BCl of 20 to 80 SCCM and Cl 2 gas of 40 to 120 SCCM. The aluminium film 24 is removed. Then, at a source power of 250 to 300 W and a bias power of 80 to 250 W, the Ti / TiN film 23 is removed by overetching with BCl 3 and Cl 2 gas as in the main etching. At the time of over etching, the flow rate of the gas is set in a range similar to the main etching. In the case of using the RIE, the main etching and the over etching are performed at the same gas and flow rate as in the case of using a power of 200 to 600 W and TCP. In the second etching process, since the etching selectivity ratio of the oxide film pattern 26a to the aluminum film 24 is about 5: 1, it is possible to use the oxide film pattern 26a as an etching mask. At this time, the oxide film pattern 26a is partially lost. Then, the oxide film pattern 26a is removed.
도 2d를 참조하면, 도 2c의 구조상에 패시배이션막으로서 HDP 산화막(28)을 형성한다. 이때, 도 2d에 도시된 바와 같이, 배선의 균일한 프로파일에 의해 배선 양 측의 HDP 산화막(28)에 보이드가 발생되지 않는다.Referring to FIG. 2D, the HDP oxide film 28 is formed as a passivation film on the structure of FIG. 2C. At this time, as shown in FIG. 2D, no void is generated in the HDP oxide film 28 on both sides of the wiring due to the uniform profile of the wiring.
한편, 도 3 및 도 4는 종래 및 본 발명의 배선 프로파일을 각각 나타낸 도면으로서, 도 4에 도시된 바와 같이, 본 발명에서는 도 3에 도시된 바와 같은 종래의 탑형상이 나타나지 않는 균일한 배선 프로파일을 얻을 수 있다.On the other hand, Figures 3 and 4 is a view showing the wiring profile of the conventional and the present invention, respectively, as shown in Figure 4, in the present invention uniform wiring profile does not appear in the conventional tower shape as shown in Figure 3 Can be obtained.
상기한 본 발명에 의하면, 배선 형성을 위한 패터닝 공정이 2번의 식각공정으로 진행되기 때문에, 균일한 배선 프로파일을 얻을 수 있다. 즉, 별도의 산화막 마스크 패턴을 이용하여 TiN막을 배선의 프로파일 형태로 먼저 패터닝한 다음, 알루미늄막과 Ti/TiN막을 패터닝하기 때문에, TiN막의 테이블 탑과 같은 형상이 나타나지 않는다. 이와 같이, 불균일한 배선 프로파일로 인한 패시배이션막의 보이드 발생이 방지되어, 외부로부터 반도체 소자가 효과적으로 보호됨으로써, 결국 반도체 소자의 특성이 향상된다.According to the present invention described above, since the patterning process for forming the wiring proceeds to two etching processes, a uniform wiring profile can be obtained. That is, since the TiN film is first patterned in the form of a wiring profile using a separate oxide film mask pattern, and then the aluminum film and the Ti / TiN film are patterned, the shape of the table top of the TiN film does not appear. In this way, the void generation of the passivation film due to the nonuniform wiring profile is prevented, and the semiconductor element is effectively protected from the outside, thereby improving the characteristics of the semiconductor element.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (12)
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| JPH0729908A (en) * | 1993-07-15 | 1995-01-31 | Nec Corp | Formation of copper fine wiring |
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| JPH0729908A (en) * | 1993-07-15 | 1995-01-31 | Nec Corp | Formation of copper fine wiring |
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