KR100421280B1 - Method for forming a metal line of semiconductor device - Google Patents
Method for forming a metal line of semiconductor device Download PDFInfo
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- KR100421280B1 KR100421280B1 KR10-2001-0076192A KR20010076192A KR100421280B1 KR 100421280 B1 KR100421280 B1 KR 100421280B1 KR 20010076192 A KR20010076192 A KR 20010076192A KR 100421280 B1 KR100421280 B1 KR 100421280B1
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- forming
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- metal wiring
- interlayer oxide
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 68
- 239000011229 interlayer Substances 0.000 claims description 26
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 21
- 239000007789 gas Substances 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 44
- 229910052721 tungsten Inorganic materials 0.000 abstract description 44
- 239000010937 tungsten Substances 0.000 abstract description 44
- 230000010354 integration Effects 0.000 abstract description 5
- 230000002708 enhancing effect Effects 0.000 abstract 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 25
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 다층 금속 배선 형성 방법에 관한 것으로, 특히“T”자 구조의 콘택홀을 형성한 후 상기 콘택홀을 매립하는“T”자 구조의 텅스텐(W) 플러그(Plug)를 형성하므로, 종래의 텅스텐 플러그 상부 부위 면적보다“T”자 구조의 텅스텐 플러그가 넓게 형성되어 금속 배선과의 접촉면적이 증가되어 소자의 집적화로 축소된 접촉 면적을 보충하고 또한, “T”자 구조의 텅스텐 플러그 종래의 텅스텐 플러그보다 단면적이 크므로 텅스텐 플러그 자체의 전기적인 저항이 저하되어 금속 배선과 텅스텐 플러그간의 전기적인 접촉이 강화되므로 소자의 안정성, 수율 및 신뢰성을 향상시키는 특징이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer metal wiring of a semiconductor device. In particular, a “T” shaped tungsten (W) plug is formed to fill a contact hole after forming a “T” shaped contact hole. Therefore, the “T” shaped tungsten plug is formed wider than the area of the upper portion of the conventional tungsten plug, and the contact area with the metal wiring is increased to compensate for the reduced contact area due to the integration of the device. Tungsten Plug Since the cross-sectional area is larger than that of the conventional tungsten plug, the electrical resistance of the tungsten plug itself is reduced, thereby enhancing the electrical contact between the metal wire and the tungsten plug, thereby improving stability, yield and reliability of the device.
Description
본 발명은 반도체 소자의 다층 금속 배선 형성 방법에 관한 것으로, 특히 “T”자 구조의 콘택홀을 형성한 후 상기 콘택홀을 매립하는“T”자 구조의 텅스텐(W) 플러그(Plug)를 형성하여 소자의 안정성, 수율 및 신뢰성을 향상시키는 반도체 소자의 다층 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer metal wiring of a semiconductor device. In particular, a “T” shaped tungsten (W) plug for filling a contact hole after forming a “T” shaped contact hole is formed. The present invention relates to a method for forming a multilayer metal wiring of a semiconductor device, thereby improving the stability, yield and reliability of the device.
도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자의 다층 금속 배선 형성 방법을 도시한 단면도이고, 도 2는 종래 기술에 따른 금속 배선의 텅스텐 플러그 오버랩 형상을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a multilayer metal wiring of a semiconductor device according to the prior art, and FIG. 2 is a cross-sectional view illustrating a tungsten plug overlap shape of the metal wire according to the prior art.
종래의 반도체 소자의 다층 금속 배선 형성 방법은 도 1a를 참조하면, 제 1 금속 배선(13)을 포함한 하부구조물(11) 상에 층간 산화막(15)을 형성한다.Referring to FIG. 1A, a method of forming a multilayer metal wiring of a semiconductor device according to the related art forms an interlayer oxide film 15 on a lower structure 11 including a first metal wiring 13.
그리고, 비아 콘택 마스크를 사용한 사진 식각 공정에 의해 상기 층간 산화막(15)을 식각하여 비아홀(17)을 형성한다.The interlayer oxide layer 15 is etched by a photolithography process using a via contact mask to form a via hole 17.
도 1b를 참조하면, 상기 비아홀(17)을 포함한 전면에 제 1 Ti/TiN층(19)과 텅스텐층(21)을 순차적으로 형성한다.Referring to FIG. 1B, the first Ti / TiN layer 19 and the tungsten layer 21 are sequentially formed on the entire surface including the via hole 17.
도 1c를 참조하면, 상기 층간 산화막(15)을 식각 방지막으로 상기 텅스텐층(21)과 제 1 Ti/TiN층(19)을 평탄화 식각 하여 텅스텐 플러그(23)를 형성한다.Referring to FIG. 1C, the tungsten layer 23 and the first Ti / TiN layer 19 may be planarized by using the interlayer oxide layer 15 as an etch stop layer to form a tungsten plug 23.
여기서, 상기 평탄화 식각 공정은 플라즈마를 사용한 전면 식각을 사용하여 실시하거나 화학적 기계 연마 방법을 사용하여 실시한다.In this case, the planarization etching process may be performed using full surface etching using plasma or using a chemical mechanical polishing method.
도 1d를 참조하면, 상기 텅스텐 플러그(23)를 포함한 층간 산화막(15) 상에 제 2 Ti/TiN층(25), 알루미늄(Al)층(27), 제 3 Ti/TiN층(29) 및 감광막을 순차적으로 형성한다.Referring to FIG. 1D, the second Ti / TiN layer 25, the aluminum (Al) layer 27, the third Ti / TiN layer 29, and the interlayer oxide film 15 including the tungsten plug 23 are formed. The photosensitive film is formed sequentially.
그리고, 상기 감광막을 제 2 금속 배선이 형성될 부위에만 남도록 노광 및 현상하여 감광막 패턴(31)을 형성한다.The photoresist film is exposed and developed to remain only at the site where the second metal wiring is to be formed, thereby forming the photoresist pattern 31.
여기서, 상기 감광막의 노광 및 현상 공정 시 미스 얼라인(Misalign), 선 끝 축소 현상 및 틀어짐 현상(A)이 발생된다.Here, in the exposure and development process of the photosensitive film, misalignment, line shrinkage phenomenon, and distortion phenomenon A occur.
도 1e를 참조하면, 상기 감광막 패턴(31)을 마스크로 상기 제 3 Ti/TiN층(29), 알루미늄층(27) 및 제 2 Ti/TiN층(25)을 식각하여 Ti/TiN/Al/Ti/TiN 적층 구조의 금속 배선을 형성한 다음, 상기 감광막 패턴(31)을 제거한다.Referring to FIG. 1E, the third Ti / TiN layer 29, the aluminum layer 27, and the second Ti / TiN layer 25 are etched using the photoresist pattern 31 as a mask. After forming a metal wiring having a Ti / TiN laminated structure, the photosensitive film pattern 31 is removed.
여기서, 상기 감광막 패턴(31)의 미스 얼라인, 선 끝 축소 현상 및 틀어짐 현상의 발생과 소자의 집적화로 도 2에서와 같이, 상기 금속 배선이“B”의 지름을 갖는 텅스텐 플러그(23) 일부를 덮는 형태로 형성된다.Here, a portion of the tungsten plug 23 having a diameter of “B” is formed as shown in FIG. 2 due to occurrence of misalignment, line end shrinkage and distortion of the photosensitive film pattern 31 and integration of devices. It is formed in the form of covering.
그러나, 종래의 반도체 소자의 다층 금속 배선 형성 방법은 다음과 같은 이유에 의해 금속 배선과 텅스텐 플러그 사이의 전기적인 접촉이 취약해지는 문제점이 있었다.However, the conventional method of forming a multilayer metal wiring of a semiconductor device has a problem in that electrical contact between the metal wiring and the tungsten plug becomes weak due to the following reason.
첫째, 소자의 집적도가 높아질수록 금속 배선과 텅스텐 플러그 사이의 오버랩 마진(Overlap margin) 확보가 어렵다.First, as the degree of integration of devices increases, it is difficult to secure an overlap margin between the metal wire and the tungsten plug.
둘째, 상기 금속 배선 형성 공정 시 마스킹 역할을 하는 감광막 패턴의 미스얼라인, 선 끝 축소 현상 및 틀어짐 현상이 발생되기 때문에 상기 금속 배선과 텅스텐 플러그 사이의 접촉 면적이 작아지고 불안정하다.Second, since the misalignment, line end shrinkage, and distortion of the photoresist pattern, which serves as a masking role, may occur during the metal wiring forming process, the contact area between the metal wiring and the tungsten plug may be small and unstable.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로“T”자 구조의 콘택홀을 형성한 후 상기 콘택홀을 매립하는“T”자 구조의 텅스텐 플러그를 형성하여 금속 배선과 텅스텐 플러그간의 전기적인 접촉이 강화되는 반도체 소자의 다층 금속 배선 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and after forming a "T" shaped contact hole, forming a "T" shaped tungsten plug to fill the contact hole, thereby forming an electrical connection between the metal wiring and the tungsten plug. It is an object of the present invention to provide a method for forming a multilayer metal wiring of a semiconductor device in which contact is enhanced.
도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자의 다층 금속 배선 형성 방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method for forming a multilayer metal wiring of a semiconductor device according to the prior art.
도 2는 종래 기술에 따른 금속 배선의 텅스텐 플러그 오버랩 형상을 도시한 단면도.2 is a cross-sectional view showing a tungsten plug overlap shape of a metal wiring according to the prior art;
도 3a 내지 도 3i는 본 발명의 실시 예에 따른 반도체 소자의 다층 금속 배선 형성 방법을 도시한 단면도.3A to 3I are cross-sectional views illustrating a method of forming a multilayer metal wire in a semiconductor device according to an embodiment of the present invention.
도 4는 본 발명의 실시 예에 따른 금속 배선의 텅스텐 플러그 오버랩 형상을 도시한 단면도.4 is a cross-sectional view illustrating a tungsten plug overlap shape of a metal wire according to an exemplary embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11, 51 : 하부 구조물 13, 53 : 제 1 금속 배선11, 51: lower structure 13, 53: first metal wiring
15, 55 : 층간 산화막 17, 63 : 비아홀15, 55: interlayer oxide film 17, 63: via hole
19, 67 : 제 1 Ti/TiN층 21, 69 : 텅스텐층19, 67: 1st Ti / TiN layer 21, 69: tungsten layer
23, 71 : 텅스텐 플러그 25, 73 : 제 2 Ti/TiN층23, 71: tungsten plug 25, 73: second Ti / TiN layer
27, 75 : 알루미늄층 29, 77 : 제 3 Ti/TiN층27, 75: aluminum layer 29, 77: third Ti / TiN layer
31, 45 : 감광막 패턴 57 : 질화막31 and 45: photosensitive film pattern 57: nitride film
59 : 제 1 감광막 패턴 61 : 제 1 트렌치59: first photosensitive film pattern 61: first trench
65 : 제 2 트렌치 79: 제 2 감광막 패턴65: second trench 79: second photosensitive film pattern
본 발명의 반도체 소자의 다층 금속 배선 형성 방법은 기판 상에“T”자 구조의 플러그를 갖는 층간 절연막을 형성하는 단계, 상기 플러그를 포함한 전면에 도전층을 형성하는 단계 및 상기 도전층을 금속 배선용 마스크로 식각하여 상기 플러그와 전기적으로 연결된 금속 배선을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a multilayer metal wiring of a semiconductor device of the present invention comprises the steps of forming an interlayer insulating film having a plug having a "T" structure on the substrate, forming a conductive layer on the entire surface including the plug, and the conductive layer for metal wiring And etching a mask to form a metal wire electrically connected to the plug.
본 발명의 원리는“T”자 구조의 콘택홀을 형성한 후 상기 콘택홀을 매립하는“T”자 구조의 텅스텐 플러그를 형성하므로, 종래의 텅스텐 플러그 상부 부위 면적보다“T”자 구조의 텅스텐 플러그가 넓게 형성되어 금속 배선과의 접촉면적이 증가되므로 소자의 집적화로 축소된 접촉 면적을 보충할 수 있고 또한,“T”자 구조의 텅스텐 플러그 종래의 텅스텐 플러그보다 단면적이 크므로 텅스텐 플러그 자체의 전기적인 저항이 저하되어 금속 배선과 텅스텐 플러그간의 전기적인 접촉을 강화시키기 위한 것이다.The principle of the present invention is to form a "T" shaped contact hole and then form a "T" shaped tungsten plug which fills the contact hole. Since the plug is formed wider, the contact area with the metal wiring is increased, so that the contact area reduced by the integration of the element can be compensated. Also, since the tungsten plug having the “T” structure has a larger cross-sectional area than the conventional tungsten plug, The electrical resistance is lowered to strengthen the electrical contact between the metal wiring and the tungsten plug.
상기와 같은 본 발명에 따른 반도체 소자의 다층 금속 배선 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, a preferred embodiment of the method for forming a multi-layer metal wiring of the semiconductor device according to the present invention as described above in detail as follows.
도 3a 내지 도 3i는 본 발명의 실시 예에 따른 반도체 소자의 다층 금속 배선 형성 방법을 도시한 단면도이고, 도 4는 본 발명의 실시 예에 따른 금속 배선의 텅스텐 플러그 오버랩 형상을 도시한 단면도이다.3A to 3I are cross-sectional views illustrating a method of forming a multilayer metal wiring of a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view illustrating a tungsten plug overlap shape of a metal wiring according to an embodiment of the present invention.
도 3a를 참조하면, 제 1 금속 배선(53)을 포함한 하부구조물(51) 상에 층간 산화막(55), 질화막(57) 및 제 1 감광막을 순차적으로 형성한다.Referring to FIG. 3A, an interlayer oxide film 55, a nitride film 57, and a first photosensitive film are sequentially formed on a lower structure 51 including the first metal wiring 53.
이때, 상기 층간 산화막(55)을 상기 질화막(57) 두께의 2 ∼ 4배의 두께로 형성하고, 상기 질화막(57)은 하드 마스크(Hard mask)의 역할을 한다.In this case, the interlayer oxide layer 55 is formed to have a thickness of 2 to 4 times the thickness of the nitride layer 57, and the nitride layer 57 serves as a hard mask.
그리고, 상기 제 1 감광막을 비아 콘택이 형성될 부위에만 제거되도록 노광 및 현상하여 제 1 감광막 패턴(59)을 형성한다.The first photoresist layer is exposed and developed to be removed only at a portion where a via contact is to be formed, thereby forming a first photoresist layer pattern 59.
이때, 상기 제 1 감광막을 후속 공정인 상기 질화막(57)의 패터닝 공정 시 식각 마스크로 사용될 만큼 얇게 형성한다.In this case, the first photoresist layer is formed to be thin enough to be used as an etching mask in the subsequent patterning process of the nitride layer 57.
그리고, 상기 제 1 감광막의 두께가 얇기 때문에 미세 패턴 공정이 가능하다.In addition, since the thickness of the first photosensitive film is thin, a fine pattern process is possible.
도 3b를 참조하면, 상기 제 1 감광막 패턴(59)을 마스크로 CxFy+ O2기체를 주성분으로 하여 활성화시킨 플라즈마(Plasma)를 사용한 식각 공정에 의해 상기 질화막(57)을 식각한 후, 상기 제 1 감광막 패턴(59)을 제거한다.Referring to FIG. 3B, the nitride layer 57 is etched by an etching process using a plasma activated by using the first photoresist layer pattern 59 as a mask and a C x F y + O 2 gas as a main component. The first photosensitive film pattern 59 is removed.
여기서, 상기 CxFy기체로 CF4, C2F6C4F8, C5F8중의 하나의 기체를 사용하거나 그 기체들을 조합하여 사용한다.Here, one gas of CF 4 , C 2 F 6 C 4 F 8 , C 5 F 8 , or a combination of the gases is used as the C x F y gas.
또한, 상기 CxFy기체 또는 그 기체들이 조합된 기체에 CHF3또는 Ar을 첨가할 수도 있다.In addition, CHF 3 or Ar may be added to the C x F y gas or a gas combined therewith.
도 3c를 참조하면, 상기 질화막(57)을 마스크로 상기 층간 산화막(55)을 식각하여 제 1 트렌치(61)를 형성한다.Referring to FIG. 3C, the interlayer oxide layer 55 is etched using the nitride layer 57 as a mask to form a first trench 61.
여기서, 상기 층간 산화막(55)의 초기 두께의 1/3 ∼ 1/5이 잔재하도록 상기 층간 산화막(55)을 식각한다.Here, the interlayer oxide film 55 is etched so that 1/3 to 1/5 of the initial thickness of the interlayer oxide film 55 remains.
그리고, 상기 층간 산화막(55)의 식각 공정은 상기 층간 산화막(55)의 식각 속도가 상기 질화막(57)의 식각 속도에 비해 10 ∼ 20 배가 되도록 O2첨가량을 줄이면서 C4F8또는 C5F8기체를 활성화시킨 플라즈마를 사용하여 실시한다.Then, the etching process of the interlayer oxide film 55, reducing the O 2 amount so that the ship 10 to 20 compared to the etching rate of the etching rate of the interlayer oxide film 55, the nitride film (57) C 4 F 8 or C 5 It is carried out using a plasma activated with F 8 gas.
도 3d를 참조하면, H3PO4용액을 사용한 습식 식각 공정으로 상기 질화막(57)의 상부 부위를 등방성 식각한다.Referring to FIG. 3D, an upper portion of the nitride layer 57 is isotropically etched by a wet etching process using an H 3 PO 4 solution.
이때, 상기 질화막(57)의 등방성 식각 공정으로 상기 제 1 트렌치(61) 양측의 층간 산화막(55)을 노출시키며 전면에 상기 질화막(57)이 잔재한다.In this case, the interlayer oxide film 55 on both sides of the first trench 61 is exposed by the isotropic etching process of the nitride film 57, and the nitride film 57 remains on the entire surface.
여기서, 상기 H3PO4용액을 사용한 습식 식각 공정 시 상기 층간 산화막(55)보다 상기 질화막(57)의 식각 속도가 50배 이상 크기 때문에 상기 층간 산화막(55)은 식각 되지 않는다.Here, in the wet etching process using the H 3 PO 4 solution, since the etch rate of the nitride layer 57 is 50 times or more than that of the interlayer oxide layer 55, the interlayer oxide layer 55 is not etched.
도 3e를 참조하면, 상기 질화막(57)을 마스크로 O2첨가량을 줄이면서 C4F8또는 C5F8기체를 활성화시킨 플라즈마를 사용한 식각 공정에 의해 상기 층간 산화막(55)을 식각하여 비아홀(63)과 제 2 트렌치(65)를 형성한다.Referring to FIG. 3E, the interlayer oxide layer 55 is etched by an etching process using a plasma in which a C 4 F 8 or C 5 F 8 gas is activated while reducing the amount of O 2 added using the nitride layer 57 as a mask. 63 and the second trench 65 are formed.
이때, 상기 층간 산화막(55)의 식각 공정 시 상기 질화막(57)은 제거되고, 상기 제 2 트렌치(65)의 형성으로 상기 비아홀(63)이“T”자 구조를 갖는다.In this case, the nitride layer 57 is removed during the etching process of the interlayer oxide layer 55, and the via hole 63 has a “T” shape by forming the second trench 65.
도 3f를 참조하면, 상기 비아홀(63)을 포함한 전면에 제 1 Ti/TiN층(67)과 텅스텐층(69)을 순차적으로 형성한다.Referring to FIG. 3F, the first Ti / TiN layer 67 and the tungsten layer 69 are sequentially formed on the entire surface including the via hole 63.
이때, 상기 텅스텐층(69)을 화학적 기상 증착 방법에 의해 형성하고, 그 증착 방식의 특성으로 상기 텅스텐층(69)의 상부가 평탄화 된다.In this case, the tungsten layer 69 is formed by a chemical vapor deposition method, and the upper portion of the tungsten layer 69 is planarized by the characteristics of the deposition method.
그리고, 상기 제 1 Ti/TiN층(67)의 Ti는 접착제의 역할을 하고 TiN는 확산 방지막의 역할을 한다.In addition, Ti of the first Ti / TiN layer 67 serves as an adhesive and TiN serves as a diffusion barrier.
도 3g를 참조하면, 상기 층간 산화막(55)을 식각 방지막으로 상기 텅스텐층(69)과 제 1 Ti/TiN층(67)을 평탄화 식각 하여“T”자 구조의 텅스텐 플러그(71)를 형성한다.Referring to FIG. 3G, the tungsten layer 69 and the first Ti / TiN layer 67 may be planarized by using the interlayer oxide layer 55 as an etch stop layer to form a “T” shaped tungsten plug 71. .
이때, 상기 평탄화 식각 공정은 플라즈마를 사용한 전면 식각을 사용하여 실시하거나 화학적 기계 연마 방법을 사용하여 실시한다.In this case, the planarization etching process may be performed by using front surface etching using plasma or using a chemical mechanical polishing method.
도 3h를 참조하면, 상기 텅스텐 플러그(71)를 포함한 층간 산화막(55) 상에 제 2 Ti/TiN층(73), 알루미늄층(75), 제 3 Ti/TiN층(77) 및 제 2 감광막을 순차적으로 형성한다.Referring to FIG. 3H, the second Ti / TiN layer 73, the aluminum layer 75, the third Ti / TiN layer 77, and the second photosensitive film are formed on the interlayer oxide film 55 including the tungsten plug 71. To form sequentially.
이때, 상기 제 2, 제 3 Ti/TiN층(73,77)의 Ti는 접착제의 역할을 하고, 상기 제 2 Ti/TiN층(73)의 TiN는 확산 방지막의 역할을 하며, 상기 제 3 Ti/TiN층(77)의 TiN는 반사 방지막의 역할을 한다.In this case, Ti of the second and third Ti / TiN layers 73 and 77 serves as an adhesive, TiN of the second Ti / TiN layer 73 serves as a diffusion barrier, and the third Ti TiN in the / TiN layer 77 serves as an antireflection film.
그리고, 상기 제 2 감광막을 제 2 금속 배선이 형성될 부위에만 남도록 노광 및 현상하여 제 2 감광막 패턴(79)을 형성한다.The second photoresist film is exposed and developed to remain only at a portion where the second metal wiring is to be formed to form a second photoresist pattern 79.
이때, 상기 제 2 감광막의 노광 및 현상 공정 시 미스 얼라인, 선 끝 축소 현상 및 틀어짐 현상(A)이 발생된다.At this time, a misalignment, a line end shrinkage phenomenon, and a distortion phenomenon (A) occur during the exposure and development processes of the second photosensitive film.
도 3i를 참조하면, 상기 제 2 감광막 패턴(79)을 마스크로 Cl2+ BCl3+ N2를 활성화시킨 플라즈마를 사용한 건식 식각 공정에 의해 상기 제 3 Ti/TiN층(77), 알루미늄층(75) 및 제 2 Ti/TiN층(73)을 식각하여 Ti/TiN/Al/Ti/TiN 적층 구조의 금속 배선을 형성한 다음, 상기 제 2 감광막 패턴(79)을 제거한다.Referring to FIG. 3I, the third Ti / TiN layer 77 and the aluminum layer may be formed by a dry etching process using a plasma in which Cl 2 + BCl 3 + N 2 is activated using the second photoresist pattern 79 as a mask. 75) and the second Ti / TiN layer 73 are etched to form a metal wiring having a Ti / TiN / Al / Ti / TiN stacked structure, and then the second photoresist layer pattern 79 is removed.
여기서, 종래 기술인 도 2와의 비교 도면인 도 4에서와 같이, 상기 제 2 트렌치(65)에 의해“H”의 지름을 갖는“T”자 구조의 텅스텐 플러그(71)를 형성하기 때문에 상기 텅스텐 플러그(71)의 면적 증가로 종래 기술보다 상기 금속 배선과 텅스텐 플러그(71) 간의 접촉 면적이 증가하게 된다.Here, the tungsten plug is formed by forming the "T" shaped tungsten plug 71 having the diameter of "H" by the second trench 65 as in FIG. An area of 71 increases the contact area between the metal wire and the tungsten plug 71 than in the prior art.
본 발명의 반도체 소자의 다층 금속 배선 형성 방법은“T”자 구조의 콘택홀을 형성한 후 상기 콘택홀을 매립하는“T”자 구조의 텅스텐 플러그를 형성하므로,다음과 같은 이유에 의해 금속 배선과 텅스텐 플러그간의 전기적인 접촉이 강화되어 소자의 안정성, 수율 및 신뢰성을 향상시키는 효과가 있다.The method for forming a multi-layered metal wiring of the semiconductor device of the present invention forms a "T" shaped tungsten plug which fills the contact hole after forming a "T" shaped contact hole. Electrical contact between the and the tungsten plug is strengthened, thereby improving the stability, yield and reliability of the device.
첫째, 종래의 텅스텐 플러그 상부 부위 면적보다“T”자 구조의 텅스텐 플러그가 넓게 형성되어 금속 배선과의 접촉면적이 증가되어 소자의 집적화로 축소된 접촉 면적을 보충한다.First, a “T” shaped tungsten plug is formed wider than the area of the upper portion of the conventional tungsten plug, thereby increasing the contact area with the metal wiring to compensate for the reduced contact area due to the integration of the device.
둘째,“T”자 구조의 텅스텐 플러그 종래의 텅스텐 플러그보다 단면적이 크므로 텅스텐 플러그 자체의 전기적인 저항이 저하된다.Secondly, the tungsten plug having a “T” structure has a larger cross-sectional area than a conventional tungsten plug, so that the electrical resistance of the tungsten plug itself is lowered.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052352A (en) * | 1995-12-26 | 1997-07-29 | 김주용 | Method for manufacturing metal wiring of semiconductor device |
| KR0185298B1 (en) * | 1995-12-30 | 1999-04-15 | 김주용 | Forming method of plug for contact hole |
| US5897369A (en) * | 1996-05-16 | 1999-04-27 | Lg Semicon Co., Ltd. | Method for forming interconnection of a semiconductor device |
| KR100197128B1 (en) * | 1995-12-30 | 1999-06-15 | 김영환 | Method for forming plug of semiconductor device |
| KR20010056822A (en) * | 1999-12-17 | 2001-07-04 | 박종섭 | Conductive line and interconnection thereof in semiconductor device and fabricating method thereof |
| JP2001274243A (en) * | 2000-03-24 | 2001-10-05 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
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2001
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052352A (en) * | 1995-12-26 | 1997-07-29 | 김주용 | Method for manufacturing metal wiring of semiconductor device |
| KR100197124B1 (en) * | 1995-12-26 | 1999-06-15 | 김영환 | Forming method for metal wiring in semiconductor divice |
| KR0185298B1 (en) * | 1995-12-30 | 1999-04-15 | 김주용 | Forming method of plug for contact hole |
| KR100197128B1 (en) * | 1995-12-30 | 1999-06-15 | 김영환 | Method for forming plug of semiconductor device |
| US5897369A (en) * | 1996-05-16 | 1999-04-27 | Lg Semicon Co., Ltd. | Method for forming interconnection of a semiconductor device |
| KR20010056822A (en) * | 1999-12-17 | 2001-07-04 | 박종섭 | Conductive line and interconnection thereof in semiconductor device and fabricating method thereof |
| JP2001274243A (en) * | 2000-03-24 | 2001-10-05 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
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