KR20010056822A - Conductive line and interconnection thereof in semiconductor device and fabricating method thereof - Google Patents

Abstract

PURPOSE: A wiring of semiconductor apparatus, wiring connecting unit and manufacturing method thereof is provided to improve the reliability of a device by reducing a resistance of a wiring connecting unit due to an outstanding increase of a plug and a connecting face of the upper part wiring, achieving a selective deposition of automatically aligned metal, and realizing a wiring and a wiring connecting unit with a uniform step coverage. CONSTITUTION: A dielectric layer(21) is formed on a substrate(20). A conductive plug interposes a first barrier layer(240), passes through the dielectric layer(21) and contacts to a predetermined part of the substrate(20). A trench has a predetermined wiring pattern as well as exposing the upper side of the first barrier layer(240) interposed on the conductive plug side and is formed by eliminating the predetermined part of the dielectric layer(21). A conductive layer is filled in the trench.

Description

Wiring and wiring connecting portion of semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring and wiring connection portions of a semiconductor device and a method of manufacturing the same, and more particularly, by forming a plug of a wiring connection portion connecting wirings formed on different layers and removing a predetermined portion of an intermetal dielectric. The present invention relates to a plug and metal wiring of a semiconductor device having a low wiring resistance and step coverage by increasing the contact area between the wiring and the plug by forming a wiring with a barrier metal layer on the side of the plug, and a method of manufacturing the same.

The wiring connection part and wiring for the electrical connection between the elements of the semiconductor device and the formation technology thereof are formed by forming a plug in a contact hole or a via hole of an interlayer insulating layer, and then patterning the wiring on the plug. Deeper, low step coverage, short circuit between wirings, and thus yield of product is poor.

In order to improve this, a dual damascene structure has been proposed as a method of forming a contact plug and a wiring at the same time. However, such a structure and its manufacturing method are excellent in mitigating a step difference from the surroundings. Further improvements in step coverage and reduced resistance at the wiring connections are needed.

1A to 1D are process cross-sectional views showing a wiring of a semiconductor device and a method of forming a connection portion thereof according to the prior art.

Referring to FIG. 1A, an insulating layer 11 is deposited on a semiconductor substrate 10 made of silicon by chemical vapor deposition (hereinafter, referred to as CVD). In the above description, the substrate 10 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

In order to form the first wiring, a metal is formed on the insulating layer 11 by sputtering or the like to form a lower metal layer, and then a photoresist is applied on the lower metal layer, followed by exposure and development using a first wiring mask. After forming an etching mask (not shown), the first metal layer 12 is formed by patterning the lower metal layer using the etching mask.

Next, an inter-metal dielectric 13 is deposited on the insulating layer 11 including the first wiring 12 with an oxide film or the like. In this case, the interlayer insulating layer 13 may be formed by combining tetra ethyl ortho silicate (TEOS) and spin on glass (SOG), and a main component thereof is SiO ₂ .

A predetermined portion of the interlayer insulating layer 13 is patterned by a photolithography method to form a trench in which a contact hole or via hole exposing the first wiring layer 12 and a pattern of the second wiring, which is the upper wiring, are engraved. That is, in a subsequent process, a plug for connecting the first wiring 12, which is the upper wiring and the lower wiring, is formed in the via hole, and the upper wiring is formed in the trench.

At this time, the contact hole and the trench are simultaneously patterned. The method is as follows.

First, a first hole defining a via hole forming portion is formed by removing an interlayer insulating layer to a predetermined depth. At this time, the surface of the first wiring 12 is not exposed by the first hole.

An etch mask having a trench pattern defined is formed on the interlayer insulating layer 13 above the portion including the first hole, and then the interlayer insulating layer 13 is removed by dry etching using an etch mask to form a trench. do. Therefore, during the trench forming etching, the interlayer insulating layer under the first hole is simultaneously etched to form a via hole having an extended upper portion.

Referring to FIG. 1B, the barrier layer 14 is formed on the remaining interlayer insulating layer 13 by the physical vapor deposition (PVD) method so as to contact the first wiring 12 through the trench and the via hole. At this time, the barrier layer 14 is formed by depositing Ti or TiN.

Referring to FIG. 1C, an upper conductive layer 15, such as a metal, is deposited by a method such as CVD or sputtering to form a second wiring, which is an upper wiring, on the barrier layer 14. Silver can be formed using Al, Cu, or the like. When copper is used, a copper seed layer (not shown) for forming a copper bulk layer (Cu bulk layer) on the surface of the barrier layer 14 is also formed by PVD deposition, and then a copper seed layer is formed. The copper bulk layer 15 is formed on the thickness by which the contact hole and trench are fully filled by the electroplating method used. Therefore, the connection part between wirings and the upper wiring formation layer were formed simultaneously.

Referring to FIG. 1D, a planarization process is performed on the formed copper bulk layer to expose a surface of the remaining interlayer insulating layer 13 to form a second wiring, which is an upper wiring electrically connected to the first wiring 12 without a separate patterning process. 150). At this time, the planarization step is a chemical mechanical polishing method.

However, in the semiconductor device according to the related art, the wiring connection part and the wiring forming method of the semiconductor device have problems such as improvement in the step coverage and narrowing of the area where the conductive layer formed in the second wiring and the via hole meet in the wiring connection part, resulting in a bottleneck and an increase in resistance. .

Accordingly, an object of the present invention is to form a wire by forming a plug of a wiring connection part connecting the wires formed on different layers and removing a predetermined portion of an intermetal dielectric to form a wire having a barrier metal layer on the plug side. The present invention provides a plug and a metal wiring of a semiconductor device having a low wiring resistance and a step coverage by increasing the contact area between the plug and the plug, and a method of manufacturing the same.

The wiring and wiring connection part of the semiconductor device according to the present invention for achieving the above object is a conductive layer penetrating the insulating layer through the insulating layer formed on the semiconductor substrate, the first barrier layer and in contact with a predetermined portion of the semiconductor substrate A trench formed with a plug, a predetermined wiring pattern, and at the same time exposing an upper surface of the first barrier layer interposed on a side surface of the conductive plug and removing a predetermined portion of the insulating layer; and a conductive layer filling the trench. It is made, including.

According to the present invention, there is provided a method of manufacturing a wiring and wiring connection part of a semiconductor device according to the present invention, forming a wiring insulating layer on a semiconductor substrate, and removing a predetermined portion of the wiring insulating layer to expose a portion of the semiconductor substrate. Forming a hole to form a hole; interposing the first barrier layer in the hole; forming a plug of a conductive material; and removing a predetermined portion of the wiring insulation layer to surround the plug. Forming a trench having a predetermined wiring pattern while exposing side surfaces, and forming an upper wiring with a conductive layer having a second barrier layer interposed therebetween.

1A to 1D are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the related art.

Figure 2 is a cross-sectional view of the wiring and wiring connection of the semiconductor device according to the present invention

3A to 3E are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the present invention.

According to the present invention, instead of filling the via hole and the upper trench with a conductive material in a single process, a via hole and a wiring connection part having a damascene structure are formed in the interlayer insulating layer, and then a conductive plug for filling the via hole is formed. A trench having a pattern of upper and lower wirings is formed in an intaglio pattern by exposing the upper side surface, and then embedded in a conductive material such as a metal with a barrier metal layer interposed therebetween to form the upper wiring and its connection portion. Therefore, the contact surface of the plug and the upper wiring is significantly increased than in the prior art to reduce the resistance of the wiring connection portion, and the selective deposition of the auto-aligned metal is completed to complete the damascene structure.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a wiring and a wiring connection unit of a semiconductor device according to the present invention.

Referring to FIG. 2, an interlayer insulating layer 21 is formed on a semiconductor substrate 20 made of silicon or the like on which elements such as transistors and capacitors are formed, and electrically connected elements are electrically connected on the interlayer insulating layer 21. The first wiring 22, which is a lower wiring made of aluminum or the like, is patterned.

An intermetal dielectric 23 is formed on the first wiring 22 and the interlayer insulating layer 21 to electrically insulate the lower wiring from the first wiring 22 and the upper wiring.

A via hole or a contact hole is formed to remove a predetermined portion of the wiring insulation layer 23 to expose a part of the surface of the first wiring 22. A first barrier for reducing resistance between the wirings is formed on the bottom and side surfaces of the via hole. The layer 240 is formed in contact with the first wiring 22. In this case, the first barrier layer 240 is made of metal such as Ti or TiN.

A plug 250 for filling the via hole with a conductive material is formed on the surface of the first barrier layer 240. The plug 250 made of tungsten or the like electrically connects the first wiring 22 that is the upper wiring and the lower wiring 22.

A trench for exposing the upper surface of the first barrier layer 240 formed on the wiring insulation layer 23 has a pattern of the second wiring 270 as the upper wiring and is engraved in the wiring insulation layer 23.

The trench is covered with a second barrier layer 260 made of Ti, TiN, or the like, and the second wiring 270 filling the trench is formed of metal such as aluminum or copper on the surface of the second barrier layer 260. .

Accordingly, the second wiring 270 enclosed by the second barrier layer 260 and the first wiring 22 as the lower interconnection are electrically connected to each other by the plug 250 enclosed by the first barrier layer 240. It has a structure connected to it.

In this case, since the plug 250 is in contact with the second wiring 270 in the form of the first and second barrier layers 240 and 260, the plug 250 is in contact with the upper surface of the plug in the prior art. The contact area is increased, the electrical resistance is reduced, the alignment margin is increased, and the planarization of the wiring insulation layer 23 is also advantageous.

3A to 3E are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the present invention.

Referring to FIG. 3A, an interlayer dielectric 21 made of an oxide film or the like is deposited on a semiconductor substrate 20 made of silicon by chemical vapor deposition (hereinafter, referred to as CVD). In the above description, the substrate 20 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

In order to form the first wiring, a metal such as aluminum is deposited on the interlayer insulating layer 21 by CVD or sputtering to form a lower metal layer, and then a photoresist is applied on the lower metal layer to form a first wiring. An etch mask (not shown) is formed by exposure and development using an exposure mask for light, and then the lower metal layer is patterned using the etch mask to form the first wiring 22.

Next, an inter-metal dielectric 23 is deposited to a predetermined thickness on the interlayer insulating layer 21 including the first wiring 22 by an oxide film or the like. In this case, the metal wiring insulation layer 23 may be formed by combining tetra ethyl ortho silicate (TEOS) and spin on glass (SOG) having excellent flowability, and a main component thereof is SiO ₂ .

Then, a predetermined portion of the metal wiring insulating layer 23 is patterned by a photolithography method to form contact holes or via holes that expose predetermined portions of the first wiring 22. That is, in a subsequent process, a metal plug is formed in the via hole to connect the first wiring 22, which is the upper wiring and the lower wiring. In this case, the via hole is formed by removing a part of the metal wiring insulating layer 23 by photolithography using anisotropic etching such as dry etching.

The first barrier layer 24 is formed by sputtering or physical vapor deposition (PVD) on the remaining metal wiring insulating layer 23 to be in contact with the first wiring 22 through the via hole. In this case, the first barrier layer 24 is formed by depositing Ti or TiN.

Next, a conductive material for forming a plug such as tungsten is deposited on the first barrier layer 24 to form the metal layer 25. At this time, the metal layer 25 is formed to a thickness sufficient to sufficiently fill the via hole.

Referring to FIG. 3B, the upper surface of the metallization insulating layer 23 is exposed by etching back the metal layer and the first barrier layer. As a result, a plug 250 made of the remaining metal layer 250 having the remaining first barrier layer 240 interposed between the metal wiring insulating layer 23 is formed.

Referring to FIG. 3C, a photoresist is applied onto the metallization insulating layer including the surface of the plug 250 and the first barrier layer 240.

The photoresist pattern (not shown) is formed by exposing and developing sidewalls of the plug 250 and the first barrier layer 240, and performing exposure and development using an exposure mask defining a second wiring pattern.

Next, the metal wiring insulating layer 23 of the portion not protected by the photoresist pattern is removed to a predetermined depth to expose the plug side to be the wiring connection portion, and the trench G defining the portion where the second wiring is to be formed. Form in intaglio form. In this case, the trench is formed by anisotropic etching, such as dry etching, and an etchant having a high etching selectivity is used between the first barrier layer 240, the plug 250, and the metallization insulating layer 23.

Therefore, since the upper side surface of the first barrier layer 240 is exposed and the contact area with the second wiring formed thereafter is increased, the resistance of the wiring connection portion can be reduced.

Then, the photoresist pattern is removed by a method such as oxygen ashing (O ₂ ashing).

Referring to FIG. 3D, a second barrier layer 26 is formed on the surface of the metal wiring insulation layer 23 including the trench surface engraved in the metal wiring insulation layer 23 and the upper surface of the plug 250. . In this case, the second barrier layer 26 is formed by depositing Ti or TiN by sputtering. Therefore, the upper surface of the plug 250 in which the barrier metal is not formed is also covered with the barrier metal.

In order to form the second wiring, which is the upper wiring, an upper conductive layer 27 made of a conductor such as metal is formed on the second barrier layer 26 by a method such as CVD, sputtering, or electroplating. In this case, the upper conductive layer may be formed using Al, Cu, or the like. When copper is used, a copper seed layer (not shown) for forming a copper bulk layer (Cu bulk layer) on the surface of the second barrier layer 26 is also formed by depositing by PVD method, and then copper seed A copper bulk layer 27, which is an upper conductive layer, is formed on the thickness to sufficiently fill the contact holes and trenches by elecroplating using a layer. Therefore, the connection part between wirings and the upper wiring formation layer were formed simultaneously.

Referring to FIG. 3E, a trench is formed by a plug 250 having a barrier metal layer interposed therebetween by performing a planarization process on the formed upper metal layer (copper bulk layer) to expose the remaining interlayer insulating layer 23 surface. A second wiring 270 is formed to be buried and an upper wiring electrically connected to the first wiring 22. At this time, not only the upper metal layer but also the second barrier layer located on the surface of the interlayer insulating layer 23 is removed together, and the upper metal layer and the second barrier metal layer are removed by etch back or chemical mechanical polishing.

Therefore, the first barrier layer 240 and the second barrier layer 260 of the second wiring 270, which are disposed on the upper side of the plug 250, contact each other to allow the second wiring 270 and the first wiring 22 to contact each other. Are electrically connected, and the mutual contact area is increased to reduce the electrical resistance between the interlayer wirings.

Accordingly, the present invention is to increase the contact surface of the plug and the upper wiring is significantly higher than the conventional one to reduce the resistance of the wiring connection portion, and the selective deposition of the auto-aligned metal is made to implement the wiring and wiring connection portion having a uniform step coverage It has the advantage of improving the reliability.

Claims (9)

An insulating layer formed on the semiconductor substrate, A conductive plug passing through the insulating layer and contacting a predetermined portion of the semiconductor substrate via a first barrier layer; A trench having a predetermined wiring pattern and simultaneously exposing an upper surface of the first barrier layer interposed on a side surface of the conductive plug and removing a predetermined portion of the insulating layer; Wiring and wiring connection portions of a semiconductor device comprising a conductive layer filling the trench. The semiconductor device wiring and wiring connection unit of claim 1, wherein an impurity diffusion region or a lower wiring is formed in the predetermined portion. The wiring and wiring connection part of a semiconductor device according to claim 1, wherein a second barrier layer is interposed between the trench inner surface and the conductive layer. The semiconductor device wiring and wiring connection unit according to claim 1, wherein the trench formation depth is formed such that a contact area with the conductive layer of the first barrier layer is larger than an upper surface area of the plug. Forming a wiring insulation layer on the semiconductor substrate; Removing a predetermined portion of the wiring insulation layer to form a hole exposing a portion of the semiconductor substrate; Forming a plug having a first barrier layer in the hole and having a conductive material; Removing a predetermined portion of the wiring insulation layer to expose a side surface of the first barrier layer surrounding the plug and to form a trench having a predetermined wiring pattern; And forming a top wiring with a conductive layer having a second barrier layer in the trench. The method of claim 5, wherein the first barrier layer and the second barrier layer are formed of Ti or TiN, and the upper wiring is formed of metal. The method of claim 5, wherein the wiring pattern is formed to expose the side surface of the first barrier layer positioned on the upper surface of the plug and to define the upper wiring. The method of claim 5, wherein the upper wiring is made of copper. The method of claim 5, further comprising forming a lower wiring on an upper portion of the semiconductor substrate or forming an impurity diffusion region on a predetermined portion of the semiconductor substrate.