KR970052352A - Method for manufacturing metal wiring of semiconductor device - Google Patents

Method for manufacturing metal wiring of semiconductor device Download PDF

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Publication number
KR970052352A
KR970052352A KR1019950056949A KR19950056949A KR970052352A KR 970052352 A KR970052352 A KR 970052352A KR 1019950056949 A KR1019950056949 A KR 1019950056949A KR 19950056949 A KR19950056949 A KR 19950056949A KR 970052352 A KR970052352 A KR 970052352A
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South Korea
Prior art keywords
film
contact hole
forming
metal wiring
tungsten
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KR1019950056949A
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Korean (ko)
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KR100197124B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 노광장비의 노광 한계보다 작은 미세한 콘택홀 패턴을 형성하여 금속배선을 제조하는 반도체 소자의 금속배선 제조방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a method for manufacturing a metal wiring of a semiconductor device for forming a metal wiring by forming a fine contact hole pattern smaller than the exposure limit of the exposure equipment of the semiconductor device.

이와 같은 목적을 달성하기 위한 본 발명의 금속배선 제조방법은 반도체 기판 상부에 제1절연막과, 제1금속배선, 제2절연막을 형성하고, 제2절연막의 소정 부분에 상기 제2절연막의 두께의 반의 깊이를 갖는 제1콘택홀을 형성한 다음, 제1콘택홀을 포함한 제2절연막 전면에 감광막 마스크를 형성하여 노출된 부분을 비등방성 식각하여 초미세 패턴의 콘택홀을 형성한다. 이후, 콘택홀 부분을 포함한 전면에 제2금속배선막을 중착하여 패턴을 형성시키는 것을 특징으로 한다.In order to achieve the above object, the metal wiring manufacturing method of the present invention forms a first insulating film, a first metal wiring, and a second insulating film on a semiconductor substrate, and a predetermined portion of the second insulating film has a thickness of the second insulating film. After forming a first contact hole having a half depth, a photoresist mask is formed on the entire surface of the second insulating layer including the first contact hole, and an exposed portion is anisotropically etched to form a contact hole having an ultra fine pattern. Subsequently, the second metal wiring layer is formed on the entire surface including the contact hole, thereby forming a pattern.

Description

반도체 소자의 금속배선 제조방법Method for manufacturing metal wiring of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 실시예에 따른 금속배선막의 연결상태를 보여주는 평면도.1 is a plan view showing a connection state of a metal wiring film according to a conventional embodiment.

제2도는 제1도에서 A-A'선을 따라 절단한 단면도.2 is a cross-sectional view taken along the line AA ′ in FIG. 1.

제3도는 본 발명의 실시예에 따른 금속배선막의 연결상태를 보여주는 평면도.3 is a plan view showing a connection state of the metal wiring film according to an embodiment of the present invention.

제4도는 제3도의 B-B'선을 따라 절단한 단면도로서, 제1실시예의 공정 흐름도.4 is a cross-sectional view taken along the line B-B 'of FIG. 3, showing the process flow of the first embodiment.

제5도는 제3도의 B-B'선을 따라 절단한 단면도로서, 제2실시예에 따른 공정 흐름도.5 is a cross-sectional view taken along the line BB ′ of FIG. 3, and a process flow diagram according to the second embodiment.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체 기판 12 : 제1절연막11 semiconductor substrate 12 first insulating film

13 : 제1금속배선 14 : 제2절연막13: first metal wiring 14: second insulating film

15, 15' : 콘택홀 16 : 감광막 마스크15, 15 ': contact hole 16: photoresist mask

17, 17' : 장벽 금속막 18, 18' : 중간 금속배선막17, 17 ': barrier metal film 18, 18': intermediate metal wiring film

19, 21 : 알루미늄 합금막 및 반사방지막 20 : 텅스텐 플러그19, 21: aluminum alloy film and antireflection film 20: tungsten plug

Claims (13)

반도체 기판 상부에 소정의 제1 절연막을 형성하는 단계; 상기 제1 절연막 상에 제 1 금속배선을 형성하는 단계; 상기 제1 금속배선을 포함한 제1 절연막 전면에 제2 절연막을 형성하는 단계; 상기 제2 절연막의 소정 부분에 상기 제2 절연막의 두께의 반의 깊이를 갖는 제1 콘택홀을 형성하는 단계; 상기 제1 콘택홀을 포함한 제2 절연막 전면에 감광막을 소정 두께로 도포하는 단계; 상기 제1 콘택홀의 일부를 포함한 제2 절연막 상의 소정 부분을 노출시키는 감광막 마스크를 형성하는 단계; 상기 감광막 마스크를 식각장벽으로 하여 노출된 제2 절연막을 제1 금속배선이 드러날 때까지 비등방성 식각하여 제2 콘택홀을 형성하는 단계; 상기 제2 콘택홀을 포함한 전면에, 콘택홀을 매립하기 위한 텅스텐의 증착시 텅스텐과 질화막과의 직접적인 접착에 의한 결합력의 약화를 방지하고, 콘택홀 내부에서의 동공의 생성을 방지하는, 장벽 금속막을 소정 두께로 증착하는 단계; 상기 장벽 금속막 위에 상기 장벽 금속막을 덮는 텅스텐막을 상기 콘택홀을 매립할 정도의 소정 두께로 증착하는 단계; 상기 텅스텐 막위에 소정 두께의 알루미늄 합금막을 증착하는 단계; 상기 알루미늄 합금막 위에 패턴 형성을 위한 감광막의 노광시 반사를 방지하기 위한 반사방지막을 증착하는 단계; 상기 반사방지막 위에 감광막 마스크를 형성하는 단계; 상기 감광막 마스크를 식각장벽으로 하여 동일 식각 챔버에서 각각의 막에 따라 다른 식각용 개스를 공급하여 식각하므로써 금속배선층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.Forming a predetermined first insulating layer on the semiconductor substrate; Forming a first metal wiring on the first insulating film; Forming a second insulating film on an entire surface of the first insulating film including the first metal wiring; Forming a first contact hole having a depth of half the thickness of the second insulating film in a predetermined portion of the second insulating film; Applying a photosensitive film to a whole surface of the second insulating film including the first contact hole to a predetermined thickness; Forming a photoresist mask exposing a predetermined portion on a second insulating layer including a portion of the first contact hole; Anisotropically etching the exposed second insulating layer using the photoresist mask as an etch barrier until the first metal wiring is exposed to form a second contact hole; Barrier metal on the front surface including the second contact hole, preventing the weakening of the bonding force due to direct adhesion between the tungsten and the nitride film during deposition of tungsten for embedding the contact hole, and preventing the generation of pupils in the contact hole. Depositing a film to a predetermined thickness; Depositing a tungsten film covering the barrier metal film to a predetermined thickness to fill the contact hole on the barrier metal film; Depositing an aluminum alloy film having a predetermined thickness on the tungsten film; Depositing an anti-reflection film on the aluminum alloy layer to prevent reflection upon exposure of the photosensitive film for pattern formation; Forming a photoresist mask on the anti-reflection film; And forming a metal wiring layer by supplying and etching different etching gases according to each film in the same etching chamber using the photoresist mask as an etch barrier to form a metal wiring layer. 제1항에 있어서, 상기 제1 제2 절연막은 TEOS 산화막, BPSG막, SOG막, PE-TEOS 산화막 중에서 하나 또는 그 이상을 선택적으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the first second insulating layer selectively forms one or more of a TEOS oxide film, a BPSG film, an SOG film, and a PE-TEOS oxide film. 제1항에 있어서, 상기 장벽 금속막은 TiN인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the barrier metal film is TiN. 제3항에 있어서, 상기 TiN은 300 내지 900Å의 두께 범위로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 3, wherein the TiN is formed in a thickness range of 300 to 900 kPa. 제1항에 있어서, 상기 텅스텐막의 두께는 5,000 내지 7,000Å의 범위로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the thickness of the tungsten film is in the range of 5,000 to 7,000 kPa. 제1항에 있어서, 상기 알루미늄 합금막 및 반사방지막의 두께는 5,000 내지 10,000Å의 범위로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the aluminum alloy film and the anti-reflection film have a thickness in a range of 5,000 to 10,000 kW. 제1항에 있어서, 상기 금속배선막의 식각단계에서 알루미늄 합금막 및 반사방지막의 경우, Cl2, BCl3개스를 공급하여 식각하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein in the etching of the metal wiring layer, the aluminum alloy layer and the anti-reflective layer are etched by supplying Cl 2 and BCl 3 gases. 제1항에 있어서, 상기 금속배선막의 식각단계에서 텅스텐막과 장벽 금속막의 경우, SF6개스를 공급하여 식각하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the tungsten film and the barrier metal film are etched by supplying SF 6 gas in the etching step of the metal wiring film. 반도체 기판 상부에 소정의 제1 절연막을 형성하는 단계; 상기 제1 절연막 상에 제1 금속배선을 형성하는 단계; 상기 제1 금속배선을 포함한 제1 절연막 전면에 제2 절연막을 형성하는 단계; 상기 제2 절연막의 소정 부분에 상기 제2 절연막의 두께의 반의 깊이를 갖는 제1 콘택홀을 형성하는 단계; 상기 제1 콘택홀을 포함한 제2 절연막 전면에 감광막을 소정 두께로 도포하는 단계; 상기 제1 콘택홀의 일부를 포함한 제2 절연막 상의 소정 부분을 노출시키는 감광막 마스크를 형성하는 단계; 상기 감광막 마스크를 식각장벽으로 하여 노출된 제2 절연막을 제 1 금속배선이 드러날 때까지 비등방성 식각하여 제2 콘택홀을 형성하는 단계; 감광막 마스크를 제거하고, 상기 제2 콘택홀을 포함한 전면에, 콘택홀을 매립하기 위한 텅스텐의 증착시 텅스텐과 질화막과의 직접적인 접착에 의한 결합력의 약화를 방지하고, 콘택홀 내부에서의 동공의 생성을 방지하는, 장벽 금속막을 소정 두께로 증착하는 단계; 상기 장벽 금속막 위에 상기 장벽 금속막을 덮는 텅스텐막을 상기 콘택홀을 매립할 정도의 소정 두께로 증착하는 단계; 상기 텅스텐 막 위에 콘택홀 부분만을 덮는 감광막 마스크를 형성하는 단계; 상기 감광막 마스크를 식각장벽으로 하여 노출된 텅스텐막을 식각하는 단계; 전면에 상기 텅스텐 플러그와 전기적으로 연결되는 제2 금속배선막을 형성하는 단계; 상기 제2 금속배선막의 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.Forming a predetermined first insulating layer on the semiconductor substrate; Forming a first metal wiring on the first insulating film; Forming a second insulating film on an entire surface of the first insulating film including the first metal wiring; Forming a first contact hole having a depth of half the thickness of the second insulating film in a predetermined portion of the second insulating film; Applying a photosensitive film to a whole surface of the second insulating film including the first contact hole to a predetermined thickness; Forming a photoresist mask exposing a predetermined portion on a second insulating layer including a portion of the first contact hole; Anisotropically etching the exposed second insulating layer using the photoresist mask as an etch barrier until the first metal wiring is exposed to form a second contact hole; Removing the photoresist mask and preventing the weakening of the bonding force due to direct adhesion between the tungsten and the nitride film during deposition of tungsten for embedding the contact hole on the front surface including the second contact hole, and generation of pupils in the contact hole. Depositing a barrier metal film to a predetermined thickness, thereby preventing; Depositing a tungsten film covering the barrier metal film to a predetermined thickness to fill the contact hole on the barrier metal film; Forming a photoresist mask on the tungsten film to cover only a portion of the contact hole; Etching the exposed tungsten film using the photoresist mask as an etch barrier; Forming a second metal wiring film electrically connected to the tungsten plug on a front surface thereof; And forming a pattern of the second metal interconnection film. 제9항에 있어서, 상기 제1, 제2 절연막은 TEOS 산화막, BPSG막, SOG막, PE-TEOS 산화막 중에서 하나 또는 그 이상을 선택적으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.10. The method of claim 9, wherein the first and second insulating films selectively form one or more of a TEOS oxide film, a BPSG film, an SOG film, and a PE-TEOS oxide film. 제9항에 있어서, 상기 장벽 금속막은 TiN인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.10. The method of claim 9, wherein the barrier metal film is TiN. 제11항에 있어서, 상기 TiN은 300 내지 900Å의 두께 범위로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.12. The method of claim 11, wherein the TiN is formed in a thickness range of 300 to 900 GPa. 제9항에 있어서, 상기 텅스텐막의 두께는 5,000 내지 7,000Å의 범위로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.10. The method of claim 9, wherein the thickness of the tungsten film is in the range of 5,000 to 7,000 kPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950056949A 1995-12-26 1995-12-26 Forming method for metal wiring in semiconductor divice KR100197124B1 (en)

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KR1019950056949A KR100197124B1 (en) 1995-12-26 1995-12-26 Forming method for metal wiring in semiconductor divice

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KR100197124B1 KR100197124B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100421280B1 (en) * 2001-12-04 2004-03-09 주식회사 하이닉스반도체 Method for forming a metal line of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100421280B1 (en) * 2001-12-04 2004-03-09 주식회사 하이닉스반도체 Method for forming a metal line of semiconductor device

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