KR970052309A - Method for manufacturing metal wiring of semiconductor device - Google Patents

Method for manufacturing metal wiring of semiconductor device Download PDF

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Publication number
KR970052309A
KR970052309A KR1019950052573A KR19950052573A KR970052309A KR 970052309 A KR970052309 A KR 970052309A KR 1019950052573 A KR1019950052573 A KR 1019950052573A KR 19950052573 A KR19950052573 A KR 19950052573A KR 970052309 A KR970052309 A KR 970052309A
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film
forming
aluminum alloy
pattern
metal wiring
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KR1019950052573A
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KR0184954B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 노광장비의 노광 한계보다 작은 미세한 콘택홀 패턴을 형성하여 금속배선을 제조하는 반도체 소자의 금속배선 제조방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a method for manufacturing a metal wiring of a semiconductor device for forming a metal wiring by forming a fine contact hole pattern smaller than the exposure limit of the exposure equipment of the semiconductor device.

이와 같은 목적을 달성하기 위한 본 발명의 금속배선 제조방법은 반도체 기판 상부에 제 1 절연막과, 제 1 금속배선, 제 2 절연막, 질화막을 형성하고, 질화막의 소정 부분에 알루미늄 합금막 패턴을 형성한 다음, 알루미늄 합금막 패턴의 노출된 부분을 덮는 선택적 텅스텐막 패턴을 형성한다. 이 후, 선택적 텅스텐막 패턴의 사이에 노출된 질화막과 절연막을 제 1 금속배선이 노출될 때까지 비등방성 식각하므로써 콘택홀을 형성한다. 선택적 텅스텐막의 중앙부의 소정 부위를 노출시키는 감광막 마스크 패턴을 형성하여 제 2 절연막이 노출될 때까지 비등방성 식각하고, 블랭킷 텅스텐막을 전며네 증착한다. 다음으로 텅스텐 플러그를 형성치 않고, 바로 제 2 금속배선을 형성하는 것을 특징으로 한다.(선택적 제4도)In the metal wire manufacturing method of the present invention for achieving the above object, the first insulating film, the first metal wiring, the second insulating film, the nitride film is formed on the semiconductor substrate, and the aluminum alloy film pattern is formed on a predetermined portion of the nitride film. Next, a selective tungsten film pattern is formed to cover the exposed portion of the aluminum alloy film pattern. Thereafter, a contact hole is formed by anisotropically etching the nitride film and the insulating film exposed between the selective tungsten film patterns until the first metal wiring is exposed. A photosensitive film mask pattern is formed to expose a predetermined portion of the central portion of the selective tungsten film, anisotropically etched until the second insulating film is exposed, and the blanket tungsten film is deposited four or four times. Next, a second metal wiring is formed immediately without forming a tungsten plug. (Optional FIG. 4)

Description

반도체 소자의 금속배선 제조방법Method for manufacturing metal wiring of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 실시예에 따른 금속배선막의 연결상태를 보여주는 평면도.3 is a plan view showing a connection state of the metal wiring film according to an embodiment of the present invention.

제4도는 제3도의 B-B'선을 따라 절단한 단면도로서, 제1실시예의 공정 흐름도.4 is a cross-sectional view taken along the line B-B 'of FIG. 3, showing the process flow of the first embodiment.

Claims (17)

반도체 기판 상부에 소정의 제 1 절연막을 형성하는 단계; 상기 제 1 절연막 상에 제 1 금속배선을 형성하는 단계; 상기 제 1 금속배선을 포함한 제 1 절연막 전면에 제 2 절연막을 형성하는 단계; 상기 제 2 절연막 위에 소정 두께의 질화막을 증착하는 단계; 상기 질화막 위의 소정 부분에 알루미늄 합금막을 소정 두께로 증착한 다음 패턴을 형성하는 단계; 상기 알루미늄 합금막 패턴의 노출된 부분을 소정 두께로 덮는 선택적 텅스텐막을 형성하는 단계; 상기 선택적 텅스텐막 패턴 사이의 노출된 질화막과 제 2 절연막을 제 2 금속배선막의 표면이 노출될 때까지 비등방성 식각하여 콘택홀을 형성하는 단계; 상기 선택적 텅스텐막 패턴의 중앙부 소정 부위를 노출시키는 감광막 마스크 패턴을 형성한 다음, 선택적인 텅스텐막, 알루미늄 합금막 패턴 및 질화막을 상기 제 2 절연막이 노출될 때까지 식각하는 단계; 감광막 마스크를 제거하고, 전면에 블랭킷 텅스텐막을 소정 두께로 형성하는 단계; 전면에 알루미늄 합금막 및 TiN막의 적층막을 소정 두께만큼 증착하는 단계; 소정의 감광막 마스크 패턴을 형성하여 알루미늄 합금막 및 TiN막의 적층막과 블랭킷 텅스텐막을 동시에 식각하여 제2 금속배선 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.Forming a predetermined first insulating film on the semiconductor substrate; Forming a first metal wiring on the first insulating film; Forming a second insulating film over the entire first insulating film including the first metal wiring; Depositing a nitride film having a predetermined thickness on the second insulating film; Depositing an aluminum alloy film to a predetermined thickness on the nitride film and then forming a pattern; Forming a selective tungsten film covering the exposed portion of the aluminum alloy film pattern to a predetermined thickness; Anisotropically etching the exposed nitride film and the second insulating film between the selective tungsten film patterns until the surface of the second metal wiring film is exposed to form a contact hole; Forming a photoresist mask pattern exposing a central portion of the selective tungsten film pattern, and then etching the optional tungsten film, the aluminum alloy film pattern, and the nitride film until the second insulating film is exposed; Removing the photoresist mask, and forming a blanket tungsten film on the entire surface to a predetermined thickness; Depositing a laminated film of an aluminum alloy film and a TiN film on the entire surface by a predetermined thickness; And forming a second photoresist pattern by simultaneously etching a laminated film of an aluminum alloy film and a TiN film and a blanket tungsten film by forming a predetermined photoresist mask pattern. 제1항에 있어서, 상기 제 1, 제 2 절연막은 TEOS 산화막, BPSG막, SOG막, PE-TEOS 산화막 중에서 하나 또는 그 이상을 선택적으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the first and second insulating layers selectively form one or more of a TEOS oxide film, a BPSG film, an SOG film, and a PE-TEOS oxide film. 제1항에 있어서, 상기 질화막의 두께는 300 내지 500Å 범위인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the nitride film has a thickness in a range of 300 to 500 GPa. 제1항에 있어서, 상기 알루미늄 합금막 패턴의 두께는 500 내지 1,000Å 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the aluminum alloy layer pattern has a thickness in a range of 500 to 1,000 GPa. 제1항에 있어서, 상기 선택적 텅스텐막 패턴의 두께는 1,000 내지 3,000Å의 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein a thickness of the selective tungsten film pattern is in a range of 1,000 to 3,000 kPa. 제1항에 있어서, 상기 블랭킷 텅스텐막의 두께는 5,000 내지 8,000Å의 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the thickness of the blanket tungsten film is in the range of 5,000 to 8,000 kPa. 제1항에 있어서, 상기 알루미늄 합금막 및 TiN의 적층막의 두께는 5,000 내지 10,000Å 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein a thickness of the aluminum alloy film and the TiN laminate film is in a range of 5,000 to 10,000 GPa. 제1항에 있어서, 상기 알루미늄 합금막 및 TiN의 적층막은 스퍼터링법으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the aluminum alloy film and the TiN laminate film are formed by a sputtering method. 제1항에 있어서, 상기 제 2 금속배선 형성을 위한 알루미늄 합금막 및 TiN의 적층막과 블랭킷 텅스텐막의 식각은 동일 챔버에서 식각을 위한 공급 개스만을 달리하면서 행하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 1, wherein the etching of the aluminum alloy film and the TiN laminated film and the blanket tungsten film for forming the second metal wiring is performed in the same chamber while changing only the supply gas for etching in the metal chamber of the semiconductor device. Way. 반도체 기판 상부에 소정의 제 1 절연막을 형성하는 단계; 상기 제 1 절연막 상에 제 1 금속배선을 형성하는 단계; 상기 제 1 금속배선을 포함한 제 1 절연막 전면에 제 2 절연막을 형성하는 단계; 상기 제 2 절연막 위의 소정 부분에 알루미늄 합금막을 소정 두께로 증착한 다음 패턴을 형성하는 단계; 상기 알루미늄 합금막 패턴의 노출된 부분을 소정 두께로 덮는 텅스텐막을 형성하는 단계; 상기 텅스텐막 패턴 사이의 노출된 제 2 절연막을 제 1 금속배선막의 표면이 노출될 때까지 비등방성 식각하여 콘택홀을 형성하는 단계; 상기 선택적 텅스텐막 패턴의 중앙부 소정부위를 노출시키는 감광막 마스크 패턴을 형성한 다음, 선택적인 텅스텐막, 알루미늄 합금막 패턴을 상기 제 2 절연막이 노출될 때까지 식각하는 단계; 감광막 마스크를 제거하고, 전면에 블랭킷 텅스텐막을 소정 두께로 형성하는 단계; 전면에 알루미늄 합금막 및 TiN막의 적층막을 소정 두께만큼 증착하는 단계; 소정의 감광막 마스크 패턴을 형성하여 알루미늄 합금막 및 TiN막의 적층막과 블랭킷 텅스텐막을 동시에 식각하여제2 금속배선 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.Forming a predetermined first insulating film on the semiconductor substrate; Forming a first metal wiring on the first insulating film; Forming a second insulating film over the entire first insulating film including the first metal wiring; Depositing an aluminum alloy film to a predetermined thickness on the predetermined portion over the second insulating film, and then forming a pattern; Forming a tungsten film covering the exposed portion of the aluminum alloy film pattern to a predetermined thickness; Anisotropically etching the exposed second insulating film between the tungsten film patterns until the surface of the first metal wiring film is exposed to form a contact hole; Forming a photoresist mask pattern exposing a predetermined portion of a central portion of the selective tungsten film pattern, and then etching the selective tungsten film and aluminum alloy film pattern until the second insulating film is exposed; Removing the photoresist mask, and forming a blanket tungsten film on the entire surface to a predetermined thickness; Depositing a laminated film of an aluminum alloy film and a TiN film on the entire surface by a predetermined thickness; And forming a second photoresist pattern by simultaneously etching a laminate film of an aluminum alloy film, a TiN film, and a blanket tungsten film by forming a predetermined photoresist mask pattern. 제10항에 있어서, 상기 제 1, 제 2 절연막은 TEOS 산화막, BPSG막, SOG막, PE-TEOS 산화막 중에서 하나 또는 그 이상을 선택적으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 10, wherein the first and second insulating layers selectively form one or more of a TEOS oxide film, a BPSG film, an SOG film, and a PE-TEOS oxide film. 제10항에 있어서, 상기 알루미늄 합금막 패턴의 두께는 500 내지 1,000Å 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 10, wherein the thickness of the aluminum alloy layer pattern is in a range of 500 to 1,000 GPa. 제10항에 있어서, 상기 선택적 텅스텐막 패턴의 두께는 1,000 내지 3,000Å의 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 10, wherein the selective tungsten film pattern has a thickness in a range of 1,000 to 3,000 kPa. 제10항에 있어서, 상기 블랭킷 텅스텐막의 두께는 5,000 내지 8,000Å의 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 10, wherein the blanket tungsten film has a thickness in a range of 5,000 to 8,000 kPa. 제10항에 있어서, 상기 알루미늄 합금막 및 TiN의 적층막의 두께는 5,000 내지 10,000Å 범위인 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of claim 10, wherein a thickness of the aluminum alloy film and the TiN laminated film is in a range of 5,000 to 10,000 kPa. 제10항에 있어서, 상기 알루미늄 합금막 및 TiN의 적층막은 스퍼터링법으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.The method of manufacturing a metal wiring of a semiconductor device according to claim 10, wherein the laminated film of the aluminum alloy film and the TiN is formed by a sputtering method. 제10항에 있어서, 상기 제 2 금속배선 형성을 위한 알루미늄 합금막 및 TiN의 적층막과 블랭킷 텅스텐막의 식각은 동일 챔버에서 식각을 위한 공급 개스만을 달리하면서 행하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.11. The method of claim 10, wherein the etching of the aluminum alloy film and TiN laminated film and the blanket tungsten film for forming the second metal wiring is performed in the same chamber while changing only the supply gas for etching metal wiring manufacturing of a semiconductor device Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052573A 1995-12-20 1995-12-20 Manufacturing method of metal wiring KR0184954B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100706800B1 (en) * 2006-01-02 2007-04-12 삼성전자주식회사 Method of fabricating metal wiring of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100706800B1 (en) * 2006-01-02 2007-04-12 삼성전자주식회사 Method of fabricating metal wiring of semiconductor device
US7871829B2 (en) 2006-01-02 2011-01-18 Samsung Electronics Co., Ltd. Metal wiring of semiconductor device and method of fabricating the same

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