KR0144247B1 - Forming method of multi-layer wiring - Google Patents
Forming method of multi-layer wiringInfo
- Publication number
- KR0144247B1 KR0144247B1 KR1019940016638A KR19940016638A KR0144247B1 KR 0144247 B1 KR0144247 B1 KR 0144247B1 KR 1019940016638 A KR1019940016638 A KR 1019940016638A KR 19940016638 A KR19940016638 A KR 19940016638A KR 0144247 B1 KR0144247 B1 KR 0144247B1
- Authority
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- South Korea
- Prior art keywords
- layer
- forming
- wiring
- interlayer insulating
- film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000010410 layer Substances 0.000 claims abstract description 58
- 239000011229 interlayer Substances 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000010408 film Substances 0.000 description 49
- 238000000151 deposition Methods 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 다층배선 형성방법에 관한 것으로, 에치백 공정없이 층간절연막 평탄화 및 콘택홀 형성을 동시에 이룰 수 있도록 공정을 단순화하기 위한 것이다.The present invention relates to a method for forming a multilayer wiring, and to simplify the process so that the interlayer insulating film can be planarized and the contact hole can be simultaneously formed without an etch back process.
본 발명은 반도체 기판상에 형성된 절연막 상부에 하층배선을 형성하는 공정과, 상기 하층배선의 소정부분 상부에만 선택적으로 희생막을 형성하는 공정, 결과물 전면에 상기 희생막의 두께보다 얇은 두께로 층간절연막을 형성하는 공정, 상기 층간절연막상에 식각저지막을 형성하는 공정, 상기 희생막을 리프팅법을 이용하여 일차적으로 일정 두께만큼 제거하는 공정, 상기 희생막의 제거에 따라 노출되는 상기 층간절연막 부위를 등방성식각하는 공정, 나머지 희생막을 완전히 제거하여 하층배선 표면을 노출시키는 콘택홀을 형성하는 공정, 상기 식각저지막을 제거하는 공정, 상기 층간절연막 상부에 상기 콘택홀을 통해 상기 하층배선과 연결되는 상층배선을 형성하는 공정으로 이루어진다.The present invention provides a process for forming a lower layer wiring over an insulating film formed on a semiconductor substrate, and optionally forming a sacrificial film only over a predetermined portion of the lower layer wiring. Forming a etch stop film on the interlayer insulating film, removing the sacrificial film by a predetermined thickness using a lifting method, and isotropically etching the interlayer insulating film portion exposed by removing the sacrificial film; Forming a contact hole exposing the surface of the lower layer wiring by completely removing the remaining sacrificial layer, removing the etch stop layer, and forming an upper layer wiring connected to the lower layer wiring through the contact hole on the interlayer insulating layer. Is done.
Description
제1도는 종래의 다층배선 형성방법을 도시한 공정 순서도1 is a process flowchart showing a conventional method for forming a multilayer wiring.
제2도는 본 발명에 의한 다층배선 형성방법을 도시한 공정 순서도2 is a process flowchart showing a method for forming a multilayer wiring according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:반도체기판 2:절연막1: semiconductor substrate 2: insulating film
3:제1층배선 11:제2층배선3: first layer wiring 11: second layer wiring
12:포토레지스트패턴 13:층간절연막12: photoresist pattern 13: interlayer insulating film
14:식각저지막 15:슬로프14: etching stop 15: slope
16:콘택홀16: contact hole
본 발명은 다층배선 형성방법에 관한 것으로, 특히 포토레지스트 리프팅(lifting)법을 이용한 다층배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming multilayer wirings, and more particularly, to a method for forming multilayer wirings using a photoresist lifting method.
종래의 반도체 장치의 다층배선 형성방법을 제1도를 참조하여 설명하면 다음과 같다.A method of forming a multilayer wiring of a conventional semiconductor device will be described below with reference to FIG.
먼저, 제1도 (a)와 같이 실리콘기판(1)상에 BPSG(Borophospho-silicate Glass)와 같은 제1층간절연막(2)을 형성한 후, 이위에 알루미늄 또는 알루미늄합금과 같은 도전물질을 물리증착 방법으로 증착한 다음 사진식각공정에 의해 소정패턴으로 패터닝하여 1층 배선(3)을 형성한다.First, as shown in FIG. 1A, a first interlayer insulating film 2 such as BPSG (Borophospho-silicate Glass) is formed on the silicon substrate 1, and then a conductive material such as aluminum or an aluminum alloy is formed thereon. After depositing by a deposition method, a single-layer wiring 3 is formed by patterning a predetermined pattern by a photolithography process.
이어서 제1도 (b)와 같이 상기 1층배선(3)이 형성된 제1층간절연막(2) 전면에 제2층간절연막(4)을 형성하고, 이어서 제1도 (c)와 같이 상기 제2층간절연막(2)상에 제2층간절연막과의 식각선택비가 크고, 그 표면이 평탄하게 형성되는 물질로서, 예컨대 포토레지스트를 도포하여 희생막(5)을 형성한다.Subsequently, a second interlayer insulating film 4 is formed on the entire surface of the first interlayer insulating film 2 on which the first layer wiring 3 is formed, as shown in FIG. 1B, and then, as shown in FIG. A sacrificial film 5 is formed by applying a photoresist as a material having a large etching selectivity with the second interlayer insulating film and having a flat surface on the interlayer insulating film 2.
다음에 제1도 (d)와 같이 상기 희생막(5)을 플라즈마 식각법에 의해 에치백 하는바, 이때, 제2층간절연막(4)이 희생막(5)보다 식각이 잘되게 하거나 최소한 제2층간절연막과 희생막의 식각률이 동일하도록 삭각을 행한다. 즉, 희생막(5)으로 사용되는 포토레지스트는 산소와 반응하며 제2층간절연막은 CHF3,CF4등과 반응하여 식각이 이루어지므로 가스유량을 조절함으로써 식각선택비를 쉽게 조절할 수 있다.Next, as shown in FIG. 1 (d), the sacrificial film 5 is etched back by plasma etching. At this time, the second interlayer insulating film 4 is better etched than the sacrificial film 5 or at least a second layer. The etching is performed so that the etching rates of the interlayer insulating film and the sacrificial film are the same. That is, since the photoresist used as the sacrificial film 5 reacts with oxygen and the second interlayer insulating film reacts with CHF 3, CF 4, etc. , etching is performed to easily control the etching selectivity by adjusting the gas flow rate.
이와 같이 에치백 공정에 의해 희생막을 식각하게 되면 남겨진 제2층간절연막(4)의 두께가 1층배선(3)상에서는 얇아지게 되므로 배선간의 기생커패시턴스를 줄이기 위해 다시 제3층간절연막(6)을 제2층간절연막(4)상에 형성한다.When the sacrificial film is etched by the etch back process as described above, the remaining thickness of the second interlayer insulating film 4 becomes thinner on the one-layer wiring 3, so that the third interlayer insulating film 6 is removed again to reduce parasitic capacitance between wirings. It is formed on the interlayer insulating film 4.
이어서 제1도 (e)와 같이 제3층간절연막(6)상에 포토레지스트로 된 마스크층(8)을 형성한 후, 제1도 (f)와 같이 상기 포토레지스트 마스크층(8)을 마스크로 하여 상기 제3층간절연막(6) 및 제2층간절연막(4)을 등방성식각하고 이어서 이방성식각하여 상부에 슬로프(slope)(9)를 갖는 콘택홀(10)을 형성한다.Subsequently, a mask layer 8 made of photoresist is formed on the third interlayer insulating film 6 as shown in FIG. 1E, and then the photoresist mask layer 8 is masked as shown in FIG. In this case, the third interlayer insulating film 6 and the second interlayer insulating film 4 are isotropically etched and subsequently anisotropically etched to form a contact hole 10 having a slope 9 thereon.
다음에 제1도 (f)와 같이 상기 포토레지스트 마스크층을 제거한 후, 전면에 알루미늄, 알루미늄합금 또는 금속적층막등의 도전물질을 물리증착 방법으로 증착하고 패터닝하여 상기 콘택홀을 통해 1층배선(3)과 접속하는 2층배선(11)을 형성한다.Next, after removing the photoresist mask layer as shown in FIG. 1 (f), a conductive material such as aluminum, an aluminum alloy, or a metal laminated film is deposited on the entire surface by physical vapor deposition and patterned to form a single layer wiring through the contact hole. The two-layer wiring 11 connected with (3) is formed.
상기 콘택홀(10) 상부의 슬로프(9)에 의해 2층배선 형성시의 스텝커버리지(step coverage)가 향상된다.The step 9 in forming the two-layer wiring is improved by the slope 9 of the upper portion of the contact hole 10.
이상과 같이 종래의 다층배선 형성방법은 1층배선과 2층배선을 상호 연결하기 위한 콘택홀을 형성하기 위해 평탄화 공정후 사진식각공정이 요구되므로 공정이 복잡하고 공정에 소요되는 시간이 많이 걸린다.As described above, the conventional multilayer wiring forming method requires a photolithography process after the planarization process to form contact holes for interconnecting the 1-layer wiring and the 2-layer wiring, which is complicated and takes a long time.
또한 사진식각공정후에 식각마스크층으로 사용된 포토레지스트가 식각물과의 반응에 의해 생성된 반응 잔유물이 포토레지스트 제거후에도 남게 되어 표면을 오염시키는 문제가 있다.In addition, the photoresist used as an etching mask layer after the photolithography process has a problem that the reaction residues generated by the reaction with the etching remains after the photoresist removal, thereby contaminating the surface.
이와 같은 오염물은 금속배선의 전기적 특성 및 신뢰성을 열화시키므로 이를 제거하기 위한 엄격한 세정공정이 요구되게 된다.Such contaminants deteriorate the electrical characteristics and reliability of the metallization, and therefore, a strict cleaning process is required to remove them.
본 발명은 상술한 문제를 해결하기 위한 것으로, 에치백 공정없이 층간절연막 평탄화 및 콘택홀 형성을 동시에 이룰수 있는 다층배선 형성방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming a multi-layered wiring which can simultaneously form an interlayer insulating film and form a contact hole without an etch back process.
상기 목적을 달성하기 위한 본 발명의 다층배선 형성방법은 반도체 기판상에 형성된 절연막 상부에 하층배선을 형성하는 공정과, 상기 하층배선의 소정부분 상부에만 선택적으로 희생막을 형성하는 공정, 결과물 전면에 상기 희생막의 두께보다 얇은 두께로 층간절연막을 형성하는 공정, 상기 층간절연막상에 식각저지막을 형성하는 공정, 상기 희생막을 리프팅법을 이용하여 일차적으로 일정 두께만큼 제거하는 공정, 상기 희생막의 제거에 따라 노출되는 상기 층간절연막 부위를 등방성식각하는 공정, 나머지 희생막을 완전히 제거하여 하층배선 표면을 노출시키는 콘택홀을 형성하는 공정, 상기 식각저지막을 제거하는 공정, 상기 층간절연막 상부에 상기 콘택홀을 통해 상기 하층배선과 연결되는 상층배선을 형성하는 공정으로 이루어진다.The multi-layered wiring forming method of the present invention for achieving the above object is a step of forming a lower layer wiring on the insulating film formed on the semiconductor substrate, a step of selectively forming a sacrificial film only on a predetermined portion of the lower layer wiring, the front surface of the result Forming an interlayer insulating film having a thickness thinner than that of the sacrificial film, forming an etch stop film on the interlayer insulating film, first removing the sacrificial film by a predetermined thickness by using a lifting method, and exposing the sacrificial film by exposure. Isotropically etching the interlayer insulating film portion, forming a contact hole exposing the surface of the lower layer wiring by completely removing the remaining sacrificial film, removing the etch stop layer, and forming the lower layer through the contact hole on the interlayer insulating film. The upper layer wiring is connected to the wiring.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 다층배선 형성방법을 공정 순서에 따라 도시하였다.2 shows a method for forming a multilayer wiring according to the present invention according to the process sequence.
먼저, 제2도 (a)와 같이 반도체 기판(1)상에 BPSG(Borophospho-silicate Glass)와 같은 절연막(2)을 형성한 후, 이위에 알루미늄 또는 알루미늄합금과 같은 도전물질을 물리증착 방법으로 증착한 다음 사진식각공정에 의해 소정패턴으로 패터닝하여 하층배선이 되는 제1층배선(3)을 형성한다.First, as shown in FIG. 2 (a), an insulating film 2 such as borophospho-silicate glass (BPSG) is formed on the semiconductor substrate 1, and then a conductive material such as aluminum or an aluminum alloy is physically deposited thereon. After the deposition, the pattern is formed into a predetermined pattern by a photolithography process to form a first layer wiring 3 that becomes an underlayer wiring.
다음에 제2도 (b)와 같이 상층배선이 연결된 부분의 제1층배선(3) 상에만 희생막으로서, 예컨대 포토레지스트패턴(12)을 선택적으로 형성한다.Next, as shown in FIG. 2B, the photoresist pattern 12 is selectively formed as a sacrificial film only on the first layer wiring 3 of the portion where the upper layer wiring is connected.
이어서 제2도 (c)와 같이 기판 전면에 층간절연막(13)으로서, 저압화학기상 증착방법을 이용하여 200℃ 미만의 저온에서 PE-TEOS(Plasama Enhanced Triethyleorthosilicate)막을 형성한다. 이때, PE-TEOS막 형성공정은 증착 온도가 200℃ 미만의 저온에서 진행되기 때문에 포토레지스트패턴(12)에 전혀 지장을 주지 않는다. 또한 PE-TEOS막의 두께(t)는 포토레지스트패턴(12) 두께보다 얇게 형성하되 배선간 기생커패시턴스를 무시할 수 있을 정도의 두께, 예컨대 3000Å-15000Å 정도로 형성한다.Subsequently, as shown in FIG. 2C, as an interlayer insulating film 13, a PE-TEOS (Plasama Enhanced Triethyleorthosilicate) film is formed at a low temperature of less than 200 ° C. using a low pressure chemical vapor deposition method. At this time, the PE-TEOS film forming process does not affect the photoresist pattern 12 at all because the deposition temperature is performed at a low temperature of less than 200 ℃. In addition, the thickness t of the PE-TEOS film is formed to be thinner than the thickness of the photoresist pattern 12, but the thickness t is such that the parasitic capacitance between wirings can be neglected, for example, about 3000 kV to 15000 kPa.
다음에 식각저지막으로서, 예컨대 플라즈마 방전에 의해 질화막으로 형성된 식각저지막(14)을 상기 PE-TEOS로 구성된 층간절연막(13)상에 형성하되, 200℃ 미만의 저온에서 수백Å 정도의 두께로 얇게 형성하여 포토레지스트패턴(12)에 영향을 미치지 않도록 한다. 상기 식각저지막으로 폴리실리콘층을 이용할 수도 있다.Next, as an etch stop film, an etch stop film 14 formed of a nitride film by plasma discharge, for example, is formed on the interlayer insulating film 13 made of PE-TEOS, and has a thickness of about several hundred micrometers at a low temperature of less than 200 ° C. The thin film is formed so as not to affect the photoresist pattern 12. A polysilicon layer may be used as the etch stop layer.
이어서 제2도 (d)에 도시된 바와 같이 산소분위기에서 상기 포토레지스트패턴(12)을 리프팅법으로 1차적으로 일정두께(후에 형성될 콘택홀 상부의 슬로프 높이에 해당하는 두께) 제거한 후, 이에 따라 노출되는 상기 PE-TEOS로 구성된 층간절연막(13) 부분을 등방성식각한 다음 나머지 포토레지스트패턴을 완전히 제거하게 되면 상부에 슬로프(15)가 형성된 콘택홀(16)이 형성되게 된다.Subsequently, as shown in FIG. 2 (d), the photoresist pattern 12 is first removed by a lifting method in an oxygen atmosphere (thickness corresponding to the slope height of an upper portion of the contact hole to be formed later). After the isotropic etching of the portion of the interlayer insulating layer 13 formed of the PE-TEOS and completely removing the remaining photoresist pattern, the contact hole 16 having the slope 15 formed thereon is formed.
다음에 제2도 (e)와 같이 상기 질화막(14)을 CF4, CHF3등의 가스분위기에서 플라즈마 에칭법을 사용하여 제거한 후, 결과물 전면에 알루미늄, 알루미늄합금 또는 금속적층막등의 도전물질을 물리증착하고 패터닝하여 상기 콘택홀을 통해 상기 제1층배선(3)과 연결되는 상층배선인 제2층배선(11)을 형성함으로써 다층배선 형성공정을 완료한다.Next, as shown in FIG. 2 (e), the nitride film 14 is removed using a plasma etching method in a gas atmosphere such as CF 4 or CHF 3, and then a conductive material such as aluminum, an aluminum alloy or a metal laminated film is formed on the entire surface of the resultant product. Physically depositing and patterning the second layer wiring 11, which is an upper layer wiring connected to the first layer wiring 3 through the contact hole, to complete the multilayer wiring forming process.
이상과 같은 본 발명에 의한 다층배선 형성방법은 에치백 공정없이 층간절연막의 평탄화와 콘택홀 형성을 동시에 이룰수 있으므로 종래 방법에 비해 공정이 단순화되고 공정시간이 짧아진다.As described above, the method for forming a multilayer wiring according to the present invention can simultaneously planarize an insulating film and form a contact hole without an etch back process, which simplifies the process and shortens the process time compared with the conventional method.
또한 종래의 에치백 공정을 위한 포토레지스트 도포 및 제거공정이 없어지므로 식각반응 잔유물을 제거하기 위한 세정공정도 필요없게 되어 공정이 단순화되고 재료가 절감되는 효과를 얻을 수 있으며, 배선간의 연결을 위한 콘택홀을 포토레지스트패턴을 이용하여 층간절연막 형성전에 미리 형성하므로 미세선폭의 고집적소자에 적합하다.In addition, since the photoresist coating and removal process for the conventional etch back process is eliminated, there is no need for the cleaning process for removing the residues of the etching reaction, which simplifies the process and saves the material. Since the hole is formed before the interlayer insulating film is formed by using the photoresist pattern, it is suitable for a high integration device having a fine line width.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016638A KR0144247B1 (en) | 1994-07-11 | 1994-07-11 | Forming method of multi-layer wiring |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940016638A KR0144247B1 (en) | 1994-07-11 | 1994-07-11 | Forming method of multi-layer wiring |
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| KR0144247B1 true KR0144247B1 (en) | 1998-08-17 |
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